diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README b/boards/uniboard2a/designs/unb2a_minimal/doc/README index ffe3dbfd1845c605a3ac20af781d7ef4b73aefe6..2dc9894b76f17103a09cf0c2dd1ad89c48cd7965 100644 --- a/boards/uniboard2a/designs/unb2a_minimal/doc/README +++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README @@ -33,8 +33,8 @@ Modelsim instructions: run 500us # while the simulation runs... in another bash session do: - cd unb2a_minimal/tb/python - python tc_unb2a_minimal.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS + cd $UPE/peripherals + python util_unb2.py --sim --unb 0 --fn 3 --seq INFO,SENSORS # (sensor results only show up after 1000us of simulation runtime) @@ -48,7 +48,7 @@ Quartus instructions: run_qcomp unb2a unb2a_minimal -In case of needing the Quartus GUI for inspection: +In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1 GUI): run_quartus unb2a @@ -56,8 +56,8 @@ In case of needing the Quartus GUI for inspection: 4. Load firmware ---------------- Using JTAG: Start the Quartus GUI and open: tools->programmer. - Then click auto-detect; - Use 'change file' to select the correct .sof file for each FPGA + Then click auto-detect; (click 4x ok) + Use 'change file' to select the correct .sof file (in $RADIOHDL/build/unb2a/quartus/unb2a_minimal) for each FPGA Select the FPGA(s) which has to be programmed Click 'start' Using EPCS: See step 6 below. @@ -70,11 +70,12 @@ Using EPCS: See step 6 below. Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected LCU computer. -# (assume that the Uniboard is --unb 1) +# (assume that the Uniboard is --unb 1 -> check the dipswitches or backpanel-slotnumber) -# To read out the design_name, ppsh and sensors; do: +# To read out the design_name and sensors; do: -python tc_unb2_minimal.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5 +cd $UPE/peripherals +python util_unb2.py --unb 1 --fn 0:3 --seq REGMAP,INFO,SENSORS @@ -88,21 +89,22 @@ Firstly a JIC file has to be generated from the SOF file. In Quartus GUI; open current project; File -> Convert Programming Files. Then setup: - Output programming file: JIC +- Set the output filename to: unb2a_minimal.jic - Configuration device: EPCQL1024 - Mode: Active Serial x4 -- Flash Loader: Add/Select Device Arria10/10AX115U4ES +- Flash Loader: Add/Select Device Arria10/10AX115U4E3 - SOF Data: add file (the generated .sof file) - click the .sof file; Set property 'Compression' to ON - Press 'Generate' -Then program the .JIC file (output_file.jic) to EPCS flash: +Then program the .JIC file (unb2a_minimal.jic) to EPCS flash: - Make sure that the JTAG (on server connected to board) runs at 16MHz: c:\altera\15.0\quartus\bin64\jtagconfig USB-BlasterII JtagClock 16M - open tools->programmer - make sure the 4 fpga icons have the device 10AX115U4F45E3 - right-click each fpga icon and attach flash device EPCQL1024 - optional see (*1) -- right-click each EPCQL1024 and change file from <none> to output_file.jic +- right-click each EPCQL1024 and change file from <none> to unb2a_minimal.jic - select click each Program/Configure radiobutton - click start and wait for 'Successful'