From 0f281a6d8b70df1d23cf8c8f639920efe2f0a11b Mon Sep 17 00:00:00 2001 From: Leon Hiemstra <hiemstra@astron.nl> Date: Tue, 13 Jan 2015 15:27:39 +0000 Subject: [PATCH] svn copied from tb_unb2_board_clk25_pll.vhd and modified --- .../tb/vhdl/tb_unb2_board_clk125_pll.vhd | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd new file mode 100644 index 0000000000..13f29d9191 --- /dev/null +++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + + +-- Purpose: Simulate phase behaviour of PLL in normal mode +-- Description: +-- Usage: +-- > as 3 +-- > run -all + +LIBRARY IEEE, common_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; + + +ENTITY tb_unb2_board_clk125_pll IS +END tb_unb2_board_clk125_pll; + + +ARCHITECTURE tb OF tb_unb2_board_clk125_pll IS + + CONSTANT c_ext_clk_period : TIME := 8 ns; -- 125 MHz + + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL ext_clk : STD_LOGIC := '0'; + SIGNAL ext_rst : STD_LOGIC; + SIGNAL c0_clk20 : STD_LOGIC; + SIGNAL c1_clk50 : STD_LOGIC; + SIGNAL c2_clk100 : STD_LOGIC; + SIGNAL c3_clk125 : STD_LOGIC; + SIGNAL pll_locked : STD_LOGIC; + +BEGIN + + tb_end <= '0', '1' AFTER c_ext_clk_period*5000; + + ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2; + ext_rst <= '1', '0' AFTER c_ext_clk_period*7; + + dut_0 : ENTITY work.unb2_board_clk125_pll + PORT MAP ( + arst => ext_rst, + clk125 => ext_clk, + + c0_clk20 => c0_clk20, + c1_clk50 => c1_clk50, + c2_clk100 => c2_clk100, + c3_clk125 => c3_clk125, + + pll_locked => pll_locked + ); +END tb; -- GitLab