From 0e667d93d46350b568b18cdfd967384b06671fd0 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Mon, 4 May 2015 11:33:01 +0000
Subject: [PATCH] Changed path of ddr3 constraints file Added
modelsim_compile_ip_files key
---
.../apertif_unb1_fn_beamformer_transpose/hdllib.cfg | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
index 31ec400daa..b962140729 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
@@ -26,12 +26,15 @@ quartus_qsf_files =
quartus_tcl_files =
apertif_unb1_fn_beamformer_trans_pins.tcl
- apertif_unb1_fn_beamformer_trans_pin_constraints.tcl
+ ../../quartus/apertif_unb1_fn_beamformer_ddr3_pin_constraints.tcl
../../quartus/apertif_unb1_bf_constraints.tcl
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_trans/sopc_apertif_unb1_fn_beamformer.qip
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
--
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