From 0e2b10465c798914cbc7210189601433153ef012 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 13 Aug 2015 15:00:14 +0000
Subject: [PATCH] using a dual rank DDR4 but the IP is single rank: disabling
2nd rank by setting CS1_n=1, CKE1=0 and ODT1=0
---
libraries/technology/ddr/tech_ddr_arria10.vhd | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/libraries/technology/ddr/tech_ddr_arria10.vhd b/libraries/technology/ddr/tech_ddr_arria10.vhd
index 5f519faad8..e2e2f555cd 100644
--- a/libraries/technology/ddr/tech_ddr_arria10.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10.vhd
@@ -90,6 +90,11 @@ BEGIN
ctlr_gen_rst <= NOT ctlr_gen_rst_n;
gen_ip_arria10_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
+
+ phy_ou.cs_n(1) <= '1';
+ phy_ou.cke(1) <= '0';
+ phy_ou.odt(1) <= '0';
+
u_ip_arria10_ddr4_4g_1600 : ip_arria10_ddr4_4g_1600
PORT MAP (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
--
GitLab