From 0d4b4b1baf8fedd4812e64786df6077ebb57ab0f Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Thu, 24 Jun 2021 16:00:38 +0200
Subject: [PATCH] improved description of dp_fifo_core_arr
---
.../base/dp/src/vhdl/dp_fifo_core_arr.vhd | 27 +++++++++----------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index bf5fcd921e..83964e22b6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -26,24 +26,22 @@
-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
-- Description:
--- Provide the sink ready for FIFO write control and use source ready for
--- FIFO read access. The sink ready output is derived from FIFO almost full.
--- Data without framing can use g_use_ctrl=FALSE to avoid implementing two
--- data bits for sop and eop in the FIFO word width. Idem for g_use_sync,
--- g_use_empty, g_use_channel, g_use_error and g_use_aux.
+-- Similar to dp_fifo_core but for multiple synchronous inputs. All data fields
+-- of the in sosi's are concatenated in addition to the the control signals of
+-- in_sosi_arr(0) and in_aux. So the control signals of in_sosi_arr(1 TO g_nof_streams-1)
+-- are not used. It is useful to have dp_fifo_core_arr to ensure that all inputs
+-- are crossed over to the rd_clk domain on the same clock cycle, this cannot
+-- be guaranteed when using multiple dp_fifo_core instances. For single clock,
+-- dp_fifo_core_arr is also useful as it saves logic on the control signals since
+-- it only uses the control signals of in_sosi_arr(0).
-- Remark:
--- . The bsn, empty, channel and error fields are valid at the sop and or eop.
--- Therefore alternatively these fields can be passed on through a separate
--- FIFO, with only one entry per frame, to save FIFO memory in case
--- concatenating them makes the FIFO word width larger than a standard
--- memory data word width.
--- . The FIFO makes that the src_in.ready and snk_out.ready are not
--- combinatorially connected, so this can ease the timing closure for the
--- ready signal.
+-- . dp_fifo_core_arr is not built on top of dp_fifo_core as the input of dp_fifo_core
+-- is of type t_dp_sosi which has a limited size and could cause issues when concatenating
+-- multiple input streams.
-- . It is assumed all inputs are synchronous (identical control signals).
-- If the inputs are asynchronous, better use multiple instances of
-- dp_fifo_core.
--- . It is possible to use additonal signals to the fifo using in_aux/out_aux.
+-- . It is possible to add additonal signals to the fifo using in_aux/out_aux.
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -307,5 +305,4 @@ BEGIN
src_out => out_aux_sosi
);
-
END str;
--
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