diff --git a/applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd b/applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd index 633e438aa549b41700a6f75fe7dc54e38d39546a..cd1f937417372c2822f7b4cf770bb80243d4d4e4 100644 --- a/applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd +++ b/applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd @@ -47,13 +47,16 @@ ARCHITECTURE tb OF tb_apertif_unb1_correlator IS CONSTANT c_cable_delay : TIME := 12 ns; CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard + CONSTANT c_sa_clk_period : TIME := 6.4 ns; CONSTANT c_clk_period : TIME := 5 ns; CONSTANT c_pps_period : NATURAL := 1000; + -- DUT SIGNAL clk : STD_LOGIC := '0'; SIGNAL pps : STD_LOGIC := '0'; SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL sa_clk : STD_LOGIC := '1'; SIGNAL WDI : STD_LOGIC; SIGNAL INTA : STD_LOGIC; @@ -69,6 +72,7 @@ ARCHITECTURE tb OF tb_apertif_unb1_correlator IS SIGNAL sens_scl : STD_LOGIC; SIGNAL sens_sda : STD_LOGIC; + SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0'); BEGIN @@ -77,6 +81,7 @@ BEGIN ---------------------------------------------------------------------------- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz) eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz) + sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; INTA <= 'H'; -- pull up INTB <= 'H'; -- pull up @@ -117,7 +122,16 @@ BEGIN -- 1GbE Control Interface ETH_clk => eth_clk, ETH_SGIN => eth_rxp, - ETH_SGOUT => eth_txp + ETH_SGOUT => eth_txp, + + -- Transceiver clocks + SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN + + -- Serial I/O + SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_3_RX => si_fn_0_tx -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); ); END tb;