diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 679210d1ddda08b94d2e9f0ec1435b9d2fdd7eb4..e304cb76f09e0de3642aaa62e362e89536be3aca 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -133,7 +133,110 @@ PACKAGE tech_ddr_component_pkg IS
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-
+
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
+ PORT (
+ pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
+ global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
+ soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
+ afi_clk : OUT STD_LOGIC; -- afi_clk.clk
+ afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
+ afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
+ mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a
+ mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
+ mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
+ mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
+ mem_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cke
+ mem_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cs_n
+ mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
+ mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
+ mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
+ mem_we_n : OUT STD_LOGIC; -- .mem_we_n
+ mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
+ mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
+ mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
+ mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
+ mem_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_odt
+ avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
+ avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
+ avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
+ avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
+ avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
+ avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
+ avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
+ avl_read_req : IN STD_LOGIC; -- .read
+ avl_write_req : IN STD_LOGIC; -- .write
+ avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
+ local_init_done : OUT STD_LOGIC; -- status.local_init_done
+ local_cal_success : OUT STD_LOGIC; -- .local_cal_success
+ local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
+ oct_rdn : IN STD_LOGIC; -- oct.rdn
+ oct_rup : IN STD_LOGIC; -- .rup
+ seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
+ pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
+ pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
+ pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
+ pll_locked : OUT STD_LOGIC; -- .pll_locked
+ pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
+ pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
+ dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
+ );
+ END COMPONENT;
+
+ -- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
+ COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
+ PORT (
+ pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
+ global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
+ soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
+ afi_clk : OUT STD_LOGIC; -- afi_clk_in.clk
+ afi_half_clk : OUT STD_LOGIC; -- afi_half_clk_in.clk
+ afi_reset_n : OUT STD_LOGIC; -- afi_reset_in.reset_n
+ mem_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- memory.mem_a
+ mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
+ mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
+ mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
+ mem_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cke
+ mem_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cs_n
+ mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
+ mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
+ mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
+ mem_we_n : OUT STD_LOGIC; -- .mem_we_n
+ mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
+ mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
+ mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
+ mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
+ mem_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_odt
+ avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
+ avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
+ avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
+ avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
+ avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
+ avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
+ avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
+ avl_read_req : IN STD_LOGIC; -- .read
+ avl_write_req : IN STD_LOGIC; -- .write
+ avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
+ local_init_done : OUT STD_LOGIC; -- status.local_init_done
+ local_cal_success : OUT STD_LOGIC; -- .local_cal_success
+ local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
+ seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
+ pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
+ pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
+ pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
+ pll_locked : OUT STD_LOGIC; -- .pll_locked
+ pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
+ pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
+ dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
+ );
+ END COMPONENT;
+
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 75060c7780dab1a7169f274c8759026f17cc61db..5b0d7ab2caf8ee08f71e162cc9d6e94313d690f4 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -33,6 +33,7 @@ PACKAGE tech_ddr_pkg IS
name : STRING(1 TO 4); -- = "DDR3" or "DDR4"
mts : NATURAL; -- = 800 access rate in mega transfers per second
master : BOOLEAN; -- = TRUE TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
+ rank : STRING(1 TO 6); -- = "SINGLE" or "DUAL "
-- PHY external FPGA IO
a_w : NATURAL; -- = 16
a_row_w : NATURAL; -- = 16 = a_w, row address width, via a_w lines
@@ -65,14 +66,16 @@ PACKAGE tech_ddr_pkg IS
FUNCTION func_tech_ddr_ctlr_data_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR data width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_module_size( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR module size in GByte
- -- a a
- -- a row col ba dq dqs dm dbi bg ck cke cs cs_w odt rsl
- CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- maximum ranges for record field definitions
- CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
- CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
+ -- a a
+ -- name mts master rank a row col ba dq dqs dm dbi bg ck cke cs cs_w odt term rsl rsl_w cqd burst burst_w
+ CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- maximum ranges for record field definitions
+ CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
+ CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "DUAL ", 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
+ CONSTANT c_tech_ddr3_4g_single_rank_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 2, 1, 1, 2, 14, 4, 2, 4, 64, 7);
+ CONSTANT c_tech_ddr3_4g_single_rank_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, "SINGLE", 16, 16, 10, 3, 64, 8, 8, 0, 0, 2, 2, 1, 1, 2, 14, 4, 2, 4, 64, 7);
- CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
- CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
+ CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
+ CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, "DUAL ", 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
-- PHY in, inout and out signal records
TYPE t_tech_ddr3_phy_in IS RECORD -- DDR3 Description
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index b1e1995c3970feb94ccf911592d50a8719c0d1ac..8c0a9fe68cdb2744a6b27bb8200297b1caf54b61 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -33,6 +33,8 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
+LIBRARY ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib;
+LIBRARY ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib;
LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -88,7 +90,7 @@ BEGIN
ref_rst_n <= NOT ref_rst;
- gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE AND g_tech_ddr.rank="DUAL " GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -140,7 +142,7 @@ BEGIN
);
END GENERATE;
- gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE GENERATE
+ gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE AND g_tech_ddr.rank="DUAL " GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP (
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
@@ -190,6 +192,108 @@ BEGIN
);
END GENERATE;
+ gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE AND g_tech_ddr.rank="SINGLE" GENERATE
+ u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_master : ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ PORT MAP (
+ pll_ref_clk => ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ref_rst_n, -- global_reset.reset_n
+ soft_reset_n => '1', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctlr_mosi.rd, -- .read
+ avl_write_req => ctlr_mosi.wr, -- .write
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_miso.done, -- status.local_init_done
+ local_cal_success => ctlr_miso.cal_ok, -- .local_cal_success
+ local_cal_fail => ctlr_miso.cal_fail, -- .local_cal_fail
+ oct_rdn => phy_in.oct_rdn, -- oct.rdn
+ oct_rup => phy_in.oct_rup, -- .rup
+ seriesterminationcontrol => term_ctrl_out.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => term_ctrl_out.parallelterminationcontrol, -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ );
+ END GENERATE;
+
+ gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE AND g_tech_ddr.rank="SINGLE" GENERATE
+ u_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+ PORT MAP (
+ pll_ref_clk => ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ref_rst_n, -- global_reset.reset_n
+ soft_reset_n => '1', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst_n, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctlr_miso.rdval, -- .readdatavalid
+ avl_rdata => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctlr_mosi.rd, -- .read
+ avl_write_req => ctlr_mosi.wr, -- .write
+ avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_miso.done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ seriesterminationcontrol => term_ctrl_in.seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => term_ctrl_in.parallelterminationcontrol, -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ );
+ END GENERATE;
+
i_ctlr_gen_rst <= NOT ctlr_gen_rst_n;
u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async