diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index a4a417b9d6bc87db60d36b041f8da2cb5a0dfdb5..fe98500495006326667ac23624190a2ca3e8834d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -16,13 +16,14 @@ parameters:
- { name: c_Q_fft, value: 2 }
- { name: c_P_sq, value: 1 + c_N_pn_lb // 2 } # = 1 + 16 // 2 = 9, on revision xsub_one only first X_sq cell is used
- { name: c_X_sq, value: c_S_pn * c_S_pn } # = 144
- - { name: c_N_crosslets, value: 1 }
+ - { name: c_N_crosslets, value: 7 }
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
+ - { name: c_V_si_histogram, value: 512 }
- { name: c_W_fir_coef, value: 16 }
- { name: c_W_subband, value: 18 }
- { name: c_P_pfb, value: c_S_pn / c_Q_fft } # = 6
@@ -141,7 +142,15 @@ peripherals:
mm_port_names:
- REG_WG
- RAM_WG
-
+
+ - peripheral_name: st/st_histogram
+ parameter_overrides:
+ - { name: g_nof_instances, value: c_S_pn }
+ - { name: g_nof_bins, value: c_V_si_histogram }
+ - { name: g_nof_data_per_sync, value: c_nof_clk_per_pps}
+ mm_port_names:
+ - RAM_ST_HISTOGRAM
+
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -213,15 +222,11 @@ peripherals:
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
-
- - peripheral_name: dp/dp_bsn_scheduler
+
+ - peripheral_name: dp/dp_bsn_sync_scheduler
peripheral_group: xsub
mm_port_names:
- - REG_BSN_SCHEDULER_XSUB
-
- - peripheral_name: dp/dp_sync_insert_v2
- mm_port_names:
- - REG_DP_SYNC_INSERT_V2
+ - REG_BSN_SYNC_SCHEDULER_XSUB
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
@@ -234,6 +239,10 @@ peripherals:
mm_port_names:
- REG_CROSSLETS_INFO
+ - peripheral_name: sdp/sdp_nof_crosslets
+ mm_port_names:
+ - REG_NOF_CROSSLETS
+
- peripheral_name: common/common_variable_delay
peripheral_group: xst
mm_port_names:
@@ -243,6 +252,7 @@ peripherals:
peripheral_group: xst
mm_port_names:
- REG_STAT_HDR_DAT_XST
+
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
index c7072a387e9f36455e7ba506a9782446f68b0f4e..5667d08a041be549cadabfb3df52ffe4ba172af0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
@@ -18,463 +18,523 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
- - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
- - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
- - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
- - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
- - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG beamlet_scale 0x0001c000 1 RW uint32 b[15:0] - - -
- - - - - block_period 0x0001c001 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0001c002 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0001c003 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0001c004 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0001c005 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0001c006 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0001c007 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0001c008 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0001c009 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0001c00a 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0001c00b 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0001c00c 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
- JESD204B 1 1 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
- - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
- - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
- - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
- - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00030001 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00030003 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - - 1024
- REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00042001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0004a002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0004a006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x0004a007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004a00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004a010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0004a011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0004a012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0004a013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0004a014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0004a015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0004a016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0004a017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0004a018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0004a019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0004a01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004a01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004a01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004a01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004a01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004a01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004a020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0004a021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0004a022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0004a023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0004a024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0004a025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0004a026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0004a027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
- REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0004c000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004c001 - - - b[31:0] b[63:32] - -
- REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0004e000 1 RW uint32 b[31:0] - - -
- RAM_ST_XSQ 1 1 RAM data 0x00050000 576 RW cint64_ir b[31:0] b[31:0] - -
- - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00052000 15 RW uint32 b[31:0] - - -
- - - - - step 0x0005200f 1 RW uint32 b[31:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x00054000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00058000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x00060000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00060001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00062001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00062002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00062003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00062004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00062005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00062006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00062007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00062008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0006200a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0006200b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0006200c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0006200d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0006200e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0006200f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00062010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00062011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00062012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00062013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00062014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00062015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00062016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00062017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00062018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00062019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0006201a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0006201b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0006201c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0006201d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0006201e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0006201f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00062020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00062021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00062022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00062023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00062024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00062025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00062026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00062027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00062028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00062029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00064000 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00066000 1952 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x00064001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00068000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0006a000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x0006a001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x0006a002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x0006a003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x0006a004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x0006a005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0006a006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x0006a006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x0006a006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x0006a007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0006a008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0006a009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0006a00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0006a00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0006a00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0006a00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0006a00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0006a00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0006a010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0006a011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0006a012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0006a013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0006a014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0006a015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0006a016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0006a017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0006a018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0006a019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0006a01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0006a01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0006a01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0006a01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0006a01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0006a01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0006a020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0006a021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0006a022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0006a023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0006a024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0006a025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0006a026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0006a027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006a028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0006a029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0006a02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0006a02b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x0006c000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x0006c001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x0006c002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x0006c040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x0006c080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x0006c0c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006c0c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x0006c0c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006c0c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x0006c100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x0006c140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x0006c800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x0006c801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x0006c802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x0006c803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x0006c804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x0006c805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x0006c806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x0006c807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x0006c808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x0006c809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0006c80a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0006c80b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x0006c818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x0006cc00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x0006cc02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x0006cc04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x0006cc06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x0006cc08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x0006cc0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x0006cc0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x0006cc0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x0006cc10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x0006cc12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x0006cc14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x0006cc16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x0006cc18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x0006cc1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x0006cc1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x0006cc1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x0006cc20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x0006cc22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x0006cc24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x0006cc26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x0006cc28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x0006cc2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x0006cc2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x0006cc2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x0006cc30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x0006cc32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x0006cc34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x0006cc36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x0006cc38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x0006cc3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x0006cc3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006cc3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x0006d001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x0006d040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x0006d080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x0006d0c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006d0c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x0006d100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x0006d140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x0006d141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x0006d142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x0006d180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x0006d181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x0006d182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x0006d183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x0006d184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x0006d185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x0006d186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x0006d187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x0006d190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x0006d191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x0006d192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x0006d193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x0006d194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x0006d195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x0006d196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x0006d197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x0006d1a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x0006d200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x0006d201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x0006d202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x0006d801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x0006dc00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x0006dc02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x0006dc04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x0006dc06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x0006dc08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x0006dc0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x0006dc0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x0006dc0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x0006dc10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x0006dc12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x0006dc14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x0006dc16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x0006dc18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x0006dc1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x0006dc1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x0006dc1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x0006dc20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x0006dc22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x0006dc24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x0006dc26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x0006dc28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x0006dc2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x0006dc2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x0006dc2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x0006dc30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x0006dc32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x0006dc34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x0006dc36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x0006dc38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x0006dc3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x0006dc3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x0006dc3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006e000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0006e000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0006e000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x0001c000 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c001 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c005 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c006 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c008 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c009 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00a 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x00030000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00032000 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00032001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00032002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00032003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[31:0] b[15:0] - 1024
+ REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00046000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00048000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00048001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0004c000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004e000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004e002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x0004e003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x0004e004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x0004e005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0004e006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x0004e006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x0004e006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x0004e007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0004e008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0004e009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004e00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0004e00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004e00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004e00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004e00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004e00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004e010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004e011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004e012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004e013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004e014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004e015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004e016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004e017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004e018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004e019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004e01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004e01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004e01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004e01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004e01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004e01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004e020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004e021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004e022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004e023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004e024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004e025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004e026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004e027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004e029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004e02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0004e02b 1 RW uint32 b[15:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00050000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00050001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00050002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00050004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00050006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00050007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00050008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00050009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005000a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00060000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00060001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00070000 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0007000f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00072000 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00072001 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00074000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00076001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00076006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00076006 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00076006 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00076006 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0007600a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0007600b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0007600c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0007600d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0007600e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0007600f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00076010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00076011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00076012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00076013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00076014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00076015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00076016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00076017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00076018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00076019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0007601a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0007601b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0007601c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0007601d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0007601e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0007601f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00076020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00076021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00076022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00076023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00076024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00076025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00076026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00076027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00076028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0007602a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00078000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x0007c000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00084000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00084001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00086000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00086001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00086002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00086003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00086004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00086005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00086006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00086007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00086009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0008600a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0008600b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0008600c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0008600d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0008600e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0008600f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00086010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00086011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00086012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00086013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00086014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00086015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00086016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00086017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00086018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00086019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0008601a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0008601b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0008601c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0008601d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0008601e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0008601f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00086020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00086021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00086022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00086023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00086024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00086025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00086026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00086028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00086029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00088000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x0008a000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x0008a001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0008c000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0008e000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0008e001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x0008e002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x0008e003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x0008e004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x0008e005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0008e006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x0008e006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x0008e006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x0008e007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0008e008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0008e009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0008e00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0008e00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0008e00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0008e00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0008e00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0008e00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0008e010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0008e011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0008e012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0008e013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0008e014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0008e015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0008e016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0008e017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0008e018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0008e019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0008e01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0008e01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0008e01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0008e01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0008e01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0008e01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0008e020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0008e021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0008e022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0008e023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0008e024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0008e025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0008e026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0008e027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0008e028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0008e029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0008e02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0008e02b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00090000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00090001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00090002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00090040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00090080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000900c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000900c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000900c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000900c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00090100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00090140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00090800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00090801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00090802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00090803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00090804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00090805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00090806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00090807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00090808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00090809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0009080a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0009080b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00090818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00090c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00090c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00090c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00090c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00090c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00090c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00090c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00090c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00090c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00090c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00090c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00090c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00090c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00090c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00090c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00090c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00090c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00090c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00090c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00090c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00090c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00090c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00090c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00090c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00090c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00090c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00090c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00090c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00090c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00090c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00090c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00090c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00091001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00091040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00091080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000910c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000910c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00091100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00091140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00091141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00091142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00091180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00091181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00091182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00091183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00091184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00091185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00091186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00091187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00091190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00091191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00091192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00091193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00091194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00091195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00091196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00091197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000911a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00091200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00091201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00091202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00091801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00091c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00091c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00091c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00091c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00091c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00091c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00091c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00091c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00091c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00091c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00091c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00091c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00091c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00091c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00091c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00091c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00091c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00091c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00091c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00091c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00091c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00091c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00091c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00091c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00091c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00091c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00091c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00091c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00091c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00091c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00091c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00091c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00092000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00092000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00092000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
index b66b78aec85c70caa96b35554a85900475ad0286..be85a718fb41f93ded98fc9b737766839cca602d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
@@ -18,463 +18,523 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000df8 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000de0 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x0002d032 1 RO uint32 b[29:0] - - -
- - - - - stable 0x0002d032 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x0002d032 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x0002d033 1 RW uint32 b[27:0] - - -
- - - - - edge 0x0002d033 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x0002d034 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x0002d000 1 WO uint32 b[23:0] - - -
- - - - - rden 0x0002d001 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x0002d002 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x0002d003 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x0002d004 1 WO uint32 b[0:0] - - -
- - - - - busy 0x0002d005 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x0002d006 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002d030 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x0002d02e 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002d02c 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x0002d02d 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x0002d02a 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0002d008 1 WO uint32 b[31:0] - - -
- - - - - param 0x0002d009 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0002d00a 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0002d00b 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0002d00c 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0002d00d 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0002d00e 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG beamlet_scale 0x00000dd0 1 RW uint32 b[15:0] - - -
- - - - - block_period 0x00000dd1 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x00000dd2 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x00000dd3 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x00000dd4 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x00000dd5 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x00000dd6 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x00000dd7 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x00000dd8 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x00000dd9 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x00000dda 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x00000ddb 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x00000ddc 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0002d020 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0002d020 1 RW uint32 b[31:31] - - -
- JESD204B 1 1 REG rx_dll_ctrl 0x0002c014 1 RW uint32 b[16:0] - - -
- - - - - rx_syncn_sysref_ctrl 0x0002c015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x0002c015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x0002c015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x0002c015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x0002c018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x0002c019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x0002c020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x0002c020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x0002c021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x0002c022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x0002c023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x0002c025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x0002c025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x0002c025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x0002c025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x0002c026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x0002c026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x0002c026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x0002c026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x0002c026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x0002c026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x0002c026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x0002c026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002c03c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000df0 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00000df0 1 RW uint32 b[1:1] - - -
- - - - - nof_block_per_sync 0x00000df1 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00000df2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000df3 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00000df4 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002d026 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0002d027 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00000cc0 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00000cc0 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00000cc1 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00000cc2 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00000cc3 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d00 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00000d01 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00000d02 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00000d03 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024
- REG_SI 1 1 REG enable 0x0002d028 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x0002d024 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x0002d025 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d01e 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x00000c83 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x00000c84 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x00000c85 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000c86 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x00000c86 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x00000c86 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x00000c87 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000c88 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x00000c8a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000c8b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x00000c8c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000c8d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000c8e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000c8f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000c90 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000c91 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000c92 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000c93 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000c94 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000c95 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000c96 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000c97 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000c98 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000c99 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000c9a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000c9b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000c9c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000c9d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000c9e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000c9f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000ca0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000ca1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000ca2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000ca3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000ca4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000ca5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000ca6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000ca7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000ca8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000ca9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000caa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x00000cab 1 RW uint32 b[15:0] - - -
- REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x00000c02 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c03 - - - b[31:0] b[63:32] - -
- REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0002d018 1 RW uint32 b[31:0] - - -
- RAM_ST_XSQ 1 1 RAM data 0x00018000 576 RW cint64_ir b[31:0] b[31:0] - -
- - - - - - 0x0002d019 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00000dc0 15 RW uint32 b[31:0] - - -
- - - - - step 0x00000dcf 1 RW uint32 b[31:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x0002d014 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x0002d015 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000082 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00000083 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00000084 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00000085 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00000086 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00000087 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000088 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0000008a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0000008b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000008c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000008d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000008e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0000008f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000090 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000091 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000092 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000093 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000094 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000095 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000096 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000097 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000098 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000099 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000009a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000009b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000009c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000009d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000009e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0000009f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x000000a0 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x000000a1 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x000000a2 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x000000a3 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x000000a4 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x000000a5 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x000000a6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000a7 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x000000a8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000a9 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x0002d010 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x0002d011 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00000000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00000006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00000006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00000007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0000000a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000000b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0000000c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000000d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000000e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000000f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0000001a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000001b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000001c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000001d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000001e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000001f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0000002a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0000002b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00002000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00002001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00002002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00002040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00002080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000020c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000020c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000020c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000020c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00002100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00002140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00002800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00002801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00002802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00002803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00002804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00002805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00002806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00002807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00002808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00002809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0000280a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0000280b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00002818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00002c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00002c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00002c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00002c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00002c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00002c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00002c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00002c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00002c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00002c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00002c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00002c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00002c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00002c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00002c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00002c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00002c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00002c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00002c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00002c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00002c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00002c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00002c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00002c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00002c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00002c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00002c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00002c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00002c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00002c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00002c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00002c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00003001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00003040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00003080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000030c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000030c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00003100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00003140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00003141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00003142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00003180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00003181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00003182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00003183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00003184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00003185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00003186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00003187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00003190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00003191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00003192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00003193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00003194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00003195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00003196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00003197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000031a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00003200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00003201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00003202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00003801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00003c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00003c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00003c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00003c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00003c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00003c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00003c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00003c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00003c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00003c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00003c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00003c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00003c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00003c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00003c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00003c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00003c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00003c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00003c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00003c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00003c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00003c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00003c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00003c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00003c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00003c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00003c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00003c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00003c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00003c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00003c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00003c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002d022 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x0002d022 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x0002d022 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000dc8 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000db0 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000d80 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00000dec 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00000dec 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00000dec 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00000ded 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00000ded 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00000dee 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00000dd0 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00000dd1 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00000dd2 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00000dd3 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00000dd4 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00000dd5 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00000dd6 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002f004 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0002f002 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002f000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0002f001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00000dfe 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x00000dd8 1 WO uint32 b[31:0] - - -
+ - - - - param 0x00000dd9 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x00000dda 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x00000ddb 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x00000ddc 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x00000ddd 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x00000dde 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x00000da0 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x00000da1 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00000da2 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x00000da3 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x00000da4 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x00000da5 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00000da6 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00000da7 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00000da8 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00000da9 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00000daa 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x00000dab 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x00000df4 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x00000df4 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_dll_ctrl 0x0002e014 1 RW uint32 b[16:0] - - 256
+ - - - - rx_syncn_sysref_ctrl 0x0002e015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x0002e015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x0002e015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0002e015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x0002e018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0002e019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x0002e020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0002e020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0002e021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0002e022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0002e023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0002e025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0002e025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0002e025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0002e025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0002e026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0002e026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0002e026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0002e026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0002e026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0002e026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0002e026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0002e026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002e03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002e03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002e03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002e03f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000dc0 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00000dc0 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00000dc1 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00000dc2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000dc3 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00000dc4 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00000dfa 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000dfb - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00000d00 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00000d00 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00000d01 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00000d02 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00000d41 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00000d42 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d43 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
+ REG_SI 1 1 REG enable 0x00000dfc 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x0002c000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00000df8 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00028001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00000df2 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00000c10 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00000c11 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00000c12 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c13 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00000c14 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c15 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00000c16 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c17 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00000c18 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00000c19 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c1a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x00000c1b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00018000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00018001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00000d90 15 RW uint32 b[31:0] - - -
+ - - - - step 0x00000d9f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00000c02 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00000c03 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00000df0 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00000de8 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00000de9 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00000c83 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00000c84 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00000c85 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00000c86 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00000c87 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c88 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x00000c8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x00000c8b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c8c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c8d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c8e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c8f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c90 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c91 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c92 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c93 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c94 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c95 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c96 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c97 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c98 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c99 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c9b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c9c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c9e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c9f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000ca0 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000ca1 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000ca2 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000ca3 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000ca4 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000ca5 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000ca6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca7 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca9 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00000de4 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x00000de0 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000082 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000083 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000084 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000085 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000086 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000086 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000086 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000087 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000088 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000008a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000008b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000008c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000008d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000008e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000008f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000090 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000091 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000092 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000093 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000094 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000095 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000096 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000097 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000098 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000099 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000009a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000009b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000009c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000009d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000009e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000009f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x000000a0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000000a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000000a2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000000a3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000000a4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000000a5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000000a6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000000a7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000000a9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000aa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x000000ab 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00006040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00006080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000060c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000060c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00006100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00006140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00006800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00006801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00006802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00006803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00006804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00006805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00006806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00006807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00006808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00006809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0000680a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0000680b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00006818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00006c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00006c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00006c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00006c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00006c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00006c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00006c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00006c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00006c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00006c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00006c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00006c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00006c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00006c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00006c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00006c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00006c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00006c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00006c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00006c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00006c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00006c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00006c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00006c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00006c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00006c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00006c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00006c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00006c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00006c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00006c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00007001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00007040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00007080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000070c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000070c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00007100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00007140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00007141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00007142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00007180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00007181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00007182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00007183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00007184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00007185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00007186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00007187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00007190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00007191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00007192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00007193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00007194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00007195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00007196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00007197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000071a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00007200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00007201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00007202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00007801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00007c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00007c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00007c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00007c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00007c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00007c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00007c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00007c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00007c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00007c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00007c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00007c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00007c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00007c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00007c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00007c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00007c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00007c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00007c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00007c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00007c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00007c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00007c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00007c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00007c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00007c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00007c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00007c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00007c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00007c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00000df6 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00000df6 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00000df6 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index 8749dd152b58f0d5947280a9cd3eae6c28742f9e..85640f63d7e61ccda0714cd9d78a0f22096ee896 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /><slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /><slave name='pio_pps.mem' start='0x3770' end='0x3780' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3780' end='0x3788' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0x3788' end='0x3790' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x3790' end='0x3798' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3798' end='0x37A0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37A0' end='0x37A8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37A8' end='0x37B0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37B0' end='0x37B8' datawidth='32' /><slave name='reg_si.mem' start='0x37B8' end='0x37C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3770' end='0x3780' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler_xsub.mem' start='0x3780' end='0x3788' datawidth='32' /&gt;&lt;slave name='reg_dp_sync_insert_v2.mem' start='0x3788' end='0x3790' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x3790' end='0x3798' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3798' end='0x37A0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x37A0' end='0x37A8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x37A8' end='0x37B0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x37B0' end='0x37B8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x37B8' end='0x37C0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x37C0' end='0x37C8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x37C8' end='0x37D0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x37D0' end='0x37D8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x37D8' end='0x37E0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x37E0' end='0x37E8' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
index 3744538fd9325239f2ca6ee4c8212fc3e5e89ed6..44faa6d915ff7437d0591aa8ebc3bf0d73cea837 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</ipxact:name>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
+ <ipxact:value>32768</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -664,7 +664,12 @@
<ipxact:name>avs_mem_address</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>12</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -765,7 +770,12 @@
<ipxact:name>coe_address_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>12</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -841,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</ipxact:library>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -850,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>13</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -879,7 +889,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
@@ -899,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub
+ element qsys_lofar2_unb2c_sdp_station_ram_st_histogram
{
}
}
@@ -987,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1056,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1285,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1452,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1484,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_st_histogram.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
index 248f1a7ef8c6d3274180ea26cc264abaa8264ebd..7d833a9272e0b1cd50473d66c9d7e48fb307315c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>65536</ipxact:value>
+ <ipxact:value>262144</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>14</ipxact:value>
+ <ipxact:value>16</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
new file mode 100644
index 0000000000000000000000000000000000000000..cbdbaef9c443ac75ef4c8a9756cc17937671e8f7
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
index ea32fa4996aee36acfbfb0f7f72ddcfaa347dc57..47b558ba63a7e5c16b9f069596b0660f61feb60d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</ipxact:name>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -841,7 +841,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</ipxact:library>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -879,7 +879,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
@@ -899,7 +899,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2
+ element qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets
{
}
}
@@ -1484,38 +1484,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index a87110eabc5df42106d8ca04d377ab5af3452fa5..6753e9c4e7c59c60ed28a63de931ee7f38ae6b2d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -45,31 +45,6 @@ set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_location_assignment PIN_AT31 -to QSFP_RST
-set_location_assignment PIN_AY33 -to QSFP_SCL[0]
-set_location_assignment PIN_AY32 -to QSFP_SCL[1]
-set_location_assignment PIN_AY30 -to QSFP_SCL[2]
-set_location_assignment PIN_AN33 -to QSFP_SCL[3]
-set_location_assignment PIN_AN31 -to QSFP_SCL[4]
-set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
-set_location_assignment PIN_BA32 -to QSFP_SDA[0]
-set_location_assignment PIN_BA31 -to QSFP_SDA[1]
-set_location_assignment PIN_AP33 -to QSFP_SDA[2]
-set_location_assignment PIN_AM33 -to QSFP_SDA[3]
-set_location_assignment PIN_AK33 -to QSFP_SDA[4]
-set_location_assignment PIN_AH32 -to QSFP_SDA[5]
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
### QSFP_1_0
@@ -112,154 +87,124 @@ set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
# JESD pins
# ====================
# Pins needed for the 12 channel JESD204B interface to the ADCs
-set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
+
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11]
-
-#set_location_assignment PIN_B9 -to BCK_RX[0]
-set_location_assignment PIN_D9 -to BCK_RX[1]
-set_location_assignment PIN_C11 -to BCK_RX[2]
-set_location_assignment PIN_F9 -to BCK_RX[3]
-set_location_assignment PIN_C7 -to BCK_RX[4]
-set_location_assignment PIN_E11 -to BCK_RX[5]
-set_location_assignment PIN_E7 -to BCK_RX[6]
-set_location_assignment PIN_D5 -to BCK_RX[7]
-set_location_assignment PIN_G7 -to BCK_RX[8]
-set_location_assignment PIN_F5 -to BCK_RX[9]
-set_location_assignment PIN_J7 -to BCK_RX[10]
-set_location_assignment PIN_H5 -to BCK_RX[11]
-set_location_assignment PIN_L7 -to BCK_RX[12]
-set_location_assignment PIN_K5 -to BCK_RX[13]
-set_location_assignment PIN_N7 -to BCK_RX[14]
-set_location_assignment PIN_M5 -to BCK_RX[15]
-set_location_assignment PIN_R7 -to BCK_RX[16]
-set_location_assignment PIN_P5 -to BCK_RX[17]
-set_location_assignment PIN_U7 -to BCK_RX[18]
-set_location_assignment PIN_T5 -to BCK_RX[19]
-set_location_assignment PIN_W7 -to BCK_RX[20]
-set_location_assignment PIN_V5 -to BCK_RX[21]
-set_location_assignment PIN_AA7 -to BCK_RX[22]
-set_location_assignment PIN_Y5 -to BCK_RX[23]
-set_location_assignment PIN_AC7 -to BCK_RX[24]
-set_location_assignment PIN_AB5 -to BCK_RX[25]
-set_location_assignment PIN_AE7 -to BCK_RX[26]
-set_location_assignment PIN_AD5 -to BCK_RX[27]
-set_location_assignment PIN_AG7 -to BCK_RX[28]
-set_location_assignment PIN_AF5 -to BCK_RX[29]
-set_location_assignment PIN_AJ7 -to BCK_RX[30]
-set_location_assignment PIN_AH5 -to BCK_RX[31]
-set_location_assignment PIN_AL7 -to BCK_RX[32]
-set_location_assignment PIN_AK5 -to BCK_RX[33]
-set_location_assignment PIN_AN7 -to BCK_RX[34]
-set_location_assignment PIN_AM5 -to BCK_RX[35]
-set_location_assignment PIN_AR7 -to BCK_RX[36]
-set_location_assignment PIN_AP5 -to BCK_RX[37]
-set_location_assignment PIN_AU7 -to BCK_RX[38]
-set_location_assignment PIN_AT5 -to BCK_RX[39]
-set_location_assignment PIN_AW7 -to BCK_RX[40]
-set_location_assignment PIN_AV5 -to BCK_RX[41]
-set_location_assignment PIN_BA7 -to BCK_RX[42]
-set_location_assignment PIN_AY5 -to BCK_RX[43]
-set_location_assignment PIN_BC7 -to BCK_RX[44]
-set_location_assignment PIN_BB5 -to BCK_RX[45]
-set_location_assignment PIN_AY9 -to BCK_RX[46]
-set_location_assignment PIN_BB9 -to BCK_RX[47]
-
-
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
+
+#set_location_assignment PIN_AC7 -to BCK_RX[23]
+#set_location_assignment PIN_AB5 -to BCK_RX[22]
+#set_location_assignment PIN_AE7 -to BCK_RX[21]
+#set_location_assignment PIN_AD5 -to BCK_RX[20]
+#set_location_assignment PIN_AG7 -to BCK_RX[19]
+#set_location_assignment PIN_AF5 -to BCK_RX[18]
+#set_location_assignment PIN_AJ7 -to BCK_RX[17]
+#set_location_assignment PIN_AH5 -to BCK_RX[16]
+#set_location_assignment PIN_AL7 -to BCK_RX[15]
+#set_location_assignment PIN_AK5 -to BCK_RX[14]
+#set_location_assignment PIN_AN7 -to BCK_RX[13]
+#set_location_assignment PIN_AM5 -to BCK_RX[12]
+set_location_assignment PIN_AR7 -to BCK_RX[11]
+set_location_assignment PIN_AP5 -to BCK_RX[10]
+set_location_assignment PIN_AU7 -to BCK_RX[9]
+set_location_assignment PIN_AT5 -to BCK_RX[8]
+set_location_assignment PIN_AW7 -to BCK_RX[7]
+set_location_assignment PIN_AV5 -to BCK_RX[6]
+set_location_assignment PIN_BA7 -to BCK_RX[5]
+set_location_assignment PIN_AY5 -to BCK_RX[4]
+set_location_assignment PIN_BC7 -to BCK_RX[3]
+set_location_assignment PIN_BB5 -to BCK_RX[2]
+set_location_assignment PIN_AY9 -to BCK_RX[1]
+set_location_assignment PIN_BB9 -to BCK_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
@@ -345,190 +290,24 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47]
-
-
# Substitute new signal names from the jesd_simple design
-#set_location_assignment PIN_BA7 -to BCK_RX[0]
-
set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
set_location_assignment PIN_V9 -to BCK_REF_CLK
set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to JESD204B_SYSREF
set_location_assignment PIN_Y13 -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
-
-set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
-set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
-
-
+set_location_assignment PIN_Y12 -to "JESD204B_SYSREF(n)"
+
+set_location_assignment PIN_AD12 -to JESD204B_SYNC_N[0]
+set_location_assignment PIN_AC13 -to JESD204B_SYNC_N[1]
+set_location_assignment PIN_AA13 -to JESD204B_SYNC_N[2]
+set_location_assignment PIN_AA12 -to JESD204B_SYNC_N[3]
+#set_location_assignment PIN_V14 -to JESD204B_SYNC_N[4]
+#set_location_assignment PIN_V12 -to JESD204B_SYNC_N[5]
+#set_location_assignment PIN_U14 -to JESD204B_SYNC_N[6]
+#set_location_assignment PIN_R13 -to JESD204B_SYNC_N[7]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index eb404610dbbdba3766d738de711b3aeb157e43e0..3b4e2f6bc39c13a148f0c17f0f8218db159442b7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "950272";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "14304";
+ value = "966680";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "14232";
+ value = "14288";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "14192";
+ value = "14256";
type = "String";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "262144";
+ value = "524288";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "917504";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "786432";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "655360";
type = "String";
}
}
@@ -318,6 +318,22 @@
type = "String";
}
}
+ element ram_st_histogram
+ {
+ datum _sortIndex
+ {
+ value = "54";
+ type = "int";
+ }
+ }
+ element ram_st_histogram.mem
+ {
+ datum baseAddress
+ {
+ value = "32768";
+ type = "String";
+ }
+ }
element ram_st_sst
{
datum _sortIndex
@@ -330,7 +346,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "851968";
type = "String";
}
}
@@ -338,7 +354,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "50";
type = "int";
}
}
@@ -346,7 +362,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "262144";
type = "String";
}
}
@@ -362,7 +378,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "720896";
type = "String";
}
}
@@ -394,7 +410,7 @@
{
datum baseAddress
{
- value = "14176";
+ value = "14240";
type = "String";
}
}
@@ -426,39 +442,39 @@
{
datum baseAddress
{
- value = "14256";
+ value = "14312";
type = "String";
}
}
- element reg_bsn_scheduler_xsub
+ element reg_bsn_source_v2
{
datum _sortIndex
{
- value = "51";
+ value = "22";
type = "int";
}
}
- element reg_bsn_scheduler_xsub.mem
+ element reg_bsn_source_v2.mem
{
datum baseAddress
{
- value = "14208";
+ value = "14080";
type = "String";
}
}
- element reg_bsn_source_v2
+ element reg_bsn_sync_scheduler_xsub
{
datum _sortIndex
{
- value = "22";
+ value = "53";
type = "int";
}
}
- element reg_bsn_source_v2.mem
+ element reg_bsn_sync_scheduler_xsub.mem
{
datum baseAddress
{
- value = "14016";
+ value = "13824";
type = "String";
}
}
@@ -466,7 +482,7 @@
{
datum _sortIndex
{
- value = "50";
+ value = "49";
type = "int";
}
}
@@ -474,7 +490,7 @@
{
datum baseAddress
{
- value = "13824";
+ value = "13888";
type = "String";
}
}
@@ -506,7 +522,7 @@
{
datum baseAddress
{
- value = "14248";
+ value = "14304";
type = "String";
}
}
@@ -526,22 +542,6 @@
type = "String";
}
}
- element reg_dp_sync_insert_v2
- {
- datum _sortIndex
- {
- value = "49";
- type = "int";
- }
- }
- element reg_dp_sync_insert_v2.mem
- {
- datum baseAddress
- {
- value = "14216";
- type = "String";
- }
- }
element reg_dp_xonoff
{
datum _sortIndex
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "14160";
+ value = "14224";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "14296";
+ value = "966672";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "14288";
+ value = "966664";
type = "String";
}
}
@@ -617,7 +617,7 @@
{
datum baseAddress
{
- value = "14080";
+ value = "14144";
type = "String";
}
}
@@ -633,7 +633,7 @@
{
datum baseAddress
{
- value = "14048";
+ value = "14112";
type = "String";
}
}
@@ -654,7 +654,7 @@
{
datum baseAddress
{
- value = "13952";
+ value = "14016";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "14280";
+ value = "966656";
type = "String";
}
}
@@ -712,7 +712,23 @@
{
datum baseAddress
{
- value = "14272";
+ value = "14328";
+ type = "String";
+ }
+ }
+ element reg_nof_crosslets
+ {
+ datum _sortIndex
+ {
+ value = "55";
+ type = "int";
+ }
+ }
+ element reg_nof_crosslets.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
type = "String";
}
}
@@ -728,7 +744,7 @@
{
datum baseAddress
{
- value = "14240";
+ value = "14296";
type = "String";
}
}
@@ -744,7 +760,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "98304";
type = "String";
}
}
@@ -765,7 +781,7 @@
{
datum baseAddress
{
- value = "14112";
+ value = "14176";
type = "String";
}
}
@@ -781,7 +797,7 @@
{
datum baseAddress
{
- value = "13888";
+ value = "13952";
type = "String";
}
}
@@ -797,7 +813,7 @@
{
datum baseAddress
{
- value = "14264";
+ value = "14320";
type = "String";
}
}
@@ -813,7 +829,7 @@
{
datum baseAddress
{
- value = "14144";
+ value = "14208";
type = "String";
}
}
@@ -829,7 +845,7 @@
{
datum baseAddress
{
- value = "14224";
+ value = "14280";
type = "String";
}
}
@@ -837,7 +853,7 @@
{
datum _sortIndex
{
- value = "53";
+ value = "51";
type = "int";
}
}
@@ -845,7 +861,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "14272";
type = "String";
}
}
@@ -885,7 +901,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -1490,6 +1506,41 @@
internal="ram_st_bst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="ram_st_histogram_address"
+ internal="ram_st_histogram.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_clk"
+ internal="ram_st_histogram.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_read"
+ internal="ram_st_histogram.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_readdata"
+ internal="ram_st_histogram.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_reset"
+ internal="ram_st_histogram.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_write"
+ internal="ram_st_histogram.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_histogram_writedata"
+ internal="ram_st_histogram.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="ram_st_sst_address"
internal="ram_st_sst.address"
@@ -1720,73 +1771,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_address"
- internal="reg_bsn_scheduler_xsub.address"
+ name="reg_bsn_source_v2_address"
+ internal="reg_bsn_source_v2.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_clk"
- internal="reg_bsn_scheduler_xsub.clk"
+ name="reg_bsn_source_v2_clk"
+ internal="reg_bsn_source_v2.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_read"
- internal="reg_bsn_scheduler_xsub.read"
+ name="reg_bsn_source_v2_read"
+ internal="reg_bsn_source_v2.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_readdata"
- internal="reg_bsn_scheduler_xsub.readdata"
+ name="reg_bsn_source_v2_readdata"
+ internal="reg_bsn_source_v2.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_reset"
- internal="reg_bsn_scheduler_xsub.reset"
+ name="reg_bsn_source_v2_reset"
+ internal="reg_bsn_source_v2.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_write"
- internal="reg_bsn_scheduler_xsub.write"
+ name="reg_bsn_source_v2_write"
+ internal="reg_bsn_source_v2.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_writedata"
- internal="reg_bsn_scheduler_xsub.writedata"
+ name="reg_bsn_source_v2_writedata"
+ internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_address"
- internal="reg_bsn_source_v2.address"
+ name="reg_bsn_sync_scheduler_xsub_address"
+ internal="reg_bsn_sync_scheduler_xsub.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_clk"
- internal="reg_bsn_source_v2.clk"
+ name="reg_bsn_sync_scheduler_xsub_clk"
+ internal="reg_bsn_sync_scheduler_xsub.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_read"
- internal="reg_bsn_source_v2.read"
+ name="reg_bsn_sync_scheduler_xsub_read"
+ internal="reg_bsn_sync_scheduler_xsub.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_readdata"
- internal="reg_bsn_source_v2.readdata"
+ name="reg_bsn_sync_scheduler_xsub_readdata"
+ internal="reg_bsn_sync_scheduler_xsub.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_reset"
- internal="reg_bsn_source_v2.reset"
+ name="reg_bsn_sync_scheduler_xsub_reset"
+ internal="reg_bsn_sync_scheduler_xsub.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_write"
- internal="reg_bsn_source_v2.write"
+ name="reg_bsn_sync_scheduler_xsub_write"
+ internal="reg_bsn_sync_scheduler_xsub.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_writedata"
- internal="reg_bsn_source_v2.writedata"
+ name="reg_bsn_sync_scheduler_xsub_writedata"
+ internal="reg_bsn_sync_scheduler_xsub.writedata"
type="conduit"
dir="end" />
<interface
@@ -1929,41 +1980,6 @@
internal="reg_dp_shiftram.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_address"
- internal="reg_dp_sync_insert_v2.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_clk"
- internal="reg_dp_sync_insert_v2.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_read"
- internal="reg_dp_sync_insert_v2.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_readdata"
- internal="reg_dp_sync_insert_v2.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_reset"
- internal="reg_dp_sync_insert_v2.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_write"
- internal="reg_dp_sync_insert_v2.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_writedata"
- internal="reg_dp_sync_insert_v2.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_dp_xonoff_address"
internal="reg_dp_xonoff.address"
@@ -2275,6 +2291,41 @@
internal="reg_mmdp_data.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_nof_crosslets_address"
+ internal="reg_nof_crosslets.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_clk"
+ internal="reg_nof_crosslets.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_read"
+ internal="reg_nof_crosslets.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_readdata"
+ internal="reg_nof_crosslets.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_reset"
+ internal="reg_nof_crosslets.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_write"
+ internal="reg_nof_crosslets.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_nof_crosslets_writedata"
+ internal="reg_nof_crosslets.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_nw_10gbe_eth10g_address"
internal="reg_nw_10gbe_eth10g.address"
@@ -7273,7 +7324,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x36C0' end='0x36E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x36E0' end='0x3700' datawidth='32' /><slave name='reg_epcs.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_remu.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3740' end='0x3750' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3750' end='0x3760' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3760' end='0x3770' datawidth='32' /><slave name='pio_pps.mem' start='0x3770' end='0x3780' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3780' end='0x3788' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0x3788' end='0x3790' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x3790' end='0x3798' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3798' end='0x37A0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37A0' end='0x37A8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37A8' end='0x37B0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37B0' end='0x37B8' datawidth='32' /><slave name='reg_si.mem' start='0x37B8' end='0x37C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -23959,7 +24010,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_st_histogram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23967,17 +24018,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -23986,27 +24037,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -24019,13 +24071,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -24039,7 +24089,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24108,7 +24158,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24265,12 +24315,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -24297,17 +24347,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -24329,17 +24379,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -24361,14 +24411,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -24380,31 +24430,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -24414,22 +24463,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -24456,14 +24507,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -24514,11 +24565,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24547,17 +24598,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>14</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -24566,27 +24617,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -24599,13 +24651,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -24619,7 +24669,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24688,7 +24738,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24844,6 +24894,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -24908,199 +25118,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_xsq"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26211,37 +26262,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26257,7 +26308,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26321,7 +26372,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26390,7 +26441,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26796,11 +26847,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26837,7 +26888,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26901,7 +26952,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26970,7 +27021,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27352,37 +27403,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27398,7 +27449,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27462,7 +27513,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27531,7 +27582,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27937,11 +27988,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27978,7 +28029,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28042,7 +28093,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28111,7 +28162,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28493,37 +28544,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28539,7 +28590,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28603,7 +28654,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28672,7 +28723,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29078,11 +29129,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29119,7 +29170,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29183,7 +29234,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29252,7 +29303,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29634,37 +29685,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29680,7 +29731,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29744,7 +29795,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29813,7 +29864,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30219,11 +30270,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30252,17 +30303,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30271,28 +30322,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30305,11 +30355,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -30323,7 +30375,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30362,17 +30414,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -30388,7 +30444,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30412,6 +30468,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -30544,12 +30601,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -30576,17 +30633,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30608,17 +30665,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30640,14 +30697,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30659,30 +30716,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30692,24 +30750,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -30736,14 +30792,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -30770,37 +30826,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30816,7 +30872,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30880,7 +30936,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30949,7 +31005,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31355,11 +31411,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31396,7 +31452,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31460,7 +31516,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31529,7 +31585,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31911,37 +31967,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler_xsub"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33052,30 +33108,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -34223,7 +34279,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34231,17 +34287,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34250,27 +34306,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34283,13 +34340,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -34529,12 +34584,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34561,17 +34616,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34593,17 +34648,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -34625,14 +34680,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34644,31 +34699,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -34678,22 +34732,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34720,14 +34776,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -34811,17 +34867,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34830,27 +34886,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34863,13 +34920,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -35109,12 +35164,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35141,17 +35196,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -35173,17 +35228,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -35205,14 +35260,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -35224,31 +35279,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -35258,22 +35312,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35300,14 +35356,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -35334,37 +35390,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35380,7 +35436,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35444,7 +35500,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35513,7 +35569,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35919,11 +35975,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35960,7 +36016,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36024,7 +36080,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36093,7 +36149,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36475,37 +36531,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36521,7 +36577,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36585,7 +36641,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36654,7 +36710,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37060,11 +37116,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37101,7 +37157,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37165,7 +37221,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37234,7 +37290,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37616,37 +37672,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37662,7 +37718,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37726,7 +37782,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37795,7 +37851,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38201,11 +38257,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38242,7 +38298,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38306,7 +38362,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38375,7 +38431,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38757,37 +38813,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_sync_insert_v2"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38803,7 +38859,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38867,7 +38923,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38936,7 +38992,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39342,11 +39398,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39383,7 +39439,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39447,7 +39503,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39516,7 +39572,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39898,30 +39954,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -50197,7 +50253,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50205,17 +50261,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50224,27 +50280,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50257,13 +50314,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -50503,12 +50558,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -50535,17 +50590,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50567,17 +50622,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -50599,14 +50654,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50618,31 +50673,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -50652,22 +50706,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -50694,14 +50750,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -50785,17 +50841,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50804,27 +50860,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50837,13 +50894,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -51082,70 +51137,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -51179,14 +51170,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -51198,31 +51189,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -51232,11 +51222,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -51305,40 +51297,104 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -51354,7 +51410,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51418,7 +51474,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51487,7 +51543,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51893,11 +51949,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -51934,7 +51990,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51998,7 +52054,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52067,7 +52123,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52449,37 +52505,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -52495,7 +52551,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52559,7 +52615,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52628,7 +52684,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53034,11 +53090,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -53075,7 +53131,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53139,7 +53195,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53208,7 +53264,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53590,37 +53646,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53636,7 +53692,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53700,7 +53756,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53769,7 +53825,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54175,11 +54231,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -54216,7 +54272,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54280,7 +54336,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54349,7 +54405,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54731,37 +54787,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54777,7 +54833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54841,7 +54897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54910,7 +54966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55316,11 +55372,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55357,7 +55413,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55421,7 +55477,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55490,7 +55546,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55872,37 +55928,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -55918,7 +55974,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55982,7 +56038,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56051,7 +56107,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56457,11 +56513,1152 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_enable_bst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62195,17 +63392,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -62214,27 +63411,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -62247,13 +63445,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -62306,21 +63502,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -62360,7 +63552,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -62492,6 +63683,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -62556,165 +63907,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
@@ -67480,7 +68672,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37e0" />
+ <parameter name="baseAddress" value="0x000ec018" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67560,7 +68752,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3770" />
+ <parameter name="baseAddress" value="0x37b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67600,7 +68792,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3720" />
+ <parameter name="baseAddress" value="0x3760" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67620,7 +68812,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3700" />
+ <parameter name="baseAddress" value="0x3740" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67640,7 +68832,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37d8" />
+ <parameter name="baseAddress" value="0x000ec010" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67660,7 +68852,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37d0" />
+ <parameter name="baseAddress" value="0x000ec008" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67680,7 +68872,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37c8" />
+ <parameter name="baseAddress" value="0x000ec000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67700,7 +68892,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37c0" />
+ <parameter name="baseAddress" value="0x37f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67720,7 +68912,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36e0" />
+ <parameter name="baseAddress" value="0x3720" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67740,7 +68932,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3680" />
+ <parameter name="baseAddress" value="0x36c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67760,7 +68952,7 @@
start="cpu_0.data_master"
end="ram_st_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x000d0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67780,7 +68972,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37b8" />
+ <parameter name="baseAddress" value="0x37f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67800,7 +68992,7 @@
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x000c0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67860,7 +69052,7 @@
start="cpu_0.data_master"
end="ram_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000b0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67900,7 +69092,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37b0" />
+ <parameter name="baseAddress" value="0x37e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67920,7 +69112,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x36c0" />
+ <parameter name="baseAddress" value="0x3700" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -67980,7 +69172,7 @@
start="cpu_0.data_master"
end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x000e8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68000,7 +69192,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37a8" />
+ <parameter name="baseAddress" value="0x37e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68020,7 +69212,7 @@
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x000e0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68040,7 +69232,7 @@
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x000a0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68060,7 +69252,7 @@
start="cpu_0.data_master"
end="ram_bf_weights.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0x00080000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68080,7 +69272,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3760" />
+ <parameter name="baseAddress" value="0x37a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68120,7 +69312,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3750" />
+ <parameter name="baseAddress" value="0x3790" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68160,7 +69352,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3640" />
+ <parameter name="baseAddress" value="0x3680" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68180,7 +69372,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x37a0" />
+ <parameter name="baseAddress" value="0x37d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68200,7 +69392,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00018000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68260,7 +69452,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3798" />
+ <parameter name="baseAddress" value="0x37d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68280,7 +69472,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3790" />
+ <parameter name="baseAddress" value="0x37c8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68320,7 +69512,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3740" />
+ <parameter name="baseAddress" value="0x3780" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68358,9 +69550,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_dp_sync_insert_v2.mem">
+ end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3788" />
+ <parameter name="baseAddress" value="0x3640" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68378,9 +69570,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_crosslets_info.mem">
+ end="ram_st_xsq.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68398,9 +69590,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_scheduler_xsub.mem">
+ end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3780" />
+ <parameter name="baseAddress" value="0x37c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68418,9 +69610,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="ram_st_xsq.mem">
+ end="reg_stat_hdr_dat_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68438,9 +69630,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_stat_enable_xst.mem">
+ end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
+ <parameter name="baseAddress" value="0x3600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68458,9 +69650,29 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_xst.mem">
+ end="ram_st_histogram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x8000" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_nof_crosslets.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3008" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68814,28 +70026,33 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_dp_sync_insert_v2.system" />
+ end="reg_crosslets_info.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_st_xsq.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_crosslets_info.system" />
+ end="reg_stat_enable_xst.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_scheduler_xsub.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_st_xsq.system" />
+ end="reg_stat_hdr_dat_xst.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_stat_enable_xst.system" />
+ end="reg_bsn_sync_scheduler_xsub.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_stat_hdr_dat_xst.system" />
+ end="ram_st_histogram.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_nof_crosslets.system" />
<connection
kind="interrupt"
version="19.4"
@@ -69093,32 +70310,37 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_dp_sync_insert_v2.system_reset" />
+ end="reg_crosslets_info.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_crosslets_info.system_reset" />
+ end="ram_st_xsq.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_stat_enable_xst.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_scheduler_xsub.system_reset" />
+ end="reg_stat_hdr_dat_xst.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="ram_st_xsq.system_reset" />
+ end="reg_bsn_sync_scheduler_xsub.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_stat_enable_xst.system_reset" />
+ end="ram_st_histogram.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_xst.system_reset" />
+ end="reg_nof_crosslets.system_reset" />
<connection
kind="reset"
version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index 1b57c1a0fe03f71452f52a7f8e8dc9fd8da09dc8..3685635e95dfdc9628d753c2924d4b3410a496da 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -59,6 +59,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
@@ -66,15 +67,14 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
@@ -82,6 +82,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 1205e0b452a180cf271c24dead78329cf56dcbc0..c7ace4c1d3eabd4e79efecdad9c7f6a5072a448a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_adc IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,27 +80,16 @@ END lofar2_unb2c_sdp_station_adc;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_adc IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 0a333e41420d8cac3d9ee639b38b9bfe7910fb04..bb33bc3e00dbc943b2fc39e59fefbd2c8d8f9355 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -67,6 +67,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
@@ -74,15 +75,14 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
@@ -90,6 +90,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 3076d3396070c968f5db7e3297b3b91a9a797d14..a24859007bcc2cbd1512cd9c03211310f09e83e6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -69,17 +69,17 @@ ENTITY lofar2_unb2c_sdp_station_bf IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -87,30 +87,18 @@ END lofar2_unb2c_sdp_station_bf;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_bf IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index 59528fa408d41d7d04047fe82c50db11ea234d4a..5734a679fb767738cb552eb7e88ab76c674a1b6e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -66,6 +66,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
@@ -73,15 +74,14 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
@@ -89,6 +89,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index d293a305d761fe824eb51deca6fa2fb7b767bc7a..a6e729e54b03ff8b8d6e2547781ae189f1bd7ea0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_fsub IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,29 +80,17 @@ END lofar2_unb2c_sdp_station_fsub;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_fsub IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index e2d6c0a93c9a98a5470f57796fbe4f958ce920ce..a334150799684286048e96b2c425ade2d9fb70e7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -63,6 +63,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
@@ -70,15 +71,14 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
@@ -86,6 +86,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index c16a176dcd76128778bf86cc8c39cb4f6b10eefe..25983bb3e183a8967e25752573c24223c06a1073 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -69,17 +69,17 @@ ENTITY lofar2_unb2c_sdp_station_full IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -87,30 +87,17 @@ END lofar2_unb2c_sdp_station_full;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_full IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
-
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index 4e6c1c1af33b74e2cd6129dc496450c8c4c2bcf9..5511ee62f386606cc02bb9a8246b935476a0ee90 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -66,6 +66,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
@@ -73,15 +74,14 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
@@ -89,6 +89,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index 0d792d0d60461c15d0e144bfd7da8c631d87075c..76b86a18a368ab2763459e122090d64ed4927281 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_xsub_one IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,29 +80,17 @@ END lofar2_unb2c_sdp_station_xsub_one;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_xsub_one IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 7819eb6d3ef4e7a6bda4b41d6c740a51fcad105e..3d23da21e2dc0cb487733b0f97f72582a786c2f9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -94,7 +94,7 @@ ENTITY lofar2_unb2c_sdp_station IS
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0)
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0)
);
END lofar2_unb2c_sdp_station;
@@ -222,6 +222,10 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ -- ST Histogram
+ SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+
-- Aduh statistics monitor
SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
@@ -258,17 +262,18 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
- -- dp_sync_insert_v2
- SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
-- crosslets_info
SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
-- st_xsq
SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -562,6 +567,8 @@ BEGIN
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_st_histogram_mosi => ram_st_histogram_mosi,
+ ram_st_histogram_miso => ram_st_histogram_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
ram_st_sst_mosi => ram_st_sst_mosi,
@@ -606,12 +613,12 @@ BEGIN
reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
+ reg_nof_crosslets_miso => reg_nof_crosslets_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
@@ -685,6 +692,8 @@ BEGIN
ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_st_histogram_mosi => ram_st_histogram_mosi,
+ ram_st_histogram_miso => ram_st_histogram_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
@@ -705,12 +714,12 @@ BEGIN
reg_sdp_info_miso => reg_sdp_info_miso,
-- XSUB
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
+ reg_nof_crosslets_miso => reg_nof_crosslets_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 34a3f2b9082251f09f602a374f5f0286b7b12a19..d35eb3c749dd6c451f79abb9fce02821fc1618d9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -123,6 +123,10 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ -- ST Histogram
+ ram_st_histogram_mosi : OUT t_mem_mosi;
+ ram_st_histogram_miso : IN t_mem_miso;
+
-- Aduh
reg_aduh_monitor_mosi : OUT t_mem_mosi;
reg_aduh_monitor_miso : IN t_mem_miso;
@@ -199,17 +203,17 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
- -- dp_sync_insert_v2
- reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
- reg_dp_sync_insert_v2_miso : IN t_mem_miso;
-
-- crosslets_info
reg_crosslets_info_mosi : OUT t_mem_mosi;
reg_crosslets_info_miso : IN t_mem_miso;
- -- bsn_scheduler_xsub
- reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
+ -- crosslets_info
+ reg_nof_crosslets_mosi : OUT t_mem_mosi;
+ reg_nof_crosslets_miso : IN t_mem_miso;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
+ reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
-- st_xsq (XST)
ram_st_xsq_mosi : OUT t_mem_mosi;
@@ -295,6 +299,9 @@ BEGIN
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
@@ -352,14 +359,14 @@ BEGIN
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
- u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
- PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
-
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
- u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
+ u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
@@ -577,7 +584,6 @@ BEGIN
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
@@ -594,6 +600,14 @@ BEGIN
reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_clk_export => OPEN,
+ ram_st_histogram_reset_export => OPEN,
+ ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
@@ -746,14 +760,6 @@ BEGIN
reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_clk_export => OPEN,
- reg_dp_sync_insert_v2_reset_export => OPEN,
- reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
- reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
- reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
@@ -762,13 +768,21 @@ BEGIN
reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_clk_export => OPEN,
- reg_bsn_scheduler_xsub_reset_export => OPEN,
- reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
- reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
- reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_clk_export => OPEN,
+ reg_nof_crosslets_reset_export => OPEN,
+ reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 7b52937ab1250943315ac8463ad8f91857a9a18e..487539b5e64cd5b7dc85b49a433ba9590f80d94e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -91,6 +91,13 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
ram_equalizer_gains_clk_export : out std_logic; -- export
ram_equalizer_gains_read_export : out std_logic; -- export
@@ -329,13 +336,6 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
- reg_dp_sync_insert_v2_read_export : out std_logic; -- export
- reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
- reg_dp_sync_insert_v2_write_export : out std_logic; -- export
- reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
reg_crosslets_info_clk_export : out std_logic; -- export
reg_crosslets_info_read_export : out std_logic; -- export
@@ -343,14 +343,21 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
reg_crosslets_info_reset_export : out std_logic; -- export
reg_crosslets_info_write_export : out std_logic; -- export
reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 90b501d48f3aceba942ae70091199d09ceef9fc5..82cf3bf7ecad0733de0f8a1462a60cc02b195b85 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -101,7 +101,7 @@ ENTITY node_sdp_adc_input_and_timing IS
jesd204b_serial_data : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
jesd204b_refclk : IN STD_LOGIC;
jesd204b_sysref : IN STD_LOGIC;
- jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+ jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd - 1 DOWNTO 0);
-- Streaming data output
out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -123,7 +123,7 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
CONSTANT c_bs_block_size : NATURAL := c_sdp_N_fft; -- =1024;
CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-
+
-- JESD signals
SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
SIGNAL rx_rst : STD_LOGIC;
@@ -169,7 +169,7 @@ BEGIN
GENERIC MAP(
g_sim => g_sim,
g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_S_pn/c_sdp_S_rcu, -- = 12/3 = 4
+ g_nof_sync_n => c_sdp_N_sync_jesd,
g_jesd_freq => c_sdp_jesd204b_freq
)
PORT MAP(
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 32abb324a2812acfbe6e082727431fcc0e99f819..213dea60f73b825b798bd6dc837203d35b59f09f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -67,36 +67,37 @@ PACKAGE sdp_pkg is
-------------------------------------------------
-- SDP specific parameters as defined in:
-- L3 SDP Decision: SDP Parameter definitions
- CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
- CONSTANT c_sdp_N_beamsets : NATURAL := 2;
- CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
- CONSTANT c_sdp_N_fft : NATURAL := 1024;
- CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
- CONSTANT c_sdp_N_pn_max : NATURAL := 16;
- CONSTANT c_sdp_N_pol : NATURAL := 2;
- CONSTANT c_sdp_N_pol_bf : NATURAL := 2;
- CONSTANT c_sdp_N_ring_lanes_max : NATURAL := 8;
- CONSTANT c_sdp_N_sub : NATURAL := 512;
- CONSTANT c_sdp_N_taps : NATURAL := 16;
- CONSTANT c_sdp_P_sq : NATURAL := 9;
- CONSTANT c_sdp_Q_fft : NATURAL := 2;
- CONSTANT c_sdp_S_pn : NATURAL := 12;
- CONSTANT c_sdp_S_rcu : NATURAL := 3;
- CONSTANT c_sdp_S_sub_bf : NATURAL := 488;
- CONSTANT c_sdp_V_ring_pkt_len_max : NATURAL := 48; -- for 16 nodes
- CONSTANT c_sdp_V_sample_delay : NATURAL := 4096;
- CONSTANT c_sdp_V_si_db : NATURAL := 1024;
- CONSTANT c_sdp_V_si_db_large : NATURAL := 131072;
- CONSTANT c_sdp_V_si_histogram : NATURAL := 512;
- CONSTANT c_sdp_W_adc : NATURAL := 14;
- CONSTANT c_sdp_W_adc_jesd : NATURAL := 16;
- CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
- CONSTANT c_sdp_W_subband : NATURAL := 18;
- CONSTANT c_sdp_W_crosslet : NATURAL := 16;
- CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
- CONSTANT c_sdp_W_beamlet : NATURAL := 8;
- CONSTANT c_sdp_W_gn_id : NATURAL := 5;
- CONSTANT c_sdp_W_statistic : NATURAL := 64;
+ CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
+ CONSTANT c_sdp_N_beamsets : NATURAL := 2;
+ CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
+ CONSTANT c_sdp_N_fft : NATURAL := 1024;
+ CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
+ CONSTANT c_sdp_N_pn_max : NATURAL := 16;
+ CONSTANT c_sdp_N_pol : NATURAL := 2;
+ CONSTANT c_sdp_N_pol_bf : NATURAL := 2;
+ CONSTANT c_sdp_N_ring_lanes_max : NATURAL := 8;
+ CONSTANT c_sdp_N_sub : NATURAL := 512;
+ CONSTANT c_sdp_N_sync_rcu : NATURAL := 1;
+ CONSTANT c_sdp_N_taps : NATURAL := 16;
+ CONSTANT c_sdp_P_sq : NATURAL := 9;
+ CONSTANT c_sdp_Q_fft : NATURAL := 2;
+ CONSTANT c_sdp_S_pn : NATURAL := 12;
+ CONSTANT c_sdp_S_rcu : NATURAL := 3;
+ CONSTANT c_sdp_S_sub_bf : NATURAL := 488;
+ CONSTANT c_sdp_V_ring_pkt_len_max : NATURAL := 48; -- for 16 nodes
+ CONSTANT c_sdp_V_sample_delay : NATURAL := 4096;
+ CONSTANT c_sdp_V_si_db : NATURAL := 1024;
+ CONSTANT c_sdp_V_si_db_large : NATURAL := 131072;
+ CONSTANT c_sdp_V_si_histogram : NATURAL := 512;
+ CONSTANT c_sdp_W_adc : NATURAL := 14;
+ CONSTANT c_sdp_W_adc_jesd : NATURAL := 16;
+ CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
+ CONSTANT c_sdp_W_subband : NATURAL := 18;
+ CONSTANT c_sdp_W_crosslet : NATURAL := 16;
+ CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
+ CONSTANT c_sdp_W_beamlet : NATURAL := 8;
+ CONSTANT c_sdp_W_gn_id : NATURAL := 5;
+ CONSTANT c_sdp_W_statistic : NATURAL := 64;
CONSTANT c_sdp_W_sub_weight : NATURAL := 16; -- = w in s(w, p), s = signed
CONSTANT c_sdp_W_sub_weight_fraction : NATURAL := 13; -- = p in s(w, p)
CONSTANT c_sdp_W_sub_weight_magnitude : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 2
@@ -109,6 +110,7 @@ PACKAGE sdp_pkg is
-- Derived constants
CONSTANT c_sdp_FS_adc : NATURAL := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0
+ CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft;
CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index a7ce65a423c59fafc5aa03058c1410b9f40105b2..abe7debfc7267ffccaee9193915e765381011f85 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -77,7 +77,7 @@ ENTITY sdp_station IS
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
- JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd -1 DOWNTO 0);
----------------------------------------------
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index a6334d61cb67be4ba700df58768e4eefbb5f308b..ba8c6191dd07fbadc74a6591c3d173487e485862 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -75,9 +75,9 @@ PACKAGE unb2c_board_pkg IS
CONSTANT c_unb2c_board_tr_ring : t_c_unb2c_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
CONSTANT c_unb2c_board_tr_qsfp : t_c_unb2c_board_tr := (6, 4, 0); -- per node: 6 buses with 4 channels
CONSTANT c_unb2c_board_tr_jesd204b : t_c_unb2c_board_tr := (1, 12, 0); -- per node: 1 buses with 12 channels
- CONSTANT c_unb2c_board_nof_tr_jesd204b : NATURAL := 6; --Only 6 channels used in unb2b lab tests
- CONSTANT c_unb2c_board_start_tr_jesd204b : NATURAL := 42; --First transceiver used in unb2b lab tests
- CONSTANT c_unb2c_board_nof_sync_jesd204b : NATURAL := 2; --Only 6 channels used in unb2b lab tests
+ CONSTANT c_unb2c_board_nof_tr_jesd204b : NATURAL := 12; -- 12 channels used in unb2c lab tests
+ CONSTANT c_unb2c_board_start_tr_jesd204b : NATURAL := 0; -- First BCK transceiver used for jesd in unb2c lab tests
+ CONSTANT c_unb2c_board_nof_sync_jesd204b : NATURAL := 4; -- 4 channels used in unb2c lab tests, 1 for each RCU.
CONSTANT c_unb2c_board_tr_qsfp_nof_leds : NATURAL := c_unb2c_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 105a6387e99a03de89c336edede0fb71ffca64d4..e1570a8bb2df4fbb85e2eeb6918610e18963e3c6 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -48,7 +48,7 @@ ENTITY ip_arria10_e1sg_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -125,7 +125,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
- SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 2b2c0162a44161a08587a70db58e15efafb9e457..72263827c36312d13ea97ddcd2c0b11cc28e2d4f 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -48,7 +48,7 @@ ENTITY ip_arria10_e2sg_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -127,7 +127,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
- SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index 96ba775aea6096cd7a8ece8a3caf477462ebe151..d996d3682d5344dbaadd43cf1de9204d669739a2 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -68,7 +68,7 @@ ENTITY tech_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index 2ff054424354a47838c528b57443b32db290de37..c6f97ec3e904b49fc32208a0391e7fe7c0b1e229 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -46,7 +46,7 @@ ENTITY tech_jesd204b_arria10_e2sg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -74,7 +74,8 @@ BEGIN
u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
GENERIC MAP(
g_sim => g_sim,
- g_nof_streams => g_nof_streams,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
g_direction => g_direction
)
PORT MAP(
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 27cee6e928931eafc535d6508252983b194d69d8..7b109077f7c9445b8e33762c4a91776bdfdc0f14 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -47,7 +47,7 @@ PACKAGE tech_jesd204b_component_pkg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -85,7 +85,7 @@ PACKAGE tech_jesd204b_component_pkg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric