diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index 0e403b02febd38781f129a332a9128e7f1b455b1..ae592e5b2967c0692c57ac50ccfaabd95b458b55 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -7,10 +7,12 @@ hdl_lib_technology =
synth_files =
src/vhdl/ddrctrl_address_counter.vhd
src/vhdl/ddrctrl_pack.vhd
+ src/vhdl/ddrctrl_repack.vhd
test_bench_files =
tb/vhdl/tb_ddrctrl_address_counter.vhd
tb/vhdl/tb_ddrctrl_pack.vhd
+ tb/vhdl/tb_ddrctrl_repack.vhd
regression_test_vhdl =
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1898a3e6c8d40633aaf515ba7bb06d2a176dd745
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
@@ -0,0 +1,103 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Resize the input data vector so that the output data vector can be
+-- stored into the ddr memory.
+--
+-- Description:
+-- The input data gets resized and put into the output data vector.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- The output vector must be larger than the input vector.
+
+LIBRARY IEEE, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY ddrctrl_repack IS
+ GENERIC (
+ g_in_data_w : NATURAL := 168;
+ g_out_data_w : NATURAL := 576
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
+ out_of : OUT NATURAL := 0;
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init
+ );
+END ddrctrl_repack;
+
+
+ARCHITECTURE rtl OF ddrctrl_repack IS
+
+ CONSTANT k_c_v_w : NATURAL := g_out_data_w*2;
+
+ SIGNAL c_v_count : NATURAL := 0;
+ SIGNAL out_data_count : NATURAL := 0;
+
+BEGIN
+
+ p_clk : PROCESS(clk)
+
+ VARIABLE a_of :NATURAL := 0;
+ VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ BEGIN
+
+ IF rising_edge(clk) THEN
+
+ IF ((g_in_data_w*(c_v_count+1))+a_of >= g_out_data_w*(out_data_count+1)) THEN -- if the input data exceeds the output data vector width
+
+ IF (out_data_count = 1) THEN -- if the input data exceeds c_v widt
+ ASSERT FALSE REPORT "1" SEVERITY NOTE;
+ a_of := a_of + (g_in_data_w*(c_v_count+1)) - (g_out_data_w*(out_data_count+1)); -- check how much overflow there is and safe it in a_of
+ out_of <= a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector
+ c_v(k_c_v_w - 1 DOWNTO k_c_v_w-(g_in_data_w - a_of)) := in_data(g_in_data_w - a_of - 1 DOWNTO 0); -- fill the rest of c_v untill the end
+ c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of
+ out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO g_out_data_w); -- fill out_sosi.data with 2nd part of c_v
+ out_sosi.valid <= '1'; -- out_sosi.valid 1
+ c_v_count <= 0; -- reset counter
+ out_data_count <= 0; -- reset counter
+
+ Else -- if the input data exceeds output data vector width but not the c_v vector widt
+ ASSERT FALSE REPORT "2" SEVERITY NOTE;
+ c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
+ c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1
+ out_sosi.data(g_out_data_w - 1 DOWNTO 0) <= c_v(g_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
+ out_sosi.valid <= '1'; -- out_sosi.valid 1
+ out_data_count <= out_data_count + 1; -- increase the counter of out_sosi.data with 1
+ END IF;
+
+ ELSE -- if the input data doesn't exceeds the output data vector width
+ c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
+ c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1
+ out_sosi.valid <= '0'; -- out_sosi.valid 0
+
+ END IF;
+
+ END IF;
+
+ END PROCESS;
+
+END rtl;
+
+
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e9b362493dd77fe0fdef348f0e24eb2dd42518bd
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
@@ -0,0 +1,108 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Self checking and self-stopping tb for ddrctrl_repack.vhd
+-- Usage:
+-- > run -a
+
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY tb_ddrctrl_repack IS
+ GENERIC (
+
+ g_in_data_w : NATURAL := 168;
+ g_out_data_w : NATURAL := 576
+
+ );
+END tb_ddrctrl_repack;
+
+ARCHITECTURE tb OF tb_ddrctrl_repack IS
+
+ CONSTANT c_clk_freq : NATURAL := 200; -- MHz
+ CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
+
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL in_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0):= (OTHERS => '0');
+
+ SIGNAL out_of : NATURAL := 0;
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ p_mm : PROCESS
+ BEGIN
+
+ tb_end <= '0';
+
+ WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT FOR c_clk_period*30;
+ WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
+
+ change_in_data : FOR I IN 0 TO 32 LOOP
+ --ASSERT FALSE REPORT "I = " & NATURAL'image(I) SEVERITY NOTE;
+ in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
+ WAIT FOR c_clk_period*1;
+ END LOOP;
+
+ WAIT FOR c_clk_period*5;
+
+ tb_end <= '1';
+
+ WAIT;
+ END PROCESS;
+
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ IF rising_edge(clk) THEN
+ --check_data : FOR I IN 0 TO g_nof_streams - 1 LOOP
+ --ASSERT out_data(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I) = in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) REPORT "Data does not match, I = " & NATURAL'image(I) SEVERITY ERROR;
+ --END LOOP;
+ END IF;
+ END PROCESS;
+
+ u_ddrctrl_repack : ENTITY work.ddrctrl_repack
+ GENERIC MAP (
+ g_in_data_w => g_in_data_w,
+ g_out_data_w => g_out_data_w
+ )
+ PORT MAP (
+ clk => clk,
+ in_data => in_data,
+
+ out_of => out_of,
+ out_sosi => out_sosi
+ );
+
+END tb;
+