diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 7387bca849337e7924e0195584bcf60694162277..a93c20be86985f9cc4251fc7c507b0a47d3aa413 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -307,6 +307,16 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
SIGNAL ram_bf_weights_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL ram_bf_weights_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BF bsn aligner_v2
+ SIGNAL reg_bsn_align_v2_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_align_v2_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2 bsn monitors
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
-- mms_dp_scale Scale Beamlets
SIGNAL reg_bf_scale_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_bf_scale_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -323,6 +333,25 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
SIGNAL ram_st_bst_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL ram_st_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring lane info
+ SIGNAL reg_ring_lane_info_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_lane_info_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor rx
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor tx
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring validate err
+ SIGNAL reg_dp_block_validate_err_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_err_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn at sync
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
@@ -341,22 +370,22 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
-- XST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
- SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
+ SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
- SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
+ SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
-- XST bsn aligner_v2
- SIGNAL reg_bsn_align_v2_copi : t_mem_copi;
- SIGNAL reg_bsn_align_v2_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_align_v2_xsub_copi : t_mem_copi;
+ SIGNAL reg_bsn_align_v2_xsub_cipo : t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_copi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_cipo;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_copi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- XST UDP offload bsn monitor
SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_copi;
@@ -664,7 +693,23 @@ BEGIN
reg_dp_xonoff_copi => reg_dp_xonoff_copi,
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
@@ -689,12 +734,12 @@ BEGIN
reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_v2_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
@@ -839,7 +884,23 @@ BEGIN
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
ram_st_bst_cipo => ram_st_bst_cipo,
-
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
-- SST
reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
@@ -854,12 +915,12 @@ BEGIN
reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_bsn_align_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 3c9f5998dda3e2cd2b739a0c7035bd7e2b47f81a..97f4a99ab25b7dfc11817ebe70ba2d51c77b08ec 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -168,6 +168,16 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
ram_bf_weights_copi : OUT t_mem_copi;
ram_bf_weights_cipo : IN t_mem_cipo;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : IN t_mem_cipo;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : IN t_mem_cipo;
+
-- mms_dp_scale Scale Beamlets
reg_bf_scale_copi : OUT t_mem_copi;
reg_bf_scale_cipo : IN t_mem_cipo;
@@ -180,6 +190,26 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
reg_dp_xonoff_copi : OUT t_mem_copi;
reg_dp_xonoff_cipo : IN t_mem_cipo;
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : OUT t_mem_copi;
+ reg_ring_lane_info_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : IN t_mem_cipo;
+
-- Beamlet Statistics (BST)
ram_st_bst_copi : OUT t_mem_copi;
ram_st_bst_cipo : IN t_mem_cipo;
@@ -233,14 +263,14 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
reg_nw_10GbE_eth10g_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_v2_copi : OUT t_mem_copi;
- reg_bsn_align_v2_cipo : IN t_mem_cipo;
+ reg_bsn_align_v2_xsub_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_copi;
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_cipo;
- reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_copi;
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_rx_align_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : IN t_mem_cipo;
-- XST UDP offload bsn monitor
reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_copi;
@@ -428,40 +458,64 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
PORT MAP(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+
+ u_mm_file_reg_bsn_align_v2_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
- u_mm_file_reg_bsn_align_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_input_copi, reg_bsn_monitor_v2_bsn_align_v2_input_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
+ u_mm_file_reg_ring_lane_info_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+
+ u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
@@ -482,7 +536,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -920,29 +974,53 @@ BEGIN
reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_align_v2_clk_export => OPEN,
- reg_bsn_align_v2_reset_export => OPEN,
- reg_bsn_align_v2_address_export => reg_bsn_align_v2_copi.address(c_sdp_reg_bsn_align_v2_addr_w-1 DOWNTO 0),
- reg_bsn_align_v2_write_export => reg_bsn_align_v2_copi.wr,
- reg_bsn_align_v2_writedata_export => reg_bsn_align_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_align_v2_read_export => reg_bsn_align_v2_copi.rd,
- reg_bsn_align_v2_readdata_export => reg_bsn_align_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_input_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_address_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_write_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_read_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_input_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_output_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_address_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_write_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_v2_output_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_read_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_clk_export => OPEN,
+ reg_bsn_align_v2_bf_reset_export => OPEN,
+ reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
+ reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
+ reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
+ reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
+ reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_align_v2_xsub_clk_export => OPEN,
+ reg_bsn_align_v2_xsub_reset_export => OPEN,
+ reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
+ reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
+ reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
@@ -976,6 +1054,46 @@ BEGIN
reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_clk_export => OPEN,
+ reg_ring_lane_info_bf_reset_export => OPEN,
+ reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
+ reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
+ reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_err_bf_clk_export => OPEN,
+ reg_dp_block_validate_err_bf_reset_export => OPEN,
+ reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
+ reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
+ reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_ring_lane_info_xst_clk_export => OPEN,
reg_ring_lane_info_xst_reset_export => OPEN,
reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 20b9cf3d5a1a27bf384f3e33d35ee91ecd7e7705..380e327a6bc72885dc4b16121b43a70e32146aca 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -10,6 +10,7 @@ synth_files =
src/vhdl/sdp_subband_equalizer.vhd
src/vhdl/sdp_bf_weights.vhd
src/vhdl/sdp_beamformer_local.vhd
+ src/vhdl/sdp_beamformer_remote.vhd
src/vhdl/sdp_info_reg.vhd
src/vhdl/sdp_info.vhd
src/vhdl/sdp_beamformer_output.vhd
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index ebe6a0d76da72e26fc87d3ca54549cac67ba3189..05b1eed4cada981d995f1a2c6692a4f2957acdcc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -49,6 +49,8 @@ ENTITY node_sdp_beamformer IS
dp_rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ from_ri_sosi : IN t_dp_sosi;
+ to_ri_sosi : OUT t_dp_sosi;
bf_udp_sosi : OUT t_dp_sosi;
bf_udp_siso : IN t_dp_siso;
bst_udp_sosi : OUT t_dp_sosi;
@@ -73,10 +75,16 @@ ENTITY node_sdp_beamformer IS
reg_stat_enable_miso : OUT t_mem_miso;
reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_stat_hdr_dat_miso : OUT t_mem_miso;
- reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
- reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo;
- reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
- reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo;
+ reg_bsn_align_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -169,8 +177,27 @@ BEGIN
---------------------------------------------------------------
-- Remote BF
---------------------------------------------------------------
- -- Not yet implemented
- bf_sum_sosi <= local_bf_sosi;
+ u_sdp_beamformer_remote : ENTITY work.sdp_beamformer_remote
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ local_bf_sosi => local_bf_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+ bf_sum_sosi => bf_sum_sosi,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
+ );
---------------------------------------------------------------
-- Scale Beamlets
@@ -260,7 +287,7 @@ BEGIN
-- Streaming clock domain
dp_rst => dp_rst,
dp_clk => dp_clk,
- ref_sync => mon_bf_udp_sosi.sync, -- using in_sosi sync instead of udp_sosi as it has no sync.
+ ref_sync => mon_bf_udp_sosi.sync,
in_sosi_arr(0) => mon_bf_udp_sosi
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 8bff66dd947afaa319f43fdfa3ab7998b8ad44d6..28ce5424a0bd5e346be59c23967b2f9555ddb797 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -22,10 +22,9 @@
--
-- Author: R. van der Walle
-- Purpose:
--- . Implements the functionality of beamformer_local in node_sdp_beamformer.
+-- . Implements the functionality of beamformer_remote in node_sdp_beamformer.
-- Description:
--- The local BF function weights the subbands from the S_pn signal inputs and
--- adds them to form the local beamlet sum.
+-- The remote BF function adds the local and remote sums.
-- Remark:
-- .
-------------------------------------------------------------------------------
@@ -38,57 +37,49 @@ USE dp_lib.dp_stream_pkg.ALL;
USE work.sdp_pkg.ALL;
ENTITY sdp_beamformer_remote IS
- GENERIC (
- g_bf_weights_file_name : STRING := "UNUSED"
- );
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- out_sosi : OUT t_dp_sosi;
+ local_bf_sosi : IN t_dp_sosi;
+ from_ri_sosi : IN t_dp_sosi;
+ to_ri_sosi : OUT t_dp_sosi;
+ bf_sum_sosi : OUT t_dp_sosi;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ reg_bsn_align_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_cipo : OUT t_mem_cipo;
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
- ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_bf_weights_miso : OUT t_mem_miso
+ reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo
);
END sdp_beamformer_remote;
ARCHITECTURE str OF sdp_beamformer_remote IS
- CONSTANT c_data_w : NATURAL := c_nof_complex * c_sdp_W_beamlet_sum;
- CONSTANT c_block_size : NATURAL := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
- CONSTANT c_fifo_size : NATURAL := 2** ceil_log2((c_block_size * 9) / 16); -- 1 block of 64 bit words rounded to the next power of 2 = 1024.
- CONSTANT c_complex_adder_latency : NATURAL := ceil_log2(c_sdp_S_pn);
- CONSTANT c_bf_weights_latency : NATURAL := 3;
- CONSTANT c_total_latency : NATURAL := 4 + c_bf_weights_latency + c_complex_adder_latency;
-
- CONSTANT c_complex_adder_sum_w : NATURAL := c_sdp_W_bf_product + ceil_log2(c_sdp_S_pn);
-
- SIGNAL sub_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol_bf*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL bf_weights_out_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol_bf*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL bf_weights_x_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL bf_weights_y_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL deinterleaved_x_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL deinterleaved_y_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL interleave_out_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL complex_add_out_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL pipelined_in_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL dp_requantize_in_sosi : t_dp_sosi := c_dp_sosi_rst;
-
+ CONSTANT c_data_w : NATURAL := c_nof_complex * c_sdp_W_beamlet_sum;
+ CONSTANT c_block_size : NATURAL := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
+ CONSTANT c_fifo_size : NATURAL := 2** ceil_log2((c_block_size * 9) / 16); -- 1 block of 64 bit words rounded to the next power of 2 = 1024.
+
+ SIGNAL dispatch_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- 1 for local, 1 for remote.
+ SIGNAL dp_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL dp_fifo_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL beamlets_data_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL beamlets_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL i_bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL bf_sum_data_sosi : t_dp_sosi := c_dp_sosi_rst;
BEGIN
-
- dispatch_sosi_arr(0) <= local_bf_sosi;
-
-
-- repacking beamlets re/im to data field.
p_wire_local_bf_sosi : PROCESS(local_bf_sosi)
BEGIN
dispatch_sosi_arr(0) <= local_bf_sosi;
- dispatch_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= local_bf_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
- dispatch_sosi_arr(0).data(c_nof_complex * c_sdp_W_beamlet_sum -1 DOWNTO c_sdp_W_beamlet_sum) <= local_bf_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ dispatch_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= local_bf_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ dispatch_sosi_arr(0).data(c_data_w -1 DOWNTO c_sdp_W_beamlet_sum) <= local_bf_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
END PROCESS;
---------------------------------------------------------------
@@ -120,7 +111,7 @@ BEGIN
g_in_nof_words => 9,
g_out_dat_w => c_data_w,
g_out_nof_words => 16,
- g_pipeline_ready => TRUE -- Needed for src_in.ready to snk_out.ready.
+ g_pipeline_ready => TRUE
)
PORT MAP (
rst => dp_rst,
@@ -177,13 +168,12 @@ BEGIN
BEGIN
beamlets_sosi_arr(0) <= beamlets_data_sosi_arr(0);
beamlets_sosi_arr(1) <= beamlets_data_sosi_arr(1);
- beamlets_sosi_arr(0).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data( c_sdp_W_beamlet_sum -1 DOWNTO 0);
- beamlets_sosi_arr(0).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data(c_nof_complex * c_sdp_W_beamlet_sum -1 DOWNTO c_sdp_W_beamlet_sum);
- beamlets_sosi_arr(1).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data( c_sdp_W_beamlet_sum -1 DOWNTO 0);
- beamlets_sosi_arr(1).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data(c_nof_complex * c_sdp_W_beamlet_sum -1 DOWNTO c_sdp_W_beamlet_sum);
+ beamlets_sosi_arr(0).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0);
+ beamlets_sosi_arr(0).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum);
+ beamlets_sosi_arr(1).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data(c_sdp_W_beamlet_sum -1 DOWNTO 0);
+ beamlets_sosi_arr(1).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum);
END PROCESS;
-
---------------------------------------------------------------
-- ADD
---------------------------------------------------------------
@@ -197,19 +187,20 @@ BEGIN
clk => dp_clk,
snk_in_arr => beamlets_sosi_arr,
- src_out => i_bf_sum_sosi
+ src_out => i_bf_sum_sosi
);
bf_sum_sosi <= i_bf_sum_sosi;
+
---------------------------------------------------------------
-- Repack 36b to 64b
---------------------------------------------------------------
- -- repacking xsel re/im to data field.
- p_wire_xsel_sosi : PROCESS(xsel_sosi)
+ -- repacking bf_sum re/im to data field.
+ p_wire_bf_sum_sosi : PROCESS(i_bf_sum_sosi)
BEGIN
- xsel_data_sosi <= xsel_sosi;
- xsel_data_sosi.data( c_sdp_W_crosslet -1 DOWNTO 0) <= xsel_sosi.re(c_sdp_W_crosslet-1 DOWNTO 0);
- xsel_data_sosi.data(c_nof_complex * c_sdp_W_crosslet -1 DOWNTO c_sdp_W_crosslet) <= xsel_sosi.im(c_sdp_W_crosslet-1 DOWNTO 0);
+ bf_sum_data_sosi <= i_bf_sum_sosi;
+ bf_sum_data_sosi.data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ bf_sum_data_sosi.data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum) <= i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
END PROCESS;
u_dp_repack_data_local : ENTITY dp_lib.dp_repack_data
@@ -218,16 +209,14 @@ BEGIN
g_in_nof_words => 16,
g_out_dat_w => c_longword_w,
g_out_nof_words => 9,
- g_pipeline_ready => TRUE -- Needed for src_in.ready to snk_out.ready.
+ g_pipeline_ready => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
- snk_in => i_bf_sum_sosi,
- src_out => to_ri_sosi_sosi
+ snk_in => bf_sum_data_sosi,
+ src_out => to_ri_sosi
);
-
-
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 58548487f710ad963396e60dec61c2697878288a..d0c32782b256cbd0d93903a0894f8319e74e5040 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -442,16 +442,24 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_stat_enable_addr_w : NATURAL := 1;
-- BF MM address widths
- CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
- CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
- CONSTANT c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- CONSTANT c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
+ CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_align_v2_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(2*2);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(2) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_ring_lane_info_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_dp_block_validate_err_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 4;
+ CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 2;
-- XSUB
CONSTANT c_sdp_crosslets_index_w : NATURAL := ceil_log2(c_sdp_N_sub);
@@ -483,9 +491,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
CONSTANT c_sdp_ram_st_xsq_arr_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
- CONSTANT c_sdp_reg_bsn_align_v2_addr_w : NATURAL := ceil_log2(2*c_sdp_P_sq);
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_align_v2_xsub_addr_w : NATURAL := ceil_log2(2*c_sdp_P_sq);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w : NATURAL := 1;
CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 528ce3d5d74364c88bb0062061a910d2e6355643..fbc27de1c475995bc018f359549195699a0ed7a0 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -213,6 +213,16 @@ ENTITY sdp_station IS
ram_bf_weights_copi : IN t_mem_copi := c_mem_copi_rst;
ram_bf_weights_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_v2_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_aligned_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_aligned_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
-- mms_dp_scale Scale Beamlets
reg_bf_scale_copi : IN t_mem_copi := c_mem_copi_rst;
reg_bf_scale_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
@@ -237,70 +247,88 @@ ENTITY sdp_station IS
reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_lane_info_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_err_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_sst_copi : IN t_mem_copi;
- reg_stat_enable_sst_cipo : OUT t_mem_cipo;
+ reg_stat_enable_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_sst_copi : IN t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : OUT t_mem_cipo;
+ reg_stat_hdr_dat_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_xst_copi : IN t_mem_copi;
- reg_stat_enable_xst_cipo : OUT t_mem_cipo;
+ reg_stat_enable_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_xst_copi : IN t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : OUT t_mem_cipo;
+ reg_stat_hdr_dat_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST bsn aligner_v2
- reg_bsn_align_copi : IN t_mem_copi;
- reg_bsn_align_cipo : OUT t_mem_cipo;
+ reg_bsn_align_v2_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_v2_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi;
- reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
- reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi;
- reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_rx_align_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_aligned_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : IN t_mem_copi;
- reg_ring_lane_info_xst_cipo : OUT t_mem_cipo;
+ reg_ring_lane_info_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_lane_info_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : IN t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : OUT t_mem_cipo;
+ reg_dp_block_validate_err_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_err_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_cipo;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : IN t_mem_copi;
- reg_tr_10GbE_mac_cipo : OUT t_mem_cipo;
+ reg_tr_10GbE_mac_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_tr_10GbE_mac_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : IN t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : OUT t_mem_cipo;
+ reg_tr_10GbE_eth10g_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_tr_10GbE_eth10g_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
@@ -345,33 +373,39 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
-- Address widths of a single MM instance
- CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
- CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
- CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
- CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
-
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ CONSTANT c_addr_w_reg_bsn_align_v2_bf : NATURAL := ceil_log2(2*2);
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_rx_align_bf : NATURAL := ceil_log2(2) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_tx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
CONSTANT c_use_dp_layer : BOOLEAN := TRUE;
- CONSTANT c_lane_packet_length : NATURAL := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size devided by 2 as it is repacked from 32b to 64b.
+ CONSTANT c_lane_packet_length_xst : NATURAL := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size devided by 2 as it is repacked from 32b to 64b. = 42
+ CONSTANT c_lane_packet_length_bf : NATURAL := (c_sdp_S_sub_bf * c_sdp_N_pol_bf * 9) / 16; -- = beamlet block size repacked from 36b to 64b. = 549
CONSTANT c_err_bi : NATURAL := 0;
CONSTANT c_nof_err_counts : NATURAL := 8;
CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1;
CONSTANT c_validate_channel : BOOLEAN := TRUE;
CONSTANT c_validate_channel_mode : STRING := "=";
CONSTANT c_sync_timeout : NATURAL := sel_a_b(g_sim, g_sim_sync_timeout, c_sdp_N_clk_sync_timeout );
- CONSTANT c_xsub_fifo_tx_fill : NATURAL := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total packet length
- CONSTANT c_xsub_fifo_tx_size : NATURAL := 2 * c_lane_packet_length;
+ CONSTANT c_xsub_fifo_tx_fill : NATURAL := c_lane_packet_length_bf + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total max packet length (bf has largest packets)
+ CONSTANT c_xsub_fifo_tx_size : NATURAL := 2 * c_lane_packet_length_bf;
+ CONSTANT c_nof_lane : NATURAL := 3; -- 0 = XST, 1 = BF_0, 2 = BF_1.
CONSTANT c_nof_if : NATURAL := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
CONSTANT c_qsfp_if_offset : NATURAL := 0; -- QSFP signals are indexed at c_nof_if * I.
CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
- CONSTANT c_nof_mac : NATURAL := 3; -- must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
+ CONSTANT c_nof_mac : NATURAL := 12; -- Using 9, must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
SIGNAL gn_index : NATURAL := 0;
SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
@@ -402,6 +436,38 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL ram_st_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
SIGNAL ram_st_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+ -- BF bsn align v2
+ SIGNAL reg_bsn_align_v2_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_align_v2_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF bsn monitor v2 rx align
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF bsn monitor v2 aligned
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring lane info
+ SIGNAL reg_ring_lane_info_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_ring_lane_info_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn monitor rx
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn monitor tx
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring validate err
+ SIGNAL reg_dp_block_validate_err_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_block_validate_err_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn at sync
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
----------------------------------------------
-- BST
----------------------------------------------
@@ -427,11 +493,13 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL bs_sosi : t_dp_sosi;
SIGNAL xst_from_ri_sosi : t_dp_sosi;
- SIGNAL xst_to_ri_sosi : t_dp_sosi;
- SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
+ SIGNAL xst_to_ri_sosi : t_dp_sosi;
+ SIGNAL bf_from_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_to_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL dp_bsn_source_restart : STD_LOGIC;
@@ -678,12 +746,12 @@ BEGIN
reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
@@ -695,132 +763,6 @@ BEGIN
stat_udp_src_port => xst_udp_src_port
);
- gen_use_xsub_ring : IF g_use_ring GENERATE
- u_ring_lane_xst : ENTITY ring_lib.ring_lane
- GENERIC MAP (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => xst_from_ri_sosi,
- to_lane_sosi => xst_to_ri_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
-
- -----------------------------------------------------------------------------
- -- Combine seperate signals into array for tr_10GbE
- -----------------------------------------------------------------------------
- -- QSFP_RX
- lane_rx_cable_sosi_arr(0) <= tr_10gbe_src_out_arr(c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
- -- QSFP_TX
- tr_10gbe_snk_in_arr(c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(0) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> even lanes transmit to cable
-
- -- RING_0_RX even lanes receive from RING_0 (from the left)
- lane_rx_board_sosi_arr(0) <= tr_10gbe_src_out_arr(c_ring_0_if_offset);
-
- -- RING_1_TX even lanes transmit to RING_1 (to the right)
- tr_10gbe_snk_in_arr(c_ring_1_if_offset) <= lane_tx_board_sosi_arr(0);
-
- -----------------------------------------------------------------------------
- -- tr_10GbE
- -----------------------------------------------------------------------------
- u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_xsub_fifo_tx_fill,
- g_tx_fifo_size => c_xsub_fifo_tx_size
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
-
-
- -----------------------------------------------------------------------------
- -- Seperate serial tx/rx array
- -----------------------------------------------------------------------------
- -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
- -- QSFP port, RING_0 port and RING_1 port.
- -- QSFP_TX
- unb2_board_front_io_serial_tx_arr(0) <= tr_10gbe_serial_tx_arr(c_qsfp_if_offset);
- -- QSFP_RX
- tr_10gbe_serial_rx_arr(c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(0);
-
- -- RING_0_TX
- RING_0_TX(0) <= tr_10gbe_serial_tx_arr(c_ring_0_if_offset);
- -- RING_0_RX
- tr_10gbe_serial_rx_arr(c_ring_0_if_offset) <= RING_0_RX(0);
-
- -- RING_1_TX
- RING_1_TX(0) <= tr_10gbe_serial_tx_arr(c_ring_1_if_offset);
- -- RING_1_RX
- tr_10gbe_serial_rx_arr(c_ring_1_if_offset) <= RING_1_RX(0);
- END GENERATE;
END GENERATE;
-----------------------------------------------------------------------------
@@ -840,7 +782,9 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- in_sosi_arr => fsub_sosi_arr,
+ in_sosi_arr => fsub_sosi_arr,
+ from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
bf_udp_siso => bf_udp_siso_arr(beamset_id),
bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
@@ -864,11 +808,17 @@ BEGIN
reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
+ reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
sdp_info => sdp_info,
gn_id => gn_id,
@@ -909,7 +859,19 @@ BEGIN
mosi_arr => ram_bf_weights_copi_arr,
miso_arr => ram_bf_weights_cipo_arr
);
-
+
+ u_mem_mux_reg_bsn_align_v2_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_align_v2_bf_copi,
+ miso => reg_bsn_align_v2_bf_cipo,
+ mosi_arr => reg_bsn_align_v2_bf_copi_arr,
+ miso_arr => reg_bsn_align_v2_bf_cipo_arr
+ );
+
u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => c_sdp_N_beamsets,
@@ -981,6 +943,30 @@ BEGIN
mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
miso_arr => reg_stat_hdr_dat_bst_cipo_arr
);
+
+ u_mem_mux_reg_bsn_monitor_v2_rx_align_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_aligned_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_aligned_bf_copi,
+ miso => reg_bsn_monitor_v2_aligned_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_bst_offload : ENTITY common_lib.common_mem_mux
GENERIC MAP (
@@ -1083,6 +1069,249 @@ BEGIN
);
END GENERATE;
+ gen_use_ring : IF g_use_ring GENERATE
+ gen_xst_ring : IF g_use_xsub GENERATE
+ u_ring_lane_xst : ENTITY ring_lib.ring_lane
+ GENERIC MAP (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_packet_length_xst,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => xst_from_ri_sosi,
+ to_lane_sosi => xst_to_ri_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
+ END GENERATE;
+
+ gen_bf_ring : IF g_use_bf GENERATE
+ gen_beamset_ring : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
+ u_ring_lane_bf : ENTITY ring_lib.ring_lane
+ GENERIC MAP (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_packet_length_bf,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
+ bs_sosi => fsub_sosi_arr(0), -- used for bsn and sync
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
+ END GENERATE;
+
+
+ u_mem_mux_reg_ring_lane_info_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_ring_lane_info_addr_w
+ )
+ PORT MAP (
+ mosi => reg_ring_lane_info_bf_copi,
+ miso => reg_ring_lane_info_bf_cipo,
+ mosi_arr => reg_ring_lane_info_bf_copi_arr,
+ miso_arr => reg_ring_lane_info_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_dp_block_validate_err_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
+ )
+ PORT MAP (
+ mosi => reg_dp_block_validate_err_bf_copi,
+ miso => reg_dp_block_validate_err_bf_cipo,
+ mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_err_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_dp_block_validate_bsn_at_sync_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
+ )
+ PORT MAP (
+ mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
+ );
+ END GENERATE;
+ -----------------------------------------------------------------------------
+ -- Combine seperate signals into array for tr_10GbE
+ -----------------------------------------------------------------------------
+ gen_lane_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
+ -- QSFP_RX
+ lane_rx_cable_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
+
+ -- QSFP_TX
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(I) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> even lanes transmit to cable
+
+ -- RING_0_RX even lanes receive from RING_0 (from the left)
+ lane_rx_board_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
+
+ -- RING_1_TX even lanes transmit to RING_1 (to the right)
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_ring_1_if_offset) <= lane_tx_board_sosi_arr(I);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- tr_10GbE
+ -----------------------------------------------------------------------------
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_xsub_fifo_tx_fill,
+ g_tx_fifo_size => c_xsub_fifo_tx_size
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Seperate serial tx/rx array
+ -----------------------------------------------------------------------------
+ -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
+ -- QSFP port, RING_0 port and RING_1 port.
+ gen_serial_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
+ -- QSFP_TX
+ unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_qsfp_if_offset);
+ -- QSFP_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(I);
+
+ -- RING_0_TX
+ RING_0_TX(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_0_if_offset);
+ -- RING_0_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_0_if_offset) <= RING_0_RX(I);
+
+ -- RING_1_TX
+ RING_1_TX(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_1_if_offset);
+ -- RING_1_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_1_if_offset) <= RING_1_RX(I);
+ END GENERATE;
+ END GENERATE;
+
---------
-- PLL
---------