From 09609accaf94e87138fdbe52d0e7c14c0b8afd12 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 9 Jun 2015 15:25:36 +0000
Subject: [PATCH] update for 10GbE revision with 1 QSFP
---
boards/uniboard2/designs/unb2_test/doc/README | 2 +-
.../unb2_test/quartus/qsys_unb2_test.qsys | 686 +++---------------
.../unb2_test_10GbE/unb2_test_10GbE.vhd | 64 +-
.../designs/unb2_test/src/vhdl/ddr_stream.vhd | 6 +-
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 305 +++++---
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 649 ++++++++---------
.../designs/unb2_test/src/vhdl/udp_stream.vhd | 31 +-
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 312 ++++++--
.../unb2_test/src/vhdl/unb2_test_pkg.vhd | 22 +-
.../unb2_test/tb/python/tc_unb2_test.py | 116 ++-
.../unb2_test/tb/vhdl/tb_unb2_test.vhd | 46 +-
11 files changed, 1013 insertions(+), 1226 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index d79985a8f1..06127c7872 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -32,7 +32,7 @@ Modelsim instructions:
# while the simulation runs... in another bash session do:
cd unb2_test/tb/python
- python tc_unb2_test.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS
+ python tc_unb2_test.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
# (sensor results only show up after 1000us of simulation runtime)
diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index 1e8ae179e9..bf07dfab05 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -29,7 +29,7 @@
{
datum baseAddress
{
- value = "40960";
+ value = "32768";
type = "String";
}
}
@@ -37,7 +37,7 @@
{
datum baseAddress
{
- value = "53312";
+ value = "704";
type = "String";
}
}
@@ -45,7 +45,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "24576";
type = "String";
}
}
@@ -61,7 +61,7 @@
{
datum baseAddress
{
- value = "36864";
+ value = "28672";
type = "String";
}
}
@@ -69,7 +69,7 @@
{
datum baseAddress
{
- value = "53248";
+ value = "640";
type = "String";
}
}
@@ -117,7 +117,7 @@
{
datum baseAddress
{
- value = "53848";
+ value = "1352";
type = "String";
}
}
@@ -162,7 +162,7 @@
{
datum baseAddress
{
- value = "53840";
+ value = "1344";
type = "String";
}
}
@@ -194,7 +194,7 @@
{
datum baseAddress
{
- value = "53776";
+ value = "1248";
type = "String";
}
}
@@ -210,7 +210,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "35";
type = "int";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "16384";
+ value = "524288";
type = "String";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "40";
+ value = "34";
type = "int";
}
}
@@ -234,7 +234,7 @@
{
datum baseAddress
{
- value = "49152";
+ value = "40960";
type = "String";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "36";
type = "int";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "45056";
+ value = "36864";
type = "String";
}
}
@@ -258,7 +258,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "29";
type = "int";
}
}
@@ -274,7 +274,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "28";
type = "int";
}
}
@@ -290,7 +290,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "30";
type = "int";
}
}
@@ -306,7 +306,7 @@
{
datum _sortIndex
{
- value = "43";
+ value = "37";
type = "int";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "16384";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "53440";
+ value = "896";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "53376";
+ value = "832";
type = "String";
}
}
@@ -370,7 +370,7 @@
{
datum _sortIndex
{
- value = "38";
+ value = "32";
type = "int";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "53536";
+ value = "1056";
type = "String";
}
}
@@ -386,7 +386,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "31";
type = "int";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "53632";
+ value = "1120";
type = "String";
}
}
@@ -402,7 +402,7 @@
{
datum _sortIndex
{
- value = "39";
+ value = "33";
type = "int";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "53600";
+ value = "1088";
type = "String";
}
}
@@ -418,7 +418,7 @@
{
datum _sortIndex
{
- value = "32";
+ value = "26";
type = "int";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "12416";
+ value = "256";
type = "String";
}
}
@@ -434,7 +434,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "25";
type = "int";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "13184";
+ value = "512";
type = "String";
}
}
@@ -450,7 +450,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "27";
type = "int";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "13056";
+ value = "384";
type = "String";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "48";
+ value = "42";
type = "int";
}
}
@@ -482,7 +482,7 @@
{
datum _sortIndex
{
- value = "46";
+ value = "40";
type = "int";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "53504";
+ value = "1024";
type = "String";
}
}
@@ -498,7 +498,7 @@
{
datum _sortIndex
{
- value = "50";
+ value = "44";
type = "int";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "992";
type = "String";
}
}
@@ -514,7 +514,7 @@
{
datum _sortIndex
{
- value = "47";
+ value = "41";
type = "int";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "768";
type = "String";
}
}
@@ -530,7 +530,7 @@
{
datum _sortIndex
{
- value = "45";
+ value = "39";
type = "int";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "53760";
+ value = "1280";
type = "String";
}
}
@@ -546,7 +546,7 @@
{
datum _sortIndex
{
- value = "49";
+ value = "43";
type = "int";
}
}
@@ -554,103 +554,7 @@
{
datum baseAddress
{
- value = "12304";
- type = "String";
- }
- }
- element reg_dp_offload_rx_10gbe_hdr_dat
- {
- datum _sortIndex
- {
- value = "30";
- type = "int";
- }
- }
- element reg_dp_offload_rx_10gbe_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "1024";
- type = "String";
- }
- }
- element reg_dp_offload_rx_1gbe_hdr_dat
- {
- datum _sortIndex
- {
- value = "29";
- type = "int";
- }
- }
- element reg_dp_offload_rx_1gbe_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "12544";
- type = "String";
- }
- }
- element reg_dp_offload_tx_10gbe
- {
- datum _sortIndex
- {
- value = "26";
- type = "int";
- }
- }
- element reg_dp_offload_tx_10gbe.mem
- {
- datum baseAddress
- {
- value = "512";
- type = "String";
- }
- }
- element reg_dp_offload_tx_10gbe_hdr_dat
- {
- datum _sortIndex
- {
- value = "28";
- type = "int";
- }
- }
- element reg_dp_offload_tx_10gbe_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "13312";
- type = "String";
- }
- }
- element reg_dp_offload_tx_1gbe
- {
- datum _sortIndex
- {
- value = "25";
- type = "int";
- }
- }
- element reg_dp_offload_tx_1gbe.mem
- {
- datum baseAddress
- {
- value = "12296";
- type = "String";
- }
- }
- element reg_dp_offload_tx_1gbe_hdr_dat
- {
- datum _sortIndex
- {
- value = "27";
- type = "int";
- }
- }
- element reg_dp_offload_tx_1gbe_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "12800";
+ value = "1264";
type = "String";
}
}
@@ -666,7 +570,7 @@
{
datum baseAddress
{
- value = "53832";
+ value = "1336";
type = "String";
}
}
@@ -682,7 +586,7 @@
{
datum baseAddress
{
- value = "53824";
+ value = "1328";
type = "String";
}
}
@@ -698,7 +602,7 @@
{
datum baseAddress
{
- value = "53664";
+ value = "1152";
type = "String";
}
}
@@ -706,7 +610,7 @@
{
datum _sortIndex
{
- value = "44";
+ value = "38";
type = "int";
}
}
@@ -714,7 +618,7 @@
{
datum baseAddress
{
- value = "53792";
+ value = "1296";
type = "String";
}
}
@@ -730,7 +634,7 @@
{
datum baseAddress
{
- value = "53816";
+ value = "1320";
type = "String";
}
}
@@ -746,7 +650,7 @@
{
datum baseAddress
{
- value = "53808";
+ value = "1312";
type = "String";
}
}
@@ -762,7 +666,7 @@
{
datum baseAddress
{
- value = "53696";
+ value = "1184";
type = "String";
}
}
@@ -826,7 +730,7 @@
{
datum baseAddress
{
- value = "53728";
+ value = "1216";
type = "String";
}
}
@@ -884,7 +788,7 @@
{
datum baseAddress
{
- value = "53568";
+ value = "960";
type = "String";
}
}
@@ -1937,216 +1841,6 @@
internal="reg_diag_tx_seq_ddr.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_address"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_clk"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_read"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_readdata"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_reset"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_write"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_10gbe_hdr_dat_writedata"
- internal="reg_dp_offload_rx_10gbe_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_address"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_clk"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_read"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_readdata"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_reset"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_write"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_rx_1gbe_hdr_dat_writedata"
- internal="reg_dp_offload_rx_1gbe_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_address"
- internal="reg_dp_offload_tx_10gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_clk"
- internal="reg_dp_offload_tx_10gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_address"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_clk"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_read"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_readdata"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_reset"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_write"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_hdr_dat_writedata"
- internal="reg_dp_offload_tx_10gbe_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_read"
- internal="reg_dp_offload_tx_10gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_readdata"
- internal="reg_dp_offload_tx_10gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_reset"
- internal="reg_dp_offload_tx_10gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_write"
- internal="reg_dp_offload_tx_10gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_10gbe_writedata"
- internal="reg_dp_offload_tx_10gbe.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_address"
- internal="reg_dp_offload_tx_1gbe.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_clk"
- internal="reg_dp_offload_tx_1gbe.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_address"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_clk"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_read"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_readdata"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_reset"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_write"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_hdr_dat_writedata"
- internal="reg_dp_offload_tx_1gbe_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_read"
- internal="reg_dp_offload_tx_1gbe.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_readdata"
- internal="reg_dp_offload_tx_1gbe.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_reset"
- internal="reg_dp_offload_tx_1gbe.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_write"
- internal="reg_dp_offload_tx_1gbe.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_1gbe_writedata"
- internal="reg_dp_offload_tx_1gbe.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_dpmm_ctrl_address"
internal="reg_dpmm_ctrl.address"
@@ -2630,7 +2324,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_10gbe.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_10gbe_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_dp_offload_tx_1gbe.mem' start='0x3008' end='0x3010' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x3010' end='0x3020' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3020' end='0x3040' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x3080' end='0x3100' /><slave name='reg_dp_offload_rx_1gbe_hdr_dat.mem' start='0x3100' end='0x3200' /><slave name='reg_dp_offload_tx_1gbe_hdr_dat.mem' start='0x3200' end='0x3300' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3300' end='0x3380' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x3380' end='0x3400' /><slave name='reg_dp_offload_tx_10gbe_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10gbe.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_tse' start='0x8000' end='0x9000' /><slave name='avs_eth_1.mms_ram' start='0x9000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_ddr.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_1gbe.mem' start='0xC000' end='0xD000' /><slave name='avs_eth_1.mms_reg' start='0xD000' end='0xD040' /><slave name='avs_eth_0.mms_reg' start='0xD040' end='0xD080' /><slave name='reg_bsn_monitor_ddr.mem' start='0xD080' end='0xD0C0' /><slave name='reg_bsn_monitor_1GbE.mem' start='0xD0C0' end='0xD100' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0xD100' end='0xD120' /><slave name='reg_diag_bg_10gbe.mem' start='0xD120' end='0xD140' /><slave name='timer_0.s1' start='0xD140' end='0xD160' /><slave name='reg_diag_bg_ddr.mem' start='0xD160' end='0xD180' /><slave name='reg_diag_bg_1gbe.mem' start='0xD180' end='0xD1A0' /><slave name='reg_epcs.mem' start='0xD1A0' end='0xD1C0' /><slave name='reg_remu.mem' start='0xD1C0' end='0xD1E0' /><slave name='reg_unb_sens.mem' start='0xD1E0' end='0xD200' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0xD200' end='0xD210' /><slave name='pio_wdi.s1' start='0xD210' end='0xD220' /><slave name='reg_io_ddr.mem' start='0xD220' end='0xD230' /><slave name='reg_mmdp_data.mem' start='0xD230' end='0xD238' /><slave name='reg_mmdp_ctrl.mem' start='0xD238' end='0xD240' /><slave name='reg_dpmm_data.mem' start='0xD240' end='0xD248' /><slave name='reg_dpmm_ctrl.mem' start='0xD248' end='0xD250' /><slave name='pio_pps.mem' start='0xD250' end='0xD258' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xD258' end='0xD260' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_ss_ss_wide.mem' start='0x40000' end='0x50000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x50000' end='0x60000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x60000' end='0x70000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x200' end='0x280' /><slave name='avs_eth_1.mms_reg' start='0x280' end='0x2C0' /><slave name='avs_eth_0.mms_reg' start='0x2C0' end='0x300' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x300' end='0x340' /><slave name='reg_bsn_monitor_ddr.mem' start='0x340' end='0x380' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x380' end='0x3C0' /><slave name='timer_0.s1' start='0x3C0' end='0x3E0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3E0' end='0x400' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x400' end='0x420' /><slave name='reg_diag_bg_10gbe.mem' start='0x420' end='0x440' /><slave name='reg_diag_bg_ddr.mem' start='0x440' end='0x460' /><slave name='reg_diag_bg_1gbe.mem' start='0x460' end='0x480' /><slave name='reg_epcs.mem' start='0x480' end='0x4A0' /><slave name='reg_remu.mem' start='0x4A0' end='0x4C0' /><slave name='reg_unb_sens.mem' start='0x4C0' end='0x4E0' /><slave name='pio_wdi.s1' start='0x4E0' end='0x4F0' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x4F0' end='0x500' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x500' end='0x510' /><slave name='reg_io_ddr.mem' start='0x510' end='0x520' /><slave name='reg_mmdp_data.mem' start='0x520' end='0x528' /><slave name='reg_mmdp_ctrl.mem' start='0x528' end='0x530' /><slave name='reg_dpmm_data.mem' start='0x530' end='0x538' /><slave name='reg_dpmm_ctrl.mem' start='0x538' end='0x540' /><slave name='pio_pps.mem' start='0x540' end='0x548' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x548' end='0x550' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_tse' start='0x6000' end='0x7000' /><slave name='avs_eth_1.mms_ram' start='0x7000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_bg_ddr.mem' start='0x9000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xB000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_ss_ss_wide.mem' start='0x40000' end='0x50000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x50000' end='0x60000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -2864,7 +2558,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="12" />
+ <parameter name="g_adr_w" value="17" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -2919,7 +2613,7 @@
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="6" />
+ <parameter name="g_adr_w" value="11" />
<parameter name="g_dat_w" value="32" />
</module>
<module
@@ -3044,60 +2738,6 @@
<parameter name="g_adr_w" value="2" />
<parameter name="g_dat_w" value="32" />
</module>
- <module
- name="reg_dp_offload_rx_10gbe_hdr_dat"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="8" />
- <parameter name="g_dat_w" value="32" />
- </module>
- <module
- name="reg_dp_offload_rx_1gbe_hdr_dat"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="6" />
- <parameter name="g_dat_w" value="32" />
- </module>
- <module
- name="reg_dp_offload_tx_10gbe"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="7" />
- <parameter name="g_dat_w" value="32" />
- </module>
- <module
- name="reg_dp_offload_tx_10gbe_hdr_dat"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="8" />
- <parameter name="g_dat_w" value="32" />
- </module>
- <module
- name="reg_dp_offload_tx_1gbe"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- </module>
- <module
- name="reg_dp_offload_tx_1gbe_hdr_dat"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <parameter name="g_adr_w" value="6" />
- <parameter name="g_dat_w" value="32" />
- </module>
<module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="1" />
@@ -3193,7 +2833,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd258" />
+ <parameter name="baseAddress" value="0x0548" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3211,7 +2851,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd1e0" />
+ <parameter name="baseAddress" value="0x04c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3238,7 +2878,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd250" />
+ <parameter name="baseAddress" value="0x0540" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3256,7 +2896,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd1c0" />
+ <parameter name="baseAddress" value="0x04a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3265,7 +2905,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd1a0" />
+ <parameter name="baseAddress" value="0x0480" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3274,7 +2914,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd248" />
+ <parameter name="baseAddress" value="0x0538" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3283,7 +2923,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd240" />
+ <parameter name="baseAddress" value="0x0530" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3292,7 +2932,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd238" />
+ <parameter name="baseAddress" value="0x0528" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3301,7 +2941,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd230" />
+ <parameter name="baseAddress" value="0x0520" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3319,34 +2959,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd0c0" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3008" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_1gbe_hdr_dat.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_rx_1gbe_hdr_dat.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x0380" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3355,7 +2968,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3380" />
+ <parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3373,7 +2986,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd180" />
+ <parameter name="baseAddress" value="0x0460" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3382,7 +2995,7 @@
start="cpu_0.data_master"
end="ram_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xc000" />
+ <parameter name="baseAddress" value="0xa000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3409,7 +3022,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd080" />
+ <parameter name="baseAddress" value="0x0340" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3418,7 +3031,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd160" />
+ <parameter name="baseAddress" value="0x0440" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3427,7 +3040,7 @@
start="cpu_0.data_master"
end="ram_diag_bg_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xb000" />
+ <parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3436,7 +3049,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0x0180" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3463,7 +3076,7 @@
start="cpu_0.data_master"
end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd220" />
+ <parameter name="baseAddress" value="0x0510" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3472,34 +3085,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_10gbe.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_10gbe_hdr_dat.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
- <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
- kind="avalon"
- version="15.0"
- start="cpu_0.data_master"
- end="reg_dp_offload_rx_10gbe_hdr_dat.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3508,7 +3094,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3526,7 +3112,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd120" />
+ <parameter name="baseAddress" value="0x0420" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3535,7 +3121,7 @@
start="cpu_0.data_master"
end="ram_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x00080000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3544,7 +3130,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd200" />
+ <parameter name="baseAddress" value="0x0500" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3553,7 +3139,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd100" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3562,7 +3148,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0300" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3580,7 +3166,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x04f0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3589,7 +3175,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x03e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3598,7 +3184,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xa000" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3607,7 +3193,7 @@
start="cpu_0.data_master"
end="avs_eth_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x9000" />
+ <parameter name="baseAddress" value="0x7000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3616,7 +3202,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd040" />
+ <parameter name="baseAddress" value="0x02c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3625,7 +3211,7 @@
start="cpu_0.data_master"
end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd000" />
+ <parameter name="baseAddress" value="0x0280" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3634,7 +3220,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_tse">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x6000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3661,7 +3247,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd210" />
+ <parameter name="baseAddress" value="0x04e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3670,7 +3256,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xd140" />
+ <parameter name="baseAddress" value="0x03c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -3751,21 +3337,6 @@
version="15.0"
start="clk_0.clk"
end="reg_bsn_monitor_1GbE.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_tx_1gbe.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_rx_1gbe_hdr_dat.system" />
<connection
kind="clock"
version="15.0"
@@ -3832,21 +3403,6 @@
version="15.0"
start="clk_0.clk"
end="reg_bsn_monitor_10GbE.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_tx_10gbe.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_tx_10gbe_hdr_dat.system" />
- <connection
- kind="clock"
- version="15.0"
- start="clk_0.clk"
- end="reg_dp_offload_rx_10gbe_hdr_dat.system" />
<connection
kind="clock"
version="15.0"
@@ -4017,21 +3573,6 @@
version="15.0"
start="clk_0.clk_reset"
end="reg_bsn_monitor_1GbE.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_tx_1gbe.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_rx_1gbe_hdr_dat.system_reset" />
<connection
kind="reset"
version="15.0"
@@ -4102,21 +3643,6 @@
version="15.0"
start="clk_0.clk_reset"
end="reg_bsn_monitor_10GbE.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_tx_10gbe.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_tx_10gbe_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="clk_0.clk_reset"
- end="reg_dp_offload_rx_10gbe_hdr_dat.system_reset" />
<connection
kind="reset"
version="15.0"
@@ -4267,21 +3793,6 @@
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_bsn_monitor_1GbE.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_tx_1gbe.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_tx_1gbe_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_rx_1gbe_hdr_dat.system_reset" />
<connection
kind="reset"
version="15.0"
@@ -4352,21 +3863,6 @@
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_bsn_monitor_10GbE.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_tx_10gbe.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_tx_10gbe_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="15.0"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_rx_10gbe_hdr_dat.system_reset" />
<connection
kind="reset"
version="15.0"
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 606d305ddf..3fbb1540fd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -67,17 +67,17 @@ ENTITY unb2_test_10GbE IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -85,16 +85,16 @@ ENTITY unb2_test_10GbE IS
-- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -146,17 +146,17 @@ BEGIN
BCK_REF_CLK => BCK_REF_CLK,
-- back transceivers
- BCK_RX => BCK_RX,
- BCK_TX => BCK_TX,
+ --BCK_RX => BCK_RX,
+ --BCK_TX => BCK_TX,
BCK_SDA => BCK_SDA,
BCK_SCL => BCK_SCL,
BCK_ERR => BCK_ERR,
-- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
+ --RING_0_RX => RING_0_RX,
+ --RING_0_TX => RING_0_TX,
+ --RING_1_RX => RING_1_RX,
+ --RING_1_TX => RING_1_TX,
-- pmbus
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
@@ -164,16 +164,16 @@ BEGIN
-- front transceivers
QSFP_0_RX => QSFP_0_RX,
QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
+ --QSFP_1_RX => QSFP_1_RX,
+ --QSFP_1_TX => QSFP_1_TX,
+ --QSFP_2_RX => QSFP_2_RX,
+ --QSFP_2_TX => QSFP_2_TX,
+ --QSFP_3_RX => QSFP_3_RX,
+ --QSFP_3_TX => QSFP_3_TX,
+ --QSFP_4_RX => QSFP_4_RX,
+ --QSFP_4_TX => QSFP_4_TX,
+ --QSFP_5_RX => QSFP_5_RX,
+ --QSFP_5_TX => QSFP_5_TX,
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/ddr_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/ddr_stream.vhd
index 6db8ed5adf..93bb8470fb 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/ddr_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/ddr_stream.vhd
@@ -70,7 +70,7 @@ ENTITY ddr_stream IS
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- bsn
- reg_bsn_monitor_mosi : IN t_mem_mosi;
+ reg_bsn_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_monitor_miso : OUT t_mem_miso;
-- databuffer
@@ -82,11 +82,11 @@ ENTITY ddr_stream IS
reg_diag_rx_seq_miso : OUT t_mem_miso;
-- IO DDR register map
- reg_io_ddr_mosi : IN t_mem_mosi;
+ reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose
- ram_ss_ss_transp_mosi : IN t_mem_mosi;
+ ram_ss_ss_transp_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 75b9c2f3d0..581946496b 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -130,6 +130,13 @@ ENTITY mmm_unb2_test IS
reg_diag_tx_seq_1GbE_mosi : OUT t_mem_mosi;
reg_diag_tx_seq_1GbE_miso : IN t_mem_miso;
+ ram_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ ram_diag_bg_10GbE_miso : IN t_mem_miso;
+ reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_bg_10GbE_miso : IN t_mem_miso;
+ reg_diag_tx_seq_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_tx_seq_10GbE_miso : IN t_mem_miso;
+
ram_diag_bg_ddr_mosi : OUT t_mem_mosi;
ram_diag_bg_ddr_miso : IN t_mem_miso;
reg_diag_bg_ddr_mosi : OUT t_mem_mosi;
@@ -138,35 +145,44 @@ ENTITY mmm_unb2_test IS
reg_diag_tx_seq_ddr_miso : IN t_mem_miso;
-- dp_offload_tx
- reg_dp_offload_tx_1GbE_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_1GbE_miso : IN t_mem_miso;
- reg_dp_offload_tx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_1GbE_hdr_dat_miso : IN t_mem_miso;
+ --reg_dp_offload_tx_1GbE_mosi : OUT t_mem_mosi;
+ --reg_dp_offload_tx_1GbE_miso : IN t_mem_miso;
+ --reg_dp_offload_tx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ --reg_dp_offload_tx_1GbE_hdr_dat_miso : IN t_mem_miso;
-- dp_offload_rx
- reg_dp_offload_rx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
- reg_dp_offload_rx_1GbE_hdr_dat_miso : IN t_mem_miso;
+ --reg_dp_offload_rx_1GbE_hdr_dat_mosi : OUT t_mem_mosi;
+ --reg_dp_offload_rx_1GbE_hdr_dat_miso : IN t_mem_miso;
-- bsn
- reg_bsn_monitor_1GbE_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
- reg_bsn_monitor_ddr_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_ddr_miso : IN t_mem_miso;
+ reg_bsn_monitor_1GbE_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
+ reg_bsn_monitor_10GbE_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_10GbE_miso : IN t_mem_miso;
+ reg_bsn_monitor_ddr_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_ddr_miso : IN t_mem_miso;
-- databuffer
- ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_1GbE_miso : IN t_mem_miso;
- reg_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_1GbE_miso : IN t_mem_miso;
- reg_diag_rx_seq_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_rx_seq_1GbE_miso : IN t_mem_miso;
-
- ram_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_ddr_miso : IN t_mem_miso;
- reg_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_ddr_miso : IN t_mem_miso;
- reg_diag_rx_seq_ddr_mosi : OUT t_mem_mosi;
- reg_diag_rx_seq_ddr_miso : IN t_mem_miso;
+ ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_1GbE_miso : IN t_mem_miso;
+ reg_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_1GbE_miso : IN t_mem_miso;
+ reg_diag_rx_seq_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_rx_seq_1GbE_miso : IN t_mem_miso;
+
+ ram_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_10GbE_miso : IN t_mem_miso;
+ reg_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_10GbE_miso : IN t_mem_miso;
+ reg_diag_rx_seq_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_rx_seq_10GbE_miso : IN t_mem_miso;
+
+ ram_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_ddr_miso : IN t_mem_miso;
+ reg_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_ddr_miso : IN t_mem_miso;
+ reg_diag_rx_seq_ddr_mosi : OUT t_mem_mosi;
+ reg_diag_rx_seq_ddr_miso : IN t_mem_miso;
-- 10GbE
reg_tr_10GbE_qsfp_ring_mosi : OUT t_mem_mosi;
@@ -184,26 +200,30 @@ ENTITY mmm_unb2_test IS
);
END mmm_unb2_test;
+
ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+ CONSTANT g_nof_streams_10GbE : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1;
+
-- Block generator
- CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
- CONSTANT c_ram_diag_bg_ddr_addr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_bg_ddr_addr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
-
- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
-
- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+-- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+-- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+--
+-- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+-- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+-- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+--
+-- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+-- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+-- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- reorder
-- v--- FIXME: g_frame_size_in
@@ -216,8 +236,9 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_reg_tr_10GbE_back1_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_tr_10GbE_adr_w));
-- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
- CONSTANT c_reg_rsp_bsn_monitor_ddr_adr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_ddr_adr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-- Simulation
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
@@ -259,62 +280,78 @@ BEGIN
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_tx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
- u_mm_file_reg_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_ddr_mosi, reg_diag_bg_ddr_miso);
- u_mm_file_ram_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DDR")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_ddr_mosi, ram_diag_bg_ddr_miso);
+ u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ u_mm_file_reg_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_ddr_mosi, reg_diag_bg_ddr_miso);
+ u_mm_file_ram_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DDR")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_ddr_mosi, ram_diag_bg_ddr_miso);
u_mm_file_reg_diag_tx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_mosi, reg_diag_tx_seq_ddr_miso);
- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
-
- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_DDR")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_ddr_mosi, reg_bsn_monitor_ddr_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_mosi, reg_diag_data_buf_ddr_miso);
- u_mm_file_ram_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_mosi, ram_diag_data_buf_ddr_miso);
- u_mm_file_reg_diag_rx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_mosi, reg_diag_rx_seq_ddr_miso);
+-- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+-- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+--
+-- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+-- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+--
+-- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+-- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+ u_mm_file_reg_bsn_monitor_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_ddr_mosi, reg_bsn_monitor_ddr_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_mosi, reg_diag_data_buf_ddr_miso);
+ u_mm_file_ram_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_mosi, ram_diag_data_buf_ddr_miso);
+ u_mm_file_reg_diag_rx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_mosi, reg_diag_rx_seq_ddr_miso);
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
@@ -329,12 +366,12 @@ BEGIN
u_mm_file_reg_eth1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+ u_mm_file_reg_tr_10GbE_back0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+ u_mm_file_reg_tr_10GbE_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -544,32 +581,32 @@ BEGIN
reg_tr_10gbe_back1_readdata_export => reg_tr_10GbE_back1_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_back1_waitrequest_export => reg_tr_10GbE_back1_miso.waitrequest,
- -- the_reg_dp_offload_tx_1GbE
- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_1GbE_clk_export => OPEN,
- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_1GbE_reset_export => OPEN,
- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_1GbE_hdr_dat
- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_rx_1GbE_hdr_dat
- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+-- -- the_reg_dp_offload_tx_1GbE
+-- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+-- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+-- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+-- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+-- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+--
+-- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+-- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+-- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+-- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+-- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+-- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+-- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+--
+-- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+-- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+-- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+-- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+-- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+-- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+-- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+-- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
@@ -580,6 +617,14 @@ BEGIN
reg_bsn_monitor_1gbe_read_export => reg_bsn_monitor_1GbE_mosi.rd,
reg_bsn_monitor_1gbe_readdata_export => reg_bsn_monitor_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_10gbe_reset_export => OPEN,
+ reg_bsn_monitor_10gbe_clk_export => OPEN,
+ reg_bsn_monitor_10gbe_address_export => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w-1 DOWNTO 0),
+ reg_bsn_monitor_10gbe_write_export => reg_bsn_monitor_10GbE_mosi.wr,
+ reg_bsn_monitor_10gbe_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_10gbe_read_export => reg_bsn_monitor_10GbE_mosi.rd,
+ reg_bsn_monitor_10gbe_readdata_export => reg_bsn_monitor_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_monitor_ddr_reset_export => OPEN,
reg_bsn_monitor_ddr_clk_export => OPEN,
reg_bsn_monitor_ddr_address_export => reg_bsn_monitor_ddr_mosi.address(c_reg_rsp_bsn_monitor_ddr_adr_w-1 DOWNTO 0),
@@ -596,6 +641,14 @@ BEGIN
reg_diag_data_buffer_1gbe_read_export => reg_diag_data_buf_1gbe_mosi.rd,
reg_diag_data_buffer_1gbe_readdata_export => reg_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_10gbe_reset_export => OPEN,
+ reg_diag_data_buffer_10gbe_clk_export => OPEN,
+ reg_diag_data_buffer_10gbe_address_export => reg_diag_data_buf_10gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_10gbe_write_export => reg_diag_data_buf_10gbe_mosi.wr,
+ reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_10gbe_read_export => reg_diag_data_buf_10gbe_mosi.rd,
+ reg_diag_data_buffer_10gbe_readdata_export => reg_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_diag_data_buffer_ddr_reset_export => OPEN,
reg_diag_data_buffer_ddr_clk_export => OPEN,
reg_diag_data_buffer_ddr_address_export => reg_diag_data_buf_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
@@ -612,6 +665,14 @@ BEGIN
ram_diag_data_buffer_1gbe_read_export => ram_diag_data_buf_1gbe_mosi.rd,
ram_diag_data_buffer_1gbe_readdata_export => ram_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10gbe_clk_export => OPEN,
+ ram_diag_data_buffer_10gbe_reset_export => OPEN,
+ ram_diag_data_buffer_10gbe_address_export => ram_diag_data_buf_10gbe_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10gbe_write_export => ram_diag_data_buf_10gbe_mosi.wr,
+ ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_10gbe_read_export => ram_diag_data_buf_10gbe_mosi.rd,
+ ram_diag_data_buffer_10gbe_readdata_export => ram_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+
ram_diag_data_buffer_ddr_clk_export => OPEN,
ram_diag_data_buffer_ddr_reset_export => OPEN,
ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
@@ -628,6 +689,14 @@ BEGIN
reg_diag_bg_1GbE_read_export => reg_diag_bg_1GbE_mosi.rd,
reg_diag_bg_1GbE_readdata_export => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_reset_export => OPEN,
+ reg_diag_bg_10GbE_clk_export => OPEN,
+ reg_diag_bg_10GbE_address_export => reg_diag_bg_10GbE_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_write_export => reg_diag_bg_10GbE_mosi.wr,
+ reg_diag_bg_10GbE_writedata_export => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_10GbE_read_export => reg_diag_bg_10GbE_mosi.rd,
+ reg_diag_bg_10GbE_readdata_export => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_diag_bg_ddr_reset_export => OPEN,
reg_diag_bg_ddr_clk_export => OPEN,
reg_diag_bg_ddr_address_export => reg_diag_bg_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
@@ -644,6 +713,14 @@ BEGIN
ram_diag_bg_1GbE_read_export => ram_diag_bg_1GbE_mosi.rd,
ram_diag_bg_1GbE_readdata_export => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_reset_export => OPEN,
+ ram_diag_bg_10GbE_clk_export => OPEN,
+ ram_diag_bg_10GbE_address_export => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
+ ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
+ ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+
ram_diag_bg_ddr_reset_export => OPEN,
ram_diag_bg_ddr_clk_export => OPEN,
ram_diag_bg_ddr_address_export => ram_diag_bg_ddr_mosi.address(c_ram_diag_bg_ddr_addr_w-1 DOWNTO 0),
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 858ea33864..8f595b201a 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -28,353 +28,312 @@ PACKAGE qsys_unb2_test_pkg IS
-- this component declaration is copy-pasted from Quartus v15 QSYS builder
-----------------------------------------------------------------------------
+
component qsys_unb2_test is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ddr_clk_export : out std_logic; -- export
- ram_diag_bg_ddr_read_export : out std_logic; -- export
- ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ddr_reset_export : out std_logic; -- export
- ram_diag_bg_ddr_write_export : out std_logic; -- export
- ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
- reg_bsn_monitor_ddr_read_export : out std_logic; -- export
- reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
- reg_bsn_monitor_ddr_write_export : out std_logic; -- export
- reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ddr_clk_export : out std_logic; -- export
- reg_diag_bg_ddr_read_export : out std_logic; -- export
- reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ddr_reset_export : out std_logic; -- export
- reg_diag_bg_ddr_write_export : out std_logic; -- export
- reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_reset_export : out std_logic -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ddr_clk_export : out std_logic; -- export
+ ram_diag_bg_ddr_read_export : out std_logic; -- export
+ ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ddr_reset_export : out std_logic; -- export
+ ram_diag_bg_ddr_write_export : out std_logic; -- export
+ ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_read_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_write_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ddr_clk_export : out std_logic; -- export
+ reg_diag_bg_ddr_read_export : out std_logic; -- export
+ reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ddr_reset_export : out std_logic; -- export
+ reg_diag_bg_ddr_write_export : out std_logic; -- export
+ reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_unb2_test;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index b3c3dfe7fc..dba9f29860 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -67,25 +67,25 @@ ENTITY udp_stream IS
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- dp_offload_tx
- reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_miso : OUT t_mem_miso;
- reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso;
+ --reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ --reg_dp_offload_tx_miso : OUT t_mem_miso;
+ --reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ --reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso;
-- to MAC
dp_offload_tx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
dp_offload_tx_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
-- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_rx_hdr_dat_miso : OUT t_mem_miso;
+ --reg_dp_offload_rx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ --reg_dp_offload_rx_hdr_dat_miso : OUT t_mem_miso;
-- from MAC
dp_offload_rx_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
dp_offload_rx_snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-- bsn
- reg_bsn_monitor_mosi : IN t_mem_mosi;
+ reg_bsn_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_monitor_miso : OUT t_mem_miso;
-- databuffer
@@ -113,7 +113,6 @@ ARCHITECTURE str OF udp_stream IS
TO_UVEC( 0, c_diag_bg_bsn_init_w));
- CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
CONSTANT c_nof_crc_words : NATURAL := 1;
CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size;
CONSTANT c_min_nof_words_per_block : NATURAL := 1;
@@ -148,7 +147,7 @@ BEGIN
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(fifo_block_gen_src_out_arr(i).sync);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(46 DOWNTO 0);
END GENERATE;
@@ -183,7 +182,7 @@ BEGIN
reg_tx_seq_miso => reg_diag_tx_seq_miso
);
- gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE --FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
g_data_w => g_data_w,
@@ -228,10 +227,10 @@ BEGIN
dp_clk => dp_clk,
-- MM
- reg_mosi => reg_dp_offload_tx_mosi,
- reg_miso => reg_dp_offload_tx_miso,
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-- from blockgen-fifo
snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams-1 DOWNTO 0),
@@ -263,8 +262,8 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-- from MAC
snk_in_arr => dp_offload_rx_snk_in_arr,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 0eaf14baa5..1a1fd7b9cc 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -78,17 +78,17 @@ ENTITY unb2_test IS
BCK_REF_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE back lower 24 lines
-- back transceivers
- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ --BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0) := (OTHERS=>'0');
+ --BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
+ --RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ --RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0) := (OTHERS=>'0');
+ --RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -96,16 +96,16 @@ ENTITY unb2_test IS
-- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -137,6 +137,10 @@ ARCHITECTURE str OF unb2_test IS
-- Revision controlled constants
CONSTANT c_use_1GbE : BOOLEAN := g_design_name="unb2_test_1GbE" OR g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb2_test_10GbE" OR g_design_name="unb2_test_all";
+ CONSTANT c_use_10GbE_qsfp : BOOLEAN := c_use_10GbE;
+ CONSTANT c_use_10GbE_ring : BOOLEAN := FALSE;
+ CONSTANT c_use_10GbE_back0 : BOOLEAN := FALSE;
+ CONSTANT c_use_10GbE_back1 : BOOLEAN := FALSE;
CONSTANT c_use_ddr : BOOLEAN := g_design_name="unb2_test_ddr" OR g_design_name="unb2_test_all";
-- ddr
@@ -144,17 +148,29 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_MB_I : NATURAL := sel_a_b(c_use_ddr,1,0); -- 1: use MB_I 0: do not use
CONSTANT c_use_MB_II : NATURAL := 0;
+ CONSTANT c_nof_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
+ CONSTANT c_nof_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
+ CONSTANT c_nof_back0 : NATURAL := c_unb2_board_tr_back.bus_w;
+ CONSTANT c_nof_back1 : NATURAL := c_unb2_board_tr_back.bus_w;
+ -- 1GbE
CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
- CONSTANT c_nof_streams_qsfp : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,0);
- CONSTANT c_nof_streams_ring : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,0);
- CONSTANT c_nof_streams_back0 : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_back.bus_w,0);
- CONSTANT c_nof_streams_back1 : NATURAL := sel_a_b(c_use_10GbE,c_unb2_board_tr_back.bus_w,0);
+
+ -- 10GbE
+ CONSTANT c_nof_streams_qsfp : NATURAL := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
+ CONSTANT c_nof_streams_ring : NATURAL := sel_a_b(c_use_10GbE_ring,c_nof_ring,0);
+ CONSTANT c_nof_streams_back0 : NATURAL := sel_a_b(c_use_10GbE_back0,c_nof_back0,0);
+ CONSTANT c_nof_streams_back1 : NATURAL := sel_a_b(c_use_10GbE_back1,c_nof_back1,0);
+
+ CONSTANT c_nof_streams_10GbE : NATURAL := c_nof_streams_qsfp+c_nof_streams_ring+c_nof_streams_back0+c_nof_streams_back1;
+
+ -- ddr
CONSTANT c_nof_streams_ddr : NATURAL := sel_a_b(c_use_MB_I,sel_a_b(c_use_MB_II,2,1),0);
CONSTANT c_nof_qsfp_bus : NATURAL := ceil_div(c_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
CONSTANT c_nof_ring_bus : NATURAL := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
CONSTANT c_nof_back_bus : NATURAL := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
+
CONSTANT c_data_w_32 : NATURAL := c_eth_data_w; -- 1GbE
CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_1GbE, c_eth_data_w,
@@ -279,6 +295,8 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
+
+
SIGNAL reg_tr_10GbE_qsfp_ring_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_qsfp_ring_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_back0_mosi : t_mem_mosi;
@@ -286,7 +304,6 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_tr_10GbE_back1_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_back1_miso : t_mem_miso;
-
SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
@@ -294,6 +311,13 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_diag_tx_seq_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_tx_seq_1GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_10GbE_miso : t_mem_miso;
+
SIGNAL reg_diag_bg_ddr_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_ddr_miso : t_mem_miso;
SIGNAL ram_diag_bg_ddr_mosi : t_mem_mosi;
@@ -301,16 +325,18 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_diag_tx_seq_ddr_mosi : t_mem_mosi;
SIGNAL reg_diag_tx_seq_ddr_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
-
- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+--
+-- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_ddr_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_ddr_miso : t_mem_miso;
@@ -321,6 +347,13 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_10GbE_miso : t_mem_miso;
+
SIGNAL ram_diag_data_buf_ddr_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_ddr_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_ddr_mosi : t_mem_mosi;
@@ -328,13 +361,15 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_diag_rx_seq_ddr_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_ddr_miso : t_mem_miso;
- SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
-
SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
@@ -559,6 +594,13 @@ BEGIN
reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
+
ram_diag_bg_ddr_mosi => ram_diag_bg_ddr_mosi,
ram_diag_bg_ddr_miso => ram_diag_bg_ddr_miso,
reg_diag_bg_ddr_mosi => reg_diag_bg_ddr_mosi,
@@ -567,18 +609,20 @@ BEGIN
reg_diag_tx_seq_ddr_miso => reg_diag_tx_seq_ddr_miso,
-- dp_offload_tx
- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
-
- -- dp_offload_rx
- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+-- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+-- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+-- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+-- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+--
+-- -- dp_offload_rx
+-- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+-- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
reg_bsn_monitor_ddr_mosi => reg_bsn_monitor_ddr_mosi,
reg_bsn_monitor_ddr_miso => reg_bsn_monitor_ddr_miso,
@@ -590,6 +634,13 @@ BEGIN
reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
ram_diag_data_buf_ddr_mosi => ram_diag_data_buf_ddr_mosi,
ram_diag_data_buf_ddr_miso => ram_diag_data_buf_ddr_miso,
reg_diag_data_buf_ddr_mosi => reg_diag_data_buf_ddr_mosi,
@@ -647,16 +698,16 @@ BEGIN
reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
-- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+-- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+-- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
@@ -689,6 +740,153 @@ BEGIN
END GENERATE;
+ gen_udp_stream_10GbE : IF c_use_10GbE = TRUE GENERATE
+ u_udp_stream_10GbE : ENTITY work.udp_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_32, -- c_data_w_64
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => TRUE -- FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
+
+ u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe -- QSFP and Ring lines
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size*2
+ )
+ PORT MAP (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
+
+ gen_qsfp_wires: FOR i IN 0 TO c_nof_streams_qsfp-1 GENERATE
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
+ END GENERATE;
+
+ gen_qsfp_pins: FOR i IN 0 TO c_nof_qsfp_bus-1 GENERATE
+ i_QSFP_RX(i) <= QSFP_0_RX;
+ QSFP_0_TX <= i_QSFP_TX(i);
+ END GENERATE;
+
+
+ u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ PORT MAP (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0),
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+ gen_no_udp_stream_10GbE : IF c_use_10GbE = FALSE GENERATE
+ u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ PORT MAP (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
+ u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
+ END GENERATE;
+
+
gen_ddr_stream : IF c_use_ddr = TRUE GENERATE
u_ddr_stream : ENTITY work.ddr_stream
@@ -745,31 +943,5 @@ BEGIN
MB_I_OU => MB_I_OU
);
END GENERATE;
-
-
- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
- GENERIC MAP (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
-
- u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
- GENERIC MAP (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- PORT MAP (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
-
END str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index 91efee9238..ffa292a652 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -28,15 +28,14 @@ USE common_lib.common_field_pkg.ALL;
PACKAGE unb2_test_pkg IS
-- dp_offload_tx
- CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
- CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ CONSTANT c_nof_hdr_fields : NATURAL := 3+12+4+2; -- Total header bits = 384 = 6 64b words
+ CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), --FIXME fill this in for non point-to-point use
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
@@ -47,17 +46,12 @@ PACKAGE unb2_test_pkg IS
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),--FIXME fill this in for non point-to-point use
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "001"&"111111111100"&"0011"&"00";
END unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
index bef7e0c350..8d44ced734 100644
--- a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
+++ b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
@@ -20,7 +20,7 @@
#
###############################################################################
-"""Test case for unb2_test
+"""Test case for unb1_test
Usage:
@@ -63,6 +63,7 @@ import pi_bsn_monitor
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_debug_wave
+import pi_io_ddr
from tools import *
from common import *
@@ -94,9 +95,10 @@ def test_BG_to_DB(tc,io,cmd):
if use_pps==True: ppsh = pi_ppsh.PiPpsh(tc, io)
tc.set_section_id('Read - ')
- nof_streams=4
+ instanceName=tc.gpString
+ nof_streams=5
blocksize=0
- Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize)
+ Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize,instanceName=instanceName)
Bg.write_disable()
settings = Bg.read_block_gen_settings()
@@ -104,11 +106,10 @@ def test_BG_to_DB(tc,io,cmd):
gapsize = settings[0][3]
blocksize = pow(2, ceil_log2(samples_per_packet+gapsize))
- Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize)
+ Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize,instanceName=instanceName)
#Bg.write_block_gen_settings(samplesPerPacket=700, blocksPerSync=781250, gapSize=300, memLowAddr=0, memHighAddr=701, BSNInit=42)
- Db = pi_diag_data_buffer.PiDiagDataBuffer(tc,io,nofStreams=nof_streams,ramSizePerStream=blocksize)
- #resetptrn = [0xc1ea1ed1]*blocksize #samples_per_packet + [0]*(blocksize-samples_per_packet)
- resetptrn = [0xa1a2a3a4]*blocksize #samples_per_packet + [0]*(blocksize-samples_per_packet)
+ Db = pi_diag_data_buffer.PiDiagDataBuffer(tc,io,nofStreams=nof_streams,ramSizePerStream=blocksize,instanceName=instanceName)
+ resetptrn = [0xc1ea1ed1]*blocksize #samples_per_packet + [0]*(blocksize-samples_per_packet)
for s in tc.gpNumbers:
Db.overwrite_data_buffer(resetptrn,streamNr=s,vLevel=9)
@@ -123,6 +124,37 @@ def test_BG_to_DB(tc,io,cmd):
Bg.write_enable()
+
+ # enable tx_seq
+# from pi_diag_tx_seq import REGMAP,PiDiagTxSeq
+# REGMAP_tx=REGMAP
+# from pi_diag_rx_seq import REGMAP,PiDiagRxSeq
+# REGMAP_rx=REGMAP
+
+# print 'read PiDiagTxSeq, PiDiagRxSeq before write'
+# on_execute(class_definition=PiDiagTxSeq,regmap=REGMAP_tx) # this reads/shows ALL registers
+# on_execute(class_definition=PiDiagRxSeq,regmap=REGMAP_rx) # this reads/shows ALL registers
+
+# tx_seq = PiDiagTxSeq(tc,io,inst_name='10GBE')
+# tx_seq.write(tc.nodeNrs,inst_nrs=0, registers=[('control', 1)],regmap=REGMAP_tx)
+#
+# rx_seq = PiDiagRxSeq(tc,io,inst_name='10GBE')
+# rx_seq.write(tc.nodeNrs,inst_nrs=0, registers=[('control', 1)],regmap=REGMAP_rx)
+#
+# print 'read PiDiagTxSeq, PiDiagRxSeq after write'
+# on_execute(class_definition=PiDiagTxSeq,regmap=REGMAP_tx) # this reads/shows ALL registers
+# on_execute(class_definition=PiDiagRxSeq,regmap=REGMAP_rx) # this reads/shows ALL registers
+
+
+# return
+
+ if instanceName == 'DDR':
+ ddr = pi_io_ddr.PiIoDdr(tc,io,nof_inst=1)
+ if tc.sim == True:
+ do_until_eq(ddr.read_init_done, ms_retry=1000, val=1, s_timeout=13600) # 110000
+
+
+
bg_ram = []
for s in tc.gpNumbers:
ram = Bg.read_waveform_ram(channelNr=s,vLevel=5)
@@ -134,6 +166,12 @@ def test_BG_to_DB(tc,io,cmd):
rram.append(ram_10G)
bg_ram.append(rram)
+
+ # Poll the databuffer to check if the response is there.
+ # Retry after 3 seconds so we don't issue too many MM reads in case of simulation.
+ do_until_ge(Db.read_nof_words, ms_retry=3000, val=blocksize, s_timeout=3600)
+
+
db_ram = []
for s in tc.gpNumbers:
databuf = Db.read_data_buffer(streamNr=s,vLevel=5)
@@ -174,7 +212,7 @@ def test_BG_to_DB(tc,io,cmd):
def get_BG_blocksize(tc,io):
- nof_streams=4
+ nof_streams=3
blocksize=0
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams,ramSizePerChannel=blocksize)
settings = Bg.read_block_gen_settings()
@@ -185,7 +223,7 @@ def get_BG_blocksize(tc,io):
def write_BG(tc,io,buf):
tc.set_section_id('Write BG - ')
- nof_streams=4
+ nof_streams=3
blocksize=get_BG_blocksize(tc,io)
Bg = pi_diag_block_gen.PiDiagBlockGen(tc,io,nofChannels=nof_streams, ramSizePerChannel=blocksize)
Bg.write_disable()
@@ -254,7 +292,7 @@ def test_tr_10GbE(tc,io,cmd):
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
- nof_streams=4
+ nof_streams=3
from pi_tr_10GbE import REGMAP,PiTr10GbE,ADDR_W
tr10 = PiTr10GbE(tc,io,nof_inst=nof_streams)
@@ -279,6 +317,49 @@ def test_tr_10GbE(tc,io,cmd):
verify_10GbE_status(tc,stat_name,tr10.read_reg(tc.nodeNrs,'REG_TR_10GBE',inst_offs+(REGMAP[stat_name][2][0]),1))
+def test_tx_seq(tc,io,cmd):
+ tc.set_section_id('tx seq - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ from pi_diag_tx_seq import REGMAP,PiDiagTxSeq
+ tx_seq = PiDiagTxSeq(tc,io,inst_name='10GBE')
+ tx_seq.write(tc.nodeNrs,inst_nrs=0, registers=[('control', 1)],regmap=REGMAP)
+
+
+ # instanceName is taken from tc.gpString
+ on_execute(class_definition=PiDiagTxSeq,regmap=REGMAP) # this reads/shows ALL status
+
+
+def test_rx_seq(tc,io,cmd):
+ tc.set_section_id('rx seq - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ from pi_diag_rx_seq import REGMAP,PiDiagRxSeq
+ rx_seq = PiDiagRxSeq(tc,io,inst_name='10GBE')
+ rx_seq.write(tc.nodeNrs,inst_nrs=0, registers=[('control', 1)],regmap=REGMAP)
+
+
+
+ # instanceName is taken from tc.gpString
+ on_execute(class_definition=PiDiagRxSeq,regmap=REGMAP) # this reads/shows ALL status
+
+
+
+
+
+def test_ddr_stat(tc,io,cmd):
+ tc.set_section_id('DDR3 status - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ from pi_io_ddr import REGMAP,PiIoDdr
+ on_execute(class_definition=PiIoDdr,regmap=REGMAP)
+
def test_bsn_mon(tc,io,cmd):
tc.set_section_id('Read BSN monitor status - ')
@@ -484,12 +565,15 @@ Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_RE
Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
Cmd['XAUI'] = (test_tr_xaui, 'using pi_tr_xaui to read xaui status (access REG_TR_XAUI)','(-r for addressing streams)')
Cmd['10GBE'] = (test_tr_10GbE,'using pi_tr_10GbE to read 10GbE status (access REG_TR_10GBE)','(-r for addressing streams)')
+Cmd['DDR'] = (test_ddr_stat,'using pi_io_ddr to read DDR3 status (access REG_IO_DDR)','')
+Cmd['TXSEQ'] = (test_tx_seq, 'using pi_diag_tx_seq','')
+Cmd['RXSEQ'] = (test_rx_seq, 'using pi_diag_rx_seq','')
Cmd['BSN'] = (test_bsn_mon, 'using pi_bsn_monitor to read BSN monitor (access REG_BSN_MONITOR)','')
-Cmd['BGDB'] = (test_BG_to_DB,'using BG (pi_diag_block_gen.py) and DB (pi_diag_data_buffer.py)','(-r for addressing streams, -n1 for use pps)')
-Cmd['BGs00100'] = (write_BG_00100,'set test BG pattern ...000000000010000000000...','(-r for addressing streams)')
-Cmd['BGsff7ff'] = (write_BG_ff7ff,'set test BG pattern ...ffffffffff7ffffffffff...','(-r for addressing streams)')
-Cmd['BGsrand'] = (write_BG_rand, 'set test BG pattern with pseudo random (seed=10)','(-r for addressing streams)')
-Cmd['BGscount'] = (write_BG_count,'set test BG pattern with counter data','(-r for addressing streams)')
+Cmd['BGDB'] = (test_BG_to_DB,'using BG (pi_diag_block_gen.py) and DB (pi_diag_data_buffer.py)','(-r and -s for addressing streams, -n1 for use pps)')
+Cmd['BGs00100'] = (write_BG_00100,'set test BG pattern ...000000000010000000000...','(-r and -s for addressing streams)')
+Cmd['BGsff7ff'] = (write_BG_ff7ff,'set test BG pattern ...ffffffffff7ffffffffff...','(-r and -s for addressing streams)')
+Cmd['BGsrand'] = (write_BG_rand, 'set test BG pattern with pseudo random (seed=10)','(-r and -s for addressing streams)')
+Cmd['BGscount'] = (write_BG_count,'set test BG pattern with counter data','(-r and -s for addressing streams)')
Cmd['sleep1'] = (sleep, 'Sleep 1 second','')
Cmd['sleep5'] = (sleep, 'Sleep 5 seconds','')
Cmd['example'] = (show_help, 'show several example commands','')
@@ -506,6 +590,8 @@ def help_text(tc,io,cmd):
tc.append_log(0, ' <nodes>: use: --unb N --fn N --bn N (N is a number or vector) or:')
tc.append_log(0, ' <nodes>: use: --gn N (N is a number or vector)')
tc.append_log(0, ' <command sequence>: use: --seq <command(s) separated by ",">:')
+ tc.append_log(0, ' <streamdevice>: use: -s 10GBE or -s 1GBE to select stream device')
+ tc.append_log(0, ' <streamnumber>: use: -r N to select a stream number (N can also be 0:2)')
tc.append_log(0, '')
for cmd in sorted(Cmd):
tc.append_log(0, ' . %s\t%s %s' % (cmd,Cmd[cmd][1],Cmd[cmd][2]))
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index fb138bea34..aad4be6c1c 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -98,6 +98,8 @@ ARCHITECTURE tb OF tb_unb2_test IS
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL qsfp_led : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
-- 10GbE
SIGNAL sa_clk : STD_LOGIC := '1';
SIGNAL sb_clk : STD_LOGIC := '1';
@@ -179,8 +181,8 @@ BEGIN
INTA => INTA,
INTB => INTB,
- sens_sc => sens_scl,
- sens_sd => sens_sda,
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
-- Others
VERSION => VERSION,
@@ -188,7 +190,7 @@ BEGIN
TESTIO => TESTIO,
-- 1GbE Control Interface
- ETH_clk => eth_clk,
+ ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
@@ -202,24 +204,26 @@ BEGIN
-- Serial I/O
QSFP_0_TX => si_lpbk_0,
QSFP_0_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_1,
- QSFP_1_RX => si_lpbk_1,
- QSFP_2_TX => si_lpbk_2,
- QSFP_2_RX => si_lpbk_2,
- QSFP_3_TX => si_lpbk_3,
- QSFP_3_RX => si_lpbk_3,
- QSFP_4_TX => si_lpbk_4,
- QSFP_4_RX => si_lpbk_4,
- QSFP_5_TX => si_lpbk_5,
- QSFP_5_RX => si_lpbk_5,
-
- RING_0_TX => si_lpbk_6,
- RING_0_RX => si_lpbk_6,
- RING_1_TX => si_lpbk_7,
- RING_1_RX => si_lpbk_7,
-
- BCK_TX => si_lpbk_8,
- BCK_RX => si_lpbk_8
+-- QSFP_1_TX => si_lpbk_1,
+-- QSFP_1_RX => si_lpbk_1,
+-- QSFP_2_TX => si_lpbk_2,
+-- QSFP_2_RX => si_lpbk_2,
+-- QSFP_3_TX => si_lpbk_3,
+-- QSFP_3_RX => si_lpbk_3,
+-- QSFP_4_TX => si_lpbk_4,
+-- QSFP_4_RX => si_lpbk_4,
+-- QSFP_5_TX => si_lpbk_5,
+-- QSFP_5_RX => si_lpbk_5,
+--
+-- RING_0_TX => si_lpbk_6,
+-- RING_0_RX => si_lpbk_6,
+-- RING_1_TX => si_lpbk_7,
+-- RING_1_RX => si_lpbk_7,
+--
+-- BCK_TX => si_lpbk_8,
+-- BCK_RX => si_lpbk_8,
+
+ QSFP_LED => qsfp_led
);
------------------------------------------------------------------------------
--
GitLab