From 0915bb14a67dca5bb294b2ca2366318f349bcd20 Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Fri, 4 Mar 2022 11:03:09 +0100
Subject: [PATCH] Ready for review.
---
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 30 ++++----
.../src/vhdl/ddrctrl_address_counter.vhd | 3 +-
.../ddrctrl/src/vhdl/ddrctrl_pack.vhd | 9 +--
.../ddrctrl/src/vhdl/ddrctrl_repack.vhd | 6 +-
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 76 ++++++++-----------
.../tb/vhdl/tb_ddrctrl_address_counter.vhd | 37 ++++-----
.../ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd | 26 +++----
.../ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd | 23 +++---
8 files changed, 94 insertions(+), 116 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 8a75aece94..1eb7a77635 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -45,15 +45,15 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY ddrctrl IS
GENERIC (
g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
- g_nof_streams : NATURAL := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
+ g_nof_streams : NATURAL := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
);
PORT (
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr; -- input data
- out_of : OUT NATURAL; -- amount of overflow this output
+ out_of : OUT NATURAL; -- amount of internal overflow this output
out_mosi : OUT t_mem_ctlr_mosi -- output data
);
END ddrctrl;
@@ -62,7 +62,7 @@ END ddrctrl;
ARCHITECTURE str OF ddrctrl IS
-- constant for readability
- CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w;
+ CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
-- signals for connecting the components
@@ -81,9 +81,8 @@ BEGIN
)
PORT MAP(
- clk => clk,
- in_sosi_arr => in_sosi_arr,
- out_data => data
+ in_sosi_arr => in_sosi_arr, -- input data
+ out_data => data -- output data
);
@@ -95,22 +94,21 @@ BEGIN
)
PORT MAP(
clk => clk,
- in_data => data,
- out_of => out_of,
- out_sosi => sosi
+ in_data => data, -- input data
+ out_of => out_of, -- amount of internal overflow
+ out_sosi => sosi -- output data
);
-- creates address by counting input valids
u_address_counter : ENTITY work.ddrctrl_address_counter
GENERIC MAP(
- g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_sim_model => g_sim_model -- determens if this is a simulation
)
PORT MAP(
- clk => clk,
rst => rst,
- in_sosi => sosi,
- out_mosi => out_mosi
+ in_sosi => sosi, -- input data
+ out_mosi => out_mosi -- output data
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
index 2a46b873dc..f8d6c54ed0 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
@@ -45,7 +45,6 @@ ENTITY ddrctrl_address_counter IS
g_sim_model : BOOLEAN := TRUE -- determens if this is a simulation
);
PORT (
- clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
out_mosi : OUT t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst -- output data
@@ -76,7 +75,7 @@ BEGIN
IF rst = '1' THEN
s_adr <= 0;
ELSIF rising_edge(in_sosi.valid) THEN
- IF (s_adr = c_max_adr) THEN
+ IF s_adr = c_max_adr THEN
s_adr <= 0;
ELSE
s_adr <= s_adr + 1;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
index 2a897961ef..1fde708fef 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
@@ -34,15 +34,14 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY ddrctrl_pack IS
GENERIC (
- g_nof_streams : POSITIVE := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
);
PORT (
- clk : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input data
- out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input data
+ out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
);
END ddrctrl_pack;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
index 7157e0b207..0011b9c691 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
@@ -41,9 +41,9 @@ ENTITY ddrctrl_repack IS
);
PORT (
clk : IN STD_LOGIC;
- in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
- out_of : OUT NATURAL := 0;
- out_sosi : OUT t_dp_sosi := c_dp_sosi_init
+ in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
+ out_of : OUT NATURAL := 0; -- amount of internal overflow this output
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
);
END ddrctrl_repack;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 5bbdd33650..18f86c6629 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_pack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl.vhd
-- Usage:
-- > run -a
@@ -39,7 +39,7 @@ ENTITY tb_ddrctrl IS
g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
- g_sim_lengt : NATURAL := 52
+ g_sim_length : NATURAL := 52
);
END tb_ddrctrl;
@@ -58,16 +58,16 @@ ARCHITECTURE tb OF tb_ddrctrl IS
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
- VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*g_sim_lengt-1 DOWNTO 0);
+ VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0);
BEGIN
- FOR I IN 0 TO g_sim_lengt*g_nof_streams-1 LOOP
+ FOR I IN 0 TO g_sim_length*g_nof_streams-1 LOOP
temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
-- constant for running the test
- CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
+ CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
-- input signals for ddrctrl.vhd
@@ -96,11 +96,6 @@ BEGIN
p_test : PROCESS
BEGIN
- -- initialize input data for ddrctrl.vhd
- fill_in_sosi_arr_1 : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
- END LOOP;
-
-- start the test
tb_end <= '0';
WAIT UNTIL rising_edge(clk);
@@ -109,27 +104,26 @@ BEGIN
test_running <= '1';
-- filling the input data vectors with the corresponding numbers
- WAIT FOR c_clk_period*1;
- make_data : FOR J IN 1 TO g_sim_lengt-1 LOOP
+ make_data : FOR J IN 0 TO g_sim_length-1 LOOP
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
END LOOP;
- in_data_cnt <= in_data_cnt + 1;
WAIT FOR c_clk_period*1;
+ in_data_cnt <= in_data_cnt + 1;
END LOOP;
test_running <= '0';
-- stopping the testbench
- WAIT FOR c_clk_period*4;
+ WAIT FOR c_clk_period*5;
tb_end <= '1';
- ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- Excecuting the reset test.
+ -- excecuting the reset test
p_test_reset : PROCESS
BEGIN
rst <= '0';
- WAIT FOR c_clk_period*g_sim_lengt*3/4;
+ WAIT FOR c_clk_period*(c_adr_size+3);
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
@@ -139,26 +133,6 @@ BEGIN
WAIT FOR c_clk_period*1;
END PROCESS;
- -- verifying if the input vectors are correctly put into the output vector and the amount of overflow is as expected
- p_verify_of_data : PROCESS
-
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
-
- BEGIN
- WAIT UNTIL rising_edge(out_mosi.wr);
- IF test_running = '1' THEN
- IF out_data_cnt > 0 THEN
- IF out_data_cnt mod 2 = 0 THEN
- ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
- END IF;
- ASSERT out_mosi.wrdata(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt)-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
- END IF;
- out_data_cnt := out_data_cnt + 1;
- END IF;
- END PROCESS;
-
-- verifying if the address is correct by keeping trach of the address
p_verify_address : PROCESS
BEGIN
@@ -168,13 +142,32 @@ BEGIN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= lag_due_reset THEN
- ASSERT I-lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ ASSERT I-lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
- ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ ASSERT (I-lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
+ -- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
+ p_verify : PROCESS
+
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
+
+ BEGIN
+ WAIT UNTIL out_mosi.wr = '1' AND test_running = '1';
+ IF out_data_cnt >= 1 THEN
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
+ END IF;
+ ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
+ END IF;
+ out_data_cnt := out_data_cnt+1;
+ END PROCESS;
+
+
-- DUT
u_ddrctrl_pack : ENTITY work.ddrctrl
GENERIC MAP (
@@ -192,8 +185,3 @@ BEGIN
);
END tb;
-
-
-
-
-
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
index 14c4720aa3..0f3e4d414a 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
@@ -35,7 +35,7 @@ ENTITY tb_ddrctrl_address_counter IS
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
- g_sim_lengt : NATURAL := 52 -- determens the lengt of the duration of the test
+ g_sim_length : NATURAL := 52 -- determens the length of the duration of the test
);
END tb_ddrctrl_address_counter;
@@ -54,7 +54,7 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
-- input signals for ddrctrl_address_counter.vhd
SIGNAL clk : STD_LOGIC := '1';
- SIGNAL rst : STD_LOGIC;
+ SIGNAL rst : STD_LOGIC := '0';
SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_init; -- signal which is the input for ddrctrl_address_counter.vhd
-- output signal from ddrctrl_address_counter.vhd
@@ -68,25 +68,25 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
BEGIN
- -- Wiring the input signals to the inputs of the testbench.
- in_sosi.data(c_data_w-1 DOWNTO 0) <= in_data(c_data_w-1 DOWNTO 0);
- in_sosi.valid <= in_data_enable;
+ -- wiring the input signals to the inputs of the testbench
+ in_sosi.data(c_data_w-1 DOWNTO 0) <= in_data(c_data_w-1 DOWNTO 0);
+ in_sosi.valid <= in_data_enable;
- -- Generating clock.
+ -- generating clock
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
- -- Excecuting the test.
+ -- excecuting the test
p_test : PROCESS
BEGIN
- -- Initialize inputs.
+ -- initialize inputs
tb_end <= '0';
in_data <= (OTHERS => '0');
in_data_enable <= '0';
WAIT UNTIL rising_edge(clk);
- -- Changing inputs to start the address counting.
- FOR I IN 0 TO g_sim_lengt-1 LOOP
+ -- changing inputs to start the address counting
+ FOR I IN 0 TO g_sim_length-1 LOOP
in_data_enable <= '1';
in_data <= NOT in_data;
WAIT FOR c_clk_period*1;
@@ -94,13 +94,13 @@ BEGIN
WAIT FOR c_clk_period*2;
END LOOP;
- -- Stopping the test.
+ -- stopping the test
WAIT FOR c_clk_period*4;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- Verifying if the data is correct and if valid is correct.
+ -- verifying if the data is correct and if valid is correct
p_verify_data_valid : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
@@ -110,11 +110,11 @@ BEGIN
END IF;
END PROCESS;
- -- Excecuting the reset test.
+ -- excecuting the reset test
p_test_reset : PROCESS
BEGIN
rst <= '0';
- WAIT FOR c_clk_period*g_sim_lengt*3/4;
+ WAIT FOR c_clk_period*(c_adr_size+3);
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
@@ -140,14 +140,14 @@ BEGIN
END LOOP;
END PROCESS;
- -- DUT.
+
+ -- DUT
u_ddrctrl_address_counter : ENTITY work.ddrctrl_address_counter
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
g_sim_model => g_sim_model
)
PORT MAP (
- clk => clk,
rst => rst,
in_sosi => in_sosi,
@@ -155,8 +155,3 @@ BEGIN
);
END tb;
-
-
-
-
-
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
index 292219045b..6f81b6cb22 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
@@ -35,10 +35,11 @@ USE common_lib.common_pkg.ALL;
ENTITY tb_ddrctrl_pack IS
GENERIC (
- g_nof_streams : POSITIVE := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14; -- data with of input data vectors
+ g_sim_length : NATURAL := 52 -- determens the lengt of the duration of the test
- );
+ );
END tb_ddrctrl_pack;
ARCHITECTURE tb OF tb_ddrctrl_pack IS
@@ -76,27 +77,27 @@ ARCHITECTURE tb OF tb_ddrctrl_pack IS
BEGIN
- -- Generating clock.
+ -- generating clock
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
- -- Excecuting the test.
+ -- excecuting the test
p_test : PROCESS
BEGIN
- -- Start the test.
+ -- starting the test
tb_end <= '0';
WAIT UNTIL rising_edge(clk);
WAIT FOR c_clk_period*2;
- -- The input data vectors get filled with the corresponding number.
+ -- the input data vectors get filled with the corresponding number
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
END LOOP;
- -- The numbers get cycled trough the input vectors.
- change_in_sosi_arr : FOR J IN 0 TO 4 LOOP
+ -- the numbers get cycled trough the input vectors
+ change_in_sosi_arr : FOR J IN 0 TO g_sim_length-1 LOOP
WAIT FOR c_clk_period*1;
in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0) <= in_sosi_arr(g_nof_streams-1).data(g_data_w - 1 DOWNTO 0);
loop_switch_data : FOR I IN 1 TO g_nof_streams-1 LOOP
@@ -104,13 +105,13 @@ BEGIN
END LOOP;
END LOOP;
- -- Stopping the testbench.
+ -- stopping the testbench
WAIT FOR c_clk_period*4;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- Verification by checking if the input vectors equel the corresponding index of the output vector.
+ -- verification by checking if the input vectors equel the corresponding index of the output vector
p_verify : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
@@ -121,14 +122,13 @@ BEGIN
END IF;
END PROCESS;
- -- DUT.
+ -- DUT
u_ddrctrl_pack : ENTITY work.ddrctrl_pack
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
)
PORT MAP (
- clk => clk,
in_sosi_arr => in_sosi_arr,
out_data => out_data
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
index c9542f7ed5..ce51bf4b8e 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
@@ -77,7 +77,6 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
-- singals for running the test
- SIGNAL ctr_of : NATURAL := 0; -- signal which contains the amount of overflow for checking
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
@@ -108,28 +107,28 @@ BEGIN
-- stopping the testbench
WAIT FOR c_clk_period*5;
tb_end <= '1';
- ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-
-- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
p_verify : PROCESS
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
- WAIT UNTIL rising_edge(out_sosi.valid);
- IF test_running = '1' THEN
- IF out_data_cnt mod 2 = 1 THEN
- ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*(out_data_cnt+1);
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
+ WAIT UNTIL out_sosi.valid = '1' AND test_running = '1';
+ IF out_data_cnt >= 1 THEN
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
- ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt+1)-1 DOWNTO c_out_data_w*out_data_cnt) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
- out_data_cnt := out_data_cnt + 1;
+ ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
+ out_data_cnt := out_data_cnt+1;
END PROCESS;
+
-- DUT
u_ddrctrl_repack : ENTITY work.ddrctrl_repack
GENERIC MAP (
--
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