From 087bfe13e1ed0f464990411cf20bc8d329de1d44 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@jive.eu>
Date: Fri, 13 Dec 2019 11:02:17 +0100
Subject: [PATCH] change HDL_BUILD_DIR to RADIOHDL_BUILD_DIR
---
.../ip_arria10_e1sg/jesd204b/hdllib.cfg | 8 +-
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 80 +++++++++----------
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index 5a423a7497..b5076ab14a 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -13,10 +13,10 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 7dc7915412..a73c42c91e 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -27,7 +27,7 @@
--
--
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
@@ -325,21 +325,21 @@ BEGIN
u_ip_arria10_e1sg_jesd204b_rx : ENTITY ip_arria10_e1sg_jesd204b_rx.ip_arria10_e1sg_jesd204b_rx
PORT MAP
(
- jesd204_0_alldev_lane_aligned_export => dev_lane_aligned_arr(i),
- csr_cf_export => OPEN,
- csr_cs_export => OPEN,
- csr_f_export => OPEN,
- csr_hd_export => OPEN,
- csr_k_export => OPEN,
- csr_l_export => OPEN,
- csr_lane_powerdown_export => rx_csr_lane_powerdown_arr(i downto i),
- csr_m_export => OPEN,
- csr_n_export => OPEN,
- csr_np_export => OPEN,
- csr_rx_testmode_export => OPEN,
- csr_s_export => OPEN,
- dev_lane_aligned_export => dev_lane_aligned_arr(i),
- dev_sync_n_export => jesd204b_sync_n_arr(i),
+ alldev_lane_aligned => dev_lane_aligned_arr(i),
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => rx_csr_lane_powerdown_arr(i downto i),
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_rx_testmode => OPEN,
+ csr_s => OPEN,
+ dev_lane_aligned => dev_lane_aligned_arr(i),
+ dev_sync_n => jesd204b_sync_n_arr(i),
jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0),
jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
@@ -347,36 +347,36 @@ BEGIN
jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
- jesd204_rx_avs_clk_clk => mm_clk,
- jesd204_rx_avs_rst_n_reset_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
- jesd204_rx_dlb_data_export => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_data_valid_export => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_disperr_export => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_errdetect_export => (others => '0'), -- debug/loopback testing
- jesd204_rx_dlb_kchar_data_export => (others => '0'), -- debug/loopback testing
- jesd204_rx_frame_error_export => '0', -- jesd204_rx_frame_error.export
- jesd204_rx_int_irq => OPEN, -- Connected to status IO in example design
+ jesd204_rx_avs_clk => mm_clk,
+ jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
+ jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_disperr => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_errdetect => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing
+ jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export
+ jesd204_rx_int => OPEN, -- Connected to status IO in example design
jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
jesd204_rx_link_ready => '1',
- pll_ref_clk_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
- rx_analogreset_rx_analogreset => rx_analogreset_arr(I DOWNTO I),
- rx_cal_busy_rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
- rx_digitalreset_rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
- rx_islockedtodata_rx_is_lockedtodata => rx_islockedtodata_arr(I DOWNTO I),
- rx_serial_data_rx_serial_data => serial_rx_arr(i downto i),
- rxlink_clk_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
- rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
- rxphy_clk_export => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
- sof_export => OPEN,
- somf_export => OPEN,
- sysref_export => jesd204b_sysref
+ pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ rx_islockedtodata => rx_islockedtodata_arr(I DOWNTO I),
+ rx_serial_data => serial_rx_arr(i downto i),
+ rxlink_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
+ rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
+ rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+ sof => OPEN,
+ somf => OPEN,
+ sysref => jesd204b_sysref
);
-----------------------------------------------------------------------------
-- Reset sequencer for each channel
-----------------------------------------------------------------------------
- u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ip_arria10_e1sg_jesd204b_rx_reset_seq_cmp
+ u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ENTITY ip_arria10_e1sg_jesd204b_rx_reset_seq.ip_arria10_e1sg_jesd204b_rx_reset_seq
PORT MAP (
av_address => reset_seq_mosi_arr(i).address(7 downto 0), -- in std_logic_vector(7 downto 0) := (others => '0');
av_readdata => reset_seq_miso_arr(i).rddata(31 downto 0),
@@ -429,7 +429,7 @@ BEGIN
END GENERATE;
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
- u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll_cmp
+ u_ip_arria10_e1sg_jesd204b_rx_corepll : ENTITY ip_arria10_e1sg_jesd204b_rx_core_pll.ip_arria10_e1sg_jesd204b_rx_core_pll
PORT MAP (
locked => core_pll_locked,
outclk_0 => rxlink_clk,
@@ -453,7 +453,7 @@ BEGIN
-- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
-- Clock set to 100MHz (use mm_clk)
- u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12_cmp
+ u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ENTITY ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
PORT MAP (
clock => mm_clk,
reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design
--
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