diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
index 39abbe964ba663e6f5752ef3fc4682300d8333b2..8724e5399fc1676504a270249182076bce2f41b4 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
@@ -6,7 +6,7 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
@@ -150,18 +150,23 @@
internal="eth_tse_0.serdes_control_connection"
type="conduit"
dir="end">
- <port name="sd_loopback" internal="sd_loopback" />
- <port name="powerdown" internal="powerdown" />
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
</interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
<interface
- name="tbi_connection"
- internal="eth_tse_0.tbi_connection"
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
type="conduit"
dir="end">
- <port name="tbi_rx_clk" internal="tbi_rx_clk" />
- <port name="tbi_tx_clk" internal="tbi_tx_clk" />
- <port name="tbi_rx_d" internal="tbi_rx_d" />
- <port name="tbi_tx_d" internal="tbi_tx_d" />
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
</interface>
<module
kind="altera_eth_tse"
@@ -176,7 +181,7 @@
<parameter name="enable_ecc" value="false" />
<parameter name="max_channels" value="1" />
<parameter name="use_misc_ports" value="true" />
- <parameter name="transceiver_type" value="NONE" />
+ <parameter name="transceiver_type" value="LVDS_IO" />
<parameter name="enable_hd_logic" value="false" />
<parameter name="enable_gmii_loopback" value="true" />
<parameter name="enable_sup_addr" value="false" />
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
index eb34f8af832d1258aef70bc97dd72cc8dcac3b58..596f0127adc9ee9f816f078fe3cbcde1101ec505 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
@@ -639,62 +639,66 @@ BEGIN
PORT MAP (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => dp_clk,
- ff_tx_rdy => ff_tx_src_in.ready,
- ff_tx_data => ff_tx_src_out.data,
- ff_tx_wren => ff_tx_src_out.valid,
- ff_tx_sop => ff_tx_src_out.sop,
- ff_tx_eop => ff_tx_src_out.eop,
- ff_tx_mod => ff_tx_src_out.empty,
- ff_tx_err => ff_tx_src_out.err(0),
+ ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
+ ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
+ ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
-- . MAC specific
- ff_tx_crc_fwd => ff_tx_crc_fwd, -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => ff_tx_septy, -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => ff_tx_a_full, -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => ff_tx_a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => ff_tx_uflow, -- when '1' then tx FIFO underflow
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
-- MAC receive interface
-- . Avalon STs
- ff_rx_clk => dp_clk,
- ff_rx_rdy => ff_rx_snk_out.ready,
- ff_rx_data => ff_rx_snk_in.data,
- ff_rx_dval => ff_rx_snk_in.valid,
- ff_rx_sop => ff_rx_snk_in.sop,
- ff_rx_eop => ff_rx_snk_in.eop,
- ff_rx_mod => ff_rx_snk_in.empty,
- rx_err => ff_rx_snk_in.err, -- [5] collision error (can only occur in half duplex mode)
- -- [4] PHY error on GMII
- -- [3] receive frame truncated due to FIFO overflow
- -- [2] CRC-32 error
- -- [1] invalid length
- -- [0] = OR of [1:5]
+ ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
+ ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
+ ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
+ ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
+ ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
+ rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => ff_rx_ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => ff_rx_frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => ff_rx_dsav, -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => ff_rx_a_full, -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => ff_rx_a_empty, -- when '1' sthen rx FIFO goes below almost-empty threshold
+ rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
-- Reset
- reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
- clk => mm_clk,
- address => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2),
- readdata => mm_miso.rddata,
- read => mm_mosi.rd,
- writedata => mm_mosi.wrdata,
- write => mm_mosi.wr,
- waitrequest => mm_miso.waitreq,
+ clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
+ reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
+ reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
-- Status LEDs
- led_an => tse_led_an, -- '1' = autonegation completed
- led_link => tse_led_link, -- '1' = successful link synchronisation
- led_disp_err => OPEN, -- TBI character error
- led_char_err => OPEN, -- TBI disparity errorreceived
+ led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
+ led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
+ led_col => OPEN, -- : out std_logic; -- .col
-- Serial 1.25 Gbps
- ref_clk => eth_clk,
- txp => eth_txp,
- rxp => eth_rxp
+ rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
+ ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ txp => eth_txp, -- : out std_logic -- .txp_0
+ rxp => eth_rxp -- : in std_logic := '0'; -- serial_connection.rxp_0
);
-
+
-- Loopback
eth_rxp <= eth_txp;