diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..6304d41c05de9cd7a6c8fc24952489dac5a9e5b1 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg @@ -0,0 +1,30 @@ +hdl_lib_name = lofar2_unb2b_ring +hdl_library_clause_name = lofar2_unb2b_ring_lib +hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tech_pll tr_10GbE diagnostics diag aduh wpfb tech_jesd204b lofar2_sdp ring +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg +hdl_lib_include_ip = + ip_arria10_e1sg_mac_10g + ip_arria10_e1sg_pll_xgmii_mac_clocks + ip_arria10_e1sg_transceiver_pll_10g + ip_arria10_e1sg_phy_10gbase_r + ip_arria10_e1sg_transceiver_reset_controller_1 + +synth_files = + src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd + src/vhdl/lofar2_unb2b_ring_pkg.vhd + src/vhdl/mmc_lofar2_unb2b_ring.vhd + src/vhdl/lofar2_unb2b_ring.vhd + +test_bench_files = +# tb/vhdl/tb_lofar2_unb2b_ring.vhd + +regression_test_vhdl = + +[modelsim_project_file] +modelsim_copy_files = + +[quartus_project_file] +quartus_copy_files = + quartus . + diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.fpga.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3c8643897a024adfe568c1fad7c31f93031e695c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.fpga.yaml @@ -0,0 +1,60 @@ +schema_name: args +schema_version: 1.0 +schema_type: fpga + +hdl_library_name: lofar2_unb2b_ring +fpga_name: lofar2_unb2b_ring +fpga_description: "FPGA design lofar2_unb2b_ring" + +peripherals: + ############################################################################# + # Factory / minimal (see ctrl_unb2b_board.vhd) + ############################################################################# + - peripheral_name: unb2b_board/system_info + lock_base_address: 0x10000 + mm_port_names: + - ROM_SYSTEM_INFO + - PIO_SYSTEM_INFO + + - peripheral_name: unb2b_board/wdi + mm_port_names: + - REG_WDI + + - peripheral_name: unb2b_board/unb2_fpga_sens + mm_port_names: + - REG_FPGA_TEMP_SENS + - REG_FPGA_VOLTAGE_SENS + + - peripheral_name: unb2b_board/ram_scrap + mm_port_names: + - RAM_SCRAP + + - peripheral_name: eth/eth + mm_port_names: + - AVS_ETH_0_TSE + - AVS_ETH_0_REG + - AVS_ETH_0_RAM + + - peripheral_name: ppsh/ppsh + mm_port_names: + - PIO_PPS + + - peripheral_name: epcs/epcs + mm_port_names: + - REG_EPCS + + - peripheral_name: dp/dpmm + mm_port_names: + - REG_DPMM_CTRL + - REG_DPMM_DATA + + - peripheral_name: dp/mmdp + mm_port_names: + - REG_MMDP_CTRL + - REG_MMDP_DATA + + - peripheral_name: remu/remu + mm_port_names: + - REG_REMU + + diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.sof b/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.sof deleted file mode 100644 index 58eae27678f44541fbf6e656921706cb35e27365..0000000000000000000000000000000000000000 Binary files a/applications/lofar2/designs/lofar2_unb2b_ring/lofar2_unb2b_ring.sof and /dev/null differ diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..9f3b374bc4341d879dcbd61a6bb3e7a6c56c47aa --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_common_mm_0</spirit:library> + <spirit:name>avs_common_mm_0</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">16384</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value 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<spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + 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<connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>14</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_0.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_0.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_0.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_0.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_0.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_0.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_0.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_0.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_0.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_0.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip new file mode 100644 index 0000000000000000000000000000000000000000..c7155e411e87a31691363c096d2991a1516daccb --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_unb2c_minimal_avs_common_mm_1</spirit:library> + <spirit:name>avs_common_mm_1</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">524288</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + 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<spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + 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<spirit:library>qsys_unb2c_minimal_avs_common_mm_1</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">17</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + 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<name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>19</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_1.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_1.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_1.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_1.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_1.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_1.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_1.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_1.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_1.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_1.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..e8af9063c2b2d23477d9a6e990c54c5304097c63 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip @@ -0,0 +1,3746 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_avs_eth_0</spirit:library> + <spirit:name>avs_eth_0</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>interrupt</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ins_interrupt_irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_ring_avs_eth_0.mms_reg</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_irq_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mm</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_mm_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mm_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_mm_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_ram</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_ram_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_reg</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_reg_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mms_tse</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>mms_tse_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">mm</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">mm_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run 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</spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + 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<spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ram_writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_ram_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reg_writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reg_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_waitrequest</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_waitrequest_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>tse_write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_tse_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + 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</interface> + <interface> + <name>irq</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_irq_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mm</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_mm_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + 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<direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>2</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_reg</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_reg_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_tse</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_tse_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_waitrequest</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_waitrequest_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mms_ram</key> + <value> + <connectionPointName>mms_ram</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_ram' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>mms_reg</key> + <value> + <connectionPointName>mms_reg</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_reg' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>mms_tse</key> + <value> + <connectionPointName>mms_tse</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_tse' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="avs_eth_0.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="interrupt" altera:internal="avs_eth_0.interrupt" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="ins_interrupt_irq" altera:internal="ins_interrupt_irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="avs_eth_0.irq" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_irq_export" altera:internal="coe_irq_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mm" altera:internal="avs_eth_0.mm" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_mm_clk" altera:internal="csi_mm_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mm_reset" altera:internal="avs_eth_0.mm_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_mm_reset" altera:internal="csi_mm_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_ram" altera:internal="avs_eth_0.mms_ram" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_ram_address" altera:internal="mms_ram_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_read" altera:internal="mms_ram_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_readdata" altera:internal="mms_ram_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_write" altera:internal="mms_ram_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_ram_writedata" altera:internal="mms_ram_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_reg" altera:internal="avs_eth_0.mms_reg" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_reg_address" altera:internal="mms_reg_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_read" altera:internal="mms_reg_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_readdata" altera:internal="mms_reg_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_write" altera:internal="mms_reg_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_reg_writedata" altera:internal="mms_reg_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mms_tse" altera:internal="avs_eth_0.mms_tse" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="mms_tse_address" altera:internal="mms_tse_address"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_read" altera:internal="mms_tse_read"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_readdata" altera:internal="mms_tse_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_waitrequest" altera:internal="mms_tse_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_write" altera:internal="mms_tse_write"></altera:port_mapping> + <altera:port_mapping altera:name="mms_tse_writedata" altera:internal="mms_tse_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_address" altera:internal="avs_eth_0.ram_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_address_export" altera:internal="coe_ram_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_read" altera:internal="avs_eth_0.ram_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_read_export" altera:internal="coe_ram_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_readdata" altera:internal="avs_eth_0.ram_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_readdata_export" altera:internal="coe_ram_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_write" altera:internal="avs_eth_0.ram_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_write_export" altera:internal="coe_ram_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="ram_writedata" altera:internal="avs_eth_0.ram_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_ram_writedata_export" altera:internal="coe_ram_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_address" altera:internal="avs_eth_0.reg_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_address_export" altera:internal="coe_reg_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_read" altera:internal="avs_eth_0.reg_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_read_export" altera:internal="coe_reg_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_readdata" altera:internal="avs_eth_0.reg_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_readdata_export" altera:internal="coe_reg_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_write" altera:internal="avs_eth_0.reg_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_write_export" altera:internal="coe_reg_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reg_writedata" altera:internal="avs_eth_0.reg_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reg_writedata_export" altera:internal="coe_reg_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="avs_eth_0.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_address" altera:internal="avs_eth_0.tse_address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_address_export" altera:internal="coe_tse_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_read" altera:internal="avs_eth_0.tse_read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_read_export" altera:internal="coe_tse_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_readdata" altera:internal="avs_eth_0.tse_readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_readdata_export" altera:internal="coe_tse_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="avs_eth_0.tse_waitrequest" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_waitrequest_export" altera:internal="coe_tse_waitrequest_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_write" altera:internal="avs_eth_0.tse_write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_write_export" altera:internal="coe_tse_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="tse_writedata" altera:internal="avs_eth_0.tse_writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_tse_writedata_export" altera:internal="coe_tse_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>true</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..5ec42fbacf5bd7086b4df15873d692fe7662fb8b --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip @@ -0,0 +1,506 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Altera Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_clk_0</spirit:library> + <spirit:name>clk_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk_out</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedDirectClock</spirit:name> + <spirit:displayName>Associated direct clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectClock">clk_in</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRateKnown</spirit:name> + <spirit:displayName>Clock rate known</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="clockRateKnown">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_in</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>in_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>qsys.ui.export_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">clk</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_in_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>qsys.ui.export_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">reset</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n_out</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedDirectReset</spirit:name> + <spirit:displayName>Associated direct reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectReset">clk_in_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedResetSinks</spirit:name> + <spirit:displayName>Associated reset sinks</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedResetSinks">clk_in_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>clock_source</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>in_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>clk_out</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n_out</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Altera Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_clk_0</spirit:library> + <spirit:name>clock_source</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockFrequency</spirit:name> + <spirit:displayName>Clock frequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockFrequency">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockFrequencyKnown</spirit:name> + <spirit:displayName>Clock frequency is known</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="clockFrequencyKnown">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>inputClockFrequency</spirit:name> + <spirit:displayName>inputClockFrequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="inputClockFrequency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetSynchronousEdges</spirit:name> + <spirit:displayName>Reset synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetSynchronousEdges">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="clk_0.clk" altera:type="clock" altera:dir="start"> + <altera:port_mapping altera:name="clk_out" altera:internal="clk_out"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_in" altera:internal="clk_0.clk_in" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_in_reset" altera:internal="clk_0.clk_in_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk_reset" altera:internal="clk_0.clk_reset" altera:type="reset" altera:dir="start"> + <altera:port_mapping altera:name="reset_n_out" altera:internal="reset_n_out"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..21089dce5a11b69ebc9405e6b4e416c197f19b6a --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip @@ -0,0 +1,3605 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_cpu_0</spirit:library> + <spirit:name>qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>custom_instruction_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="nios_custom_instruction" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readra</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>dummy_ci_port</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>CIName</spirit:name> + <spirit:displayName>CIName</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="CIName"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressWidth</spirit:name> + <spirit:displayName>addressWidth</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressWidth">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockCycle</spirit:name> + <spirit:displayName>Clock cycles</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="clockCycle">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enabled</spirit:name> + <spirit:displayName>enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>maxAddressWidth</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>opcodeExtension</spirit:name> + <spirit:displayName>opcodeExtension</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="opcodeExtension">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>sharedCombinationalAndMulticycle</spirit:name> + <spirit:displayName>sharedCombinationalAndMulticycle</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="sharedCombinationalAndMulticycle">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>data_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>d_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>debugaccess</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>adaptsTo</spirit:name> + <spirit:displayName>Adapts to</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dBSBigEndian</spirit:name> + <spirit:displayName>dBS big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamReads</spirit:name> + <spirit:displayName>Use flow control for read transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamWrites</spirit:name> + <spirit:displayName>Use flow control for write transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isAsynchronous</spirit:name> + <spirit:displayName>Is asynchronous</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Is big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isReadable</spirit:name> + <spirit:displayName>Is readable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isWriteable</spirit:name> + <spirit:displayName>Is writeable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>Maximum address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>debug.providesServices</spirit:name> + <spirit:value spirit:format="string" spirit:id="debug.providesServices">master</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>debug_mem_slave</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>debugaccess</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_debugaccess</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_mem_slave_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.hideDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.hideDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>qsys.ui.connect</spirit:name> + <spirit:value spirit:format="string" spirit:id="qsys.ui.connect">instruction_master,data_master</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>debug_reset_request</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>debug_reset_request</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedDirectReset</spirit:name> + <spirit:displayName>Associated direct reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedResetSinks</spirit:name> + <spirit:displayName>Associated reset sinks</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedResetSinks">none</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>instruction_master</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>i_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>adaptsTo</spirit:name> + <spirit:displayName>Adapts to</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dBSBigEndian</spirit:name> + <spirit:displayName>dBS big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamReads</spirit:name> + <spirit:displayName>Use flow control for read transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>doStreamWrites</spirit:name> + <spirit:displayName>Use flow control for write transfers</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isAsynchronous</spirit:name> + <spirit:displayName>Is asynchronous</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Is big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isReadable</spirit:name> + <spirit:displayName>Is readable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isWriteable</spirit:name> + <spirit:displayName>Is writeable</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maxAddressWidth</spirit:name> + <spirit:displayName>Maximum address width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:master></spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_ring_cpu_0.data_master</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqMap</spirit:name> + <spirit:displayName>IRQ Map</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqMap"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">INDIVIDUAL_REQUESTS</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_nios2_gen2</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>dummy_ci_port</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_address</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>17</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_byteenable</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_read</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_readdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_write</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>d_writedata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>8</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_byteenable</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_debugaccess</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_mem_slave_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>debug_reset_request</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_address</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>17</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_read</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_readdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>i_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>irq</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_req</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_cpu_0</spirit:library> + <spirit:name>altera_nios2_gen2</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>tmr_enabled</spirit:name> + <spirit:displayName>Nios II Triple Mode Redundancy</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="tmr_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_disable_tmr_inj</spirit:name> + <spirit:displayName>Disabled TMR Error Injection Port</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_disable_tmr_inj">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_showUnpublishedSettings</spirit:name> + <spirit:displayName>Show Unpublished Settings</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_showUnpublishedSettings">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_showInternalSettings</spirit:name> + <spirit:displayName>Show Internal Verification Settings</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_showInternalSettings">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_preciseIllegalMemAccessException</spirit:name> + <spirit:displayName>Misaligned memory access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_preciseIllegalMemAccessException">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportPCB</spirit:name> + <spirit:displayName>setting_exportPCB</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportPCB">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportdebuginfo</spirit:name> + <spirit:displayName>Export Instruction Execution States</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportdebuginfo">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_clearXBitsLDNonBypass</spirit:name> + <spirit:displayName>Clear X data bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_clearXBitsLDNonBypass">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_bigEndian</spirit:name> + <spirit:displayName>setting_bigEndian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_bigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_export_large_RAMs</spirit:name> + <spirit:displayName>Export Large RAMs</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_export_large_RAMs">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_asic_enabled</spirit:name> + <spirit:displayName>ASIC enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_asic_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>register_file_por</spirit:name> + <spirit:displayName>Register File POR</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="register_file_por">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_asic_synopsys_translate_on_off</spirit:name> + <spirit:displayName>ASIC Synopsys translate</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_asic_synopsys_translate_on_off">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_asic_third_party_synthesis</spirit:name> + <spirit:displayName>ASIC third party synthesis</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_asic_third_party_synthesis">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_asic_add_scan_mode_input</spirit:name> + <spirit:displayName>ASIC add scan mode input</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_asic_add_scan_mode_input">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_oci_version</spirit:name> + <spirit:displayName>Nios II OCI Version</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_oci_version">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_fast_register_read</spirit:name> + <spirit:displayName>Fast Register Read</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_fast_register_read">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportHostDebugPort</spirit:name> + <spirit:displayName>Export Debug Host Slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportHostDebugPort">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_oci_export_jtag_signals</spirit:name> + <spirit:displayName>Export JTAG signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_oci_export_jtag_signals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_avalonDebugPortPresent</spirit:name> + <spirit:displayName>Avalon Debug Port Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_avalonDebugPortPresent">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_alwaysEncrypt</spirit:name> + <spirit:displayName>Always encrypt</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_alwaysEncrypt">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>io_regionbase</spirit:name> + <spirit:displayName>Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="io_regionbase">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>io_regionsize</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="io_regionsize">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_support31bitdcachebypass</spirit:name> + <spirit:displayName>Use most-significant address bit in processor to bypass data cache</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_support31bitdcachebypass">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateTrace</spirit:name> + <spirit:displayName>Generate trace file during RTL simulation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateTrace">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_allow_break_inst</spirit:name> + <spirit:displayName>Allow Break instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_allow_break_inst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateTestEndChecker</spirit:name> + <spirit:displayName>Activate test end checker</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateTestEndChecker">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ecc_sim_test_ports</spirit:name> + <spirit:displayName>Enable ECC simulation test ports</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ecc_sim_test_ports">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_disableocitrace</spirit:name> + <spirit:displayName>Disable comptr generation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_disableocitrace">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_activateMonitors</spirit:name> + <spirit:displayName>Activate monitors</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_activateMonitors">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_HDLSimCachesCleared</spirit:name> + <spirit:displayName>HDL simulation caches cleared</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_HDLSimCachesCleared">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_HBreakTest</spirit:name> + <spirit:displayName>Add HBreak Request port</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_HBreakTest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_breakslaveoveride</spirit:name> + <spirit:displayName>Manually assign break slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_breakslaveoveride">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_useLimit</spirit:name> + <spirit:displayName>Use Limit for region range</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpu_useLimit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_enabled</spirit:name> + <spirit:displayName>Include MPU</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpu_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_enabled</spirit:name> + <spirit:displayName>Include MMU</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mmu_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_autoAssignTlbPtrSz</spirit:name> + <spirit:displayName>Optimize TLB entries base on device family</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mmu_autoAssignTlbPtrSz">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuReset</spirit:name> + <spirit:displayName>Include cpu_resetrequest and cpu_resettaken signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="cpuReset">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetrequest_enabled</spirit:name> + <spirit:displayName>Include reset_req signal for OCI RAM and Multi-Cycle Custom Instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetrequest_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_removeRAMinit</spirit:name> + <spirit:displayName>Remove RAM Initialization</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_removeRAMinit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_tmr_output_disable</spirit:name> + <spirit:displayName>Create a signal to disable TMR outputs</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_tmr_output_disable">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_shadowRegisterSets</spirit:name> + <spirit:displayName>Number of shadow register sets (0-63)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_shadowRegisterSets">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_numOfInstRegion</spirit:name> + <spirit:displayName> Number of instruction regions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_numOfInstRegion">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_numOfDataRegion</spirit:name> + <spirit:displayName> Number of data regions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_numOfDataRegion">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_TLBMissExcOffset</spirit:name> + <spirit:displayName>Fast TLB Miss Exception vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_TLBMissExcOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetOffset</spirit:name> + <spirit:displayName>Reset vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="resetOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>exceptionOffset</spirit:name> + <spirit:displayName>Exception vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="exceptionOffset">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuID</spirit:name> + <spirit:displayName>CPUID control register value</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="cpuID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>breakOffset</spirit:name> + <spirit:displayName>Break vector offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="breakOffset">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>userDefinedSettings</spirit:name> + <spirit:displayName>User Defined Settings</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="userDefinedSettings"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tracefilename</spirit:name> + <spirit:displayName>Trace File Name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tracefilename"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetSlave</spirit:name> + <spirit:displayName>Reset vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetSlave">onchip_memory2_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_TLBMissExcSlave</spirit:name> + <spirit:displayName>Fast TLB Miss Exception vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="mmu_TLBMissExcSlave">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>exceptionSlave</spirit:name> + <spirit:displayName>Exception vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="exceptionSlave">onchip_memory2_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>breakSlave</spirit:name> + <spirit:displayName>Break vector memory</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="breakSlave">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_interruptControllerType</spirit:name> + <spirit:displayName>Interrupt controller</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="setting_interruptControllerType">Internal</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_branchpredictiontype</spirit:name> + <spirit:displayName>Branch prediction type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="setting_branchpredictiontype">Dynamic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_bhtPtrSz</spirit:name> + <spirit:displayName> Number of entries (2-bits wide)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setting_bhtPtrSz">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cpuArchRev</spirit:name> + <spirit:displayName>Architecture Revision</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="cpuArchRev">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>stratix_dspblock_shift_mul</spirit:name> + <spirit:displayName>stratix_dspblock_shift_mul</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="stratix_dspblock_shift_mul">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>shifterType</spirit:name> + <spirit:displayName>shifterType</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="shifterType">medium_le_shift</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>multiplierType</spirit:name> + <spirit:displayName>multiplierType</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="multiplierType">no_mul</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_shift_choice</spirit:name> + <spirit:displayName>Multiply/Shift/Rotate Hardware</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_shift_choice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_32_impl</spirit:name> + <spirit:displayName>Multiply Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_32_impl">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mul_64_impl</spirit:name> + <spirit:displayName>Multiply Extended Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mul_64_impl">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>shift_rot_impl</spirit:name> + <spirit:displayName>Shift/Rotate Implementation</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="shift_rot_impl">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dividerType</spirit:name> + <spirit:displayName>Divide Hardware</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dividerType">no_div</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_minInstRegionSize</spirit:name> + <spirit:displayName> Minimum instruction region size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_minInstRegionSize">12</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpu_minDataRegionSize</spirit:name> + <spirit:displayName> Minimum data region size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mpu_minDataRegionSize">12</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_uitlbNumEntries</spirit:name> + <spirit:displayName> Micro ITLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_uitlbNumEntries">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_udtlbNumEntries</spirit:name> + <spirit:displayName> Micro DTLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_udtlbNumEntries">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_tlbPtrSz</spirit:name> + <spirit:displayName> TLB entries</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_tlbPtrSz">7</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_tlbNumWays</spirit:name> + <spirit:displayName> TLB Set-Associativity</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_tlbNumWays">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_processIDNumBits</spirit:name> + <spirit:displayName> Process ID (PID) bits</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="mmu_processIDNumBits">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>impl</spirit:name> + <spirit:displayName>Nios II Core</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="impl">Tiny</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_size</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="icache_size">4096</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>fa_cache_line</spirit:name> + <spirit:displayName>Number of Cache Lines</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="fa_cache_line">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>fa_cache_linesize</spirit:name> + <spirit:displayName>Line Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="fa_cache_linesize">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_tagramBlockType</spirit:name> + <spirit:displayName>Tag RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_tagramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_ramBlockType</spirit:name> + <spirit:displayName>Data RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_numTCIM</spirit:name> + <spirit:displayName>Number of tightly coupled instruction master ports</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="icache_numTCIM">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>icache_burstType</spirit:name> + <spirit:displayName>Add burstcount signal to instruction_master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="icache_burstType">None</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_bursts</spirit:name> + <spirit:displayName>Add burstcount signal to data_master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_bursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_victim_buf_impl</spirit:name> + <spirit:displayName>Victim buffer implementation</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_victim_buf_impl">ram</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_size</spirit:name> + <spirit:displayName>Size</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dcache_size">2048</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_tagramBlockType</spirit:name> + <spirit:displayName>Tag RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_tagramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_ramBlockType</spirit:name> + <spirit:displayName>Data RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="dcache_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dcache_numTCDM</spirit:name> + <spirit:displayName>Number of tightly coupled data master ports</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dcache_numTCDM">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_exportvectors</spirit:name> + <spirit:displayName>Export Vectors</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_exportvectors">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_usedesignware</spirit:name> + <spirit:displayName>Use Designware Components</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_usedesignware">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ecc_present</spirit:name> + <spirit:displayName>ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ecc_present">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_ic_ecc_present</spirit:name> + <spirit:displayName>Instruction Cache ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_ic_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_rf_ecc_present</spirit:name> + <spirit:displayName>Register File ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_rf_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_mmu_ecc_present</spirit:name> + <spirit:displayName>MMU ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_mmu_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_dc_ecc_present</spirit:name> + <spirit:displayName>Data Cache ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_dc_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_itcm_ecc_present</spirit:name> + <spirit:displayName>Instruction TCM ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_itcm_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setting_dtcm_ecc_present</spirit:name> + <spirit:displayName>Data TCM ECC Present</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="setting_dtcm_ecc_present">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>regfile_ramBlockType</spirit:name> + <spirit:displayName>RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="regfile_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ocimem_ramBlockType</spirit:name> + <spirit:displayName>RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ocimem_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ocimem_ramInit</spirit:name> + <spirit:displayName>Initialized OCI RAM</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ocimem_ramInit">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mmu_ramBlockType</spirit:name> + <spirit:displayName> MMU RAM block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="mmu_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bht_ramBlockType</spirit:name> + <spirit:displayName>BHT RAM Block Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bht_ramBlockType">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>cdx_enabled</spirit:name> + <spirit:displayName>CDX (Code Density eXtension) Instructions</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="cdx_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mpx_enabled</spirit:name> + <spirit:displayName>mpx_enabled</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="mpx_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_enabled</spirit:name> + <spirit:displayName>Include JTAG Debug</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_triggerArming</spirit:name> + <spirit:displayName>Trigger Arming</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_triggerArming">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_debugReqSignals</spirit:name> + <spirit:displayName>Include debugreq and debugack Signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_debugReqSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_assignJtagInstanceID</spirit:name> + <spirit:displayName>Assign JTAG Instance ID for debug core manually</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="debug_assignJtagInstanceID">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_jtagInstanceID</spirit:name> + <spirit:displayName>JTAG Instance ID value</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_jtagInstanceID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_OCIOnchipTrace</spirit:name> + <spirit:displayName>Onchip Trace Frame Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_OCIOnchipTrace">_128</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_hwbreakpoint</spirit:name> + <spirit:displayName>Hardware Breakpoints</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_hwbreakpoint">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_datatrigger</spirit:name> + <spirit:displayName>Data Triggers</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="debug_datatrigger">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_traceType</spirit:name> + <spirit:displayName>Trace Types</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_traceType">none</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>debug_traceStorage</spirit:name> + <spirit:displayName>Trace Storage</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="debug_traceStorage">onchip_trace</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>master_addr_map</spirit:name> + <spirit:displayName>Manually Set Master Base Address and Size</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="master_addr_map">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instruction_master_paddr_base</spirit:name> + <spirit:displayName>Instruction Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="instruction_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instruction_master_paddr_size</spirit:name> + <spirit:displayName>Instruction Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="instruction_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>flash_instruction_master_paddr_base</spirit:name> + <spirit:displayName>Flash Instruction Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="flash_instruction_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>flash_instruction_master_paddr_size</spirit:name> + <spirit:displayName>Flash Instruction Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="flash_instruction_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>data_master_paddr_base</spirit:name> + <spirit:displayName>Data Master Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="data_master_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>data_master_paddr_size</spirit:name> + <spirit:displayName>Data Master Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="data_master_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_0_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 0 Base Address</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_0_paddr_base">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_0_paddr_size</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 0 Size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_0_paddr_size">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>tightly_coupled_instruction_master_1_paddr_base</spirit:name> + <spirit:displayName>Tightly coupled Instruction Master 1 Base Address</spirit:displayName> + <spirit:value spirit:format="long" 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HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_DEVICE</spirit:name> + <spirit:displayName>Auto DEVICE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_DEVICE_SPEEDGRADE</spirit:name> + <spirit:displayName>Auto DEVICE_SPEEDGRADE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE_SPEEDGRADE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_CLK_CLOCK_DOMAIN</spirit:name> + <spirit:displayName>Auto CLOCK_DOMAIN</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="AUTO_CLK_CLOCK_DOMAIN">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_CLK_RESET_DOMAIN</spirit:name> + <spirit:displayName>Auto RESET_DOMAIN</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="AUTO_CLK_RESET_DOMAIN">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>debug.hostConnection</spirit:name> + <spirit:value spirit:format="string" spirit:id="debug.hostConnection">type jtag id 70:34|110:135</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIG_ENDIAN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIG_ENDIAN">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_FREQ</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_FREQ">100000000u</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_ID_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ID_SIZE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_ID_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ID_VALUE">0x00000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CPU_IMPLEMENTATION</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_IMPLEMENTATION">"tiny"</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">18</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_LINE_SIZE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DCACHE_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_SIZE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.EXCEPTION_ADDR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.EXCEPTION_ADDR">0x00020020</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLASH_ACCELERATOR_LINES">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLUSHDA_SUPPORTED"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_MULX_PRESENT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_DEBUG_CORE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_DEBUG_CORE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_DEBUG_STUB</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_DEBUG_STUB"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</spirit:name> + <spirit:value spirit:format="string" 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<connectionPointName>custom_instruction_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CUSTOM_INSTRUCTION_SLAVES</key> + <value></value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>data_master</key> + <value> + <connectionPointName>data_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>debug_mem_slave</key> + <value> + <connectionPointName>debug_mem_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>instruction_master</key> + <value> + <connectionPointName>instruction_master</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>irq</key> + <value> + <connectionPointName>irq</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>INTERRUPTS_USED</key> + <value>7</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="custom_instruction_master" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.custom_instruction_master" altera:type="nios_custom_instruction" altera:dir="start"> + <altera:port_mapping altera:name="dummy_ci_port" altera:internal="dummy_ci_port"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="data_master" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.data_master" altera:type="avalon" altera:dir="start"> + <altera:port_mapping altera:name="d_address" altera:internal="d_address"></altera:port_mapping> + <altera:port_mapping altera:name="d_byteenable" altera:internal="d_byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="d_read" altera:internal="d_read"></altera:port_mapping> + <altera:port_mapping altera:name="d_readdata" altera:internal="d_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="d_waitrequest" altera:internal="d_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="d_write" altera:internal="d_write"></altera:port_mapping> + <altera:port_mapping altera:name="d_writedata" altera:internal="d_writedata"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_debugaccess_to_roms" altera:internal="debug_mem_slave_debugaccess_to_roms"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="debug_mem_slave" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.debug_mem_slave" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="debug_mem_slave_address" altera:internal="debug_mem_slave_address"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_byteenable" altera:internal="debug_mem_slave_byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_debugaccess" altera:internal="debug_mem_slave_debugaccess"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_read" altera:internal="debug_mem_slave_read"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_readdata" altera:internal="debug_mem_slave_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_waitrequest" altera:internal="debug_mem_slave_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_write" altera:internal="debug_mem_slave_write"></altera:port_mapping> + <altera:port_mapping altera:name="debug_mem_slave_writedata" altera:internal="debug_mem_slave_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="debug_reset_request" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.debug_reset_request" altera:type="reset" altera:dir="start"> + <altera:port_mapping altera:name="debug_reset_request" altera:internal="debug_reset_request"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="instruction_master" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.instruction_master" altera:type="avalon" altera:dir="start"> + <altera:port_mapping altera:name="i_address" altera:internal="i_address"></altera:port_mapping> + <altera:port_mapping altera:name="i_read" altera:internal="i_read"></altera:port_mapping> + <altera:port_mapping altera:name="i_readdata" altera:internal="i_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="i_waitrequest" altera:internal="i_waitrequest"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.irq" altera:type="interrupt" altera:dir="start"> + <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_arts_unb2b_xc_emu_nw_10GbE_cpu_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..8f32672aa98281617264b775df5d04fdeb87fedf --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip @@ -0,0 +1,1241 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_jtag_uart_0</spirit:library> + <spirit:name>jtag_uart_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>avalon_jtag_slave</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_read_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_write_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>waitrequest</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_waitrequest</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">NATIVE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>av_irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_ring_jtag_uart_0.avalon_jtag_slave</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged receiver offset</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToReceiver</spirit:name> + <spirit:displayName>Bridges to receiver</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqScheme</spirit:name> + <spirit:displayName>Interrupt scheme</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rst_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_jtag_uart</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rst_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_read_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_write_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_waitrequest</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>av_irq</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_jtag_uart_0</spirit:library> + <spirit:name>altera_avalon_jtag_uart</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>allowMultipleConnections</spirit:name> + <spirit:displayName>Allow multiple connections to Avalon JTAG slave</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="allowMultipleConnections">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hubInstanceID</spirit:name> + <spirit:displayName>hubInstanceID</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="hubInstanceID">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readBufferDepth</spirit:name> + <spirit:displayName>Buffer depth (bytes)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readBufferDepth">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readIRQThreshold</spirit:name> + <spirit:displayName>IRQ threshold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readIRQThreshold">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simInputCharacterStream</spirit:name> + <spirit:displayName>Contents</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simInputCharacterStream"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simInteractiveOptions</spirit:name> + <spirit:displayName>Options</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRegistersForReadBuffer</spirit:name> + <spirit:displayName>Construct using registers instead of memory blocks</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRegistersForReadBuffer">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRegistersForWriteBuffer</spirit:name> + <spirit:displayName>Construct using registers instead of memory blocks</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRegistersForWriteBuffer">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useRelativePathForSimFile</spirit:name> + <spirit:displayName>useRelativePathForSimFile</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useRelativePathForSimFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeBufferDepth</spirit:name> + <spirit:displayName>Buffer depth (bytes)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeBufferDepth">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeIRQThreshold</spirit:name> + <spirit:displayName>IRQ threshold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeIRQThreshold">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clkFreq</spirit:name> + <spirit:displayName>clkFreq</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clkFreq">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>avalonSpec</spirit:name> + <spirit:displayName>avalonSpec</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="avalonSpec">2.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>legacySignalAllow</spirit:name> + <spirit:displayName>legacySignalAllow</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="legacySignalAllow">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableInteractiveInput</spirit:name> + <spirit:displayName>enableInteractiveInput</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableInteractiveInput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableInteractiveOutput</spirit:name> + <spirit:displayName>enableInteractiveOutput</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableInteractiveOutput">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_DEPTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_DEPTH">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_THRESHOLD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_THRESHOLD">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITE_DEPTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITE_DEPTH">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITE_THRESHOLD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITE_THRESHOLD">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.compatible</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,juart-1.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.group</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">serial</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.name</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">juart</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>8</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field><name>rvalid</name> + <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description> + <bitOffset>0xf</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ravail</name> + <description>The number of characters remaining in the read FIFO (after the current read).</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>CONTROL</name> + <displayName>Control</displayName> + <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>re</name> + <description>Interrupt-enable bit for read interrupts.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>we</name> + <description>Interrupt-enable bit for write interrupts</description> + <bitOffset>0x1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>ri</name> + <description>Indicates that the read interrupt is pending.</description> + <bitOffset>0x8</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>wi</name> + <description>Indicates that the write interrupt is pending.</description> + <bitOffset>0x9</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ac</name> + <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description> + <bitOffset>0xa</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>wspace</name> + <description>The number of spaces available in the write FIFO</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>qsys_lofar2_unb2b_ring_jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="avalon_jtag_slave" altera:internal="jtag_uart_0.avalon_jtag_slave" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="av_address" altera:internal="av_address"></altera:port_mapping> + <altera:port_mapping altera:name="av_chipselect" altera:internal="av_chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="av_read_n" altera:internal="av_read_n"></altera:port_mapping> + <altera:port_mapping altera:name="av_readdata" altera:internal="av_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="av_waitrequest" altera:internal="av_waitrequest"></altera:port_mapping> + <altera:port_mapping altera:name="av_write_n" altera:internal="av_write_n"></altera:port_mapping> + <altera:port_mapping altera:name="av_writedata" altera:internal="av_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="jtag_uart_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="jtag_uart_0.irq" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="av_irq" altera:internal="av_irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="jtag_uart_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="rst_n" altera:internal="rst_n"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..c637ea2ac6539871fc635676bf4475f3a7f3ecde --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip @@ -0,0 +1,1220 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_onchip_memory2_0</spirit:library> + <spirit:name>onchip_memory2_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_req</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>s1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clken</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clken</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>byteenable</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + 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+ </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_onchip_memory2</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>14</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>clken</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>byteenable</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_req</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_onchip_memory2_0</spirit:library> + <spirit:name>altera_avalon_onchip_memory2</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>allowInSystemMemoryContentEditor</spirit:name> + <spirit:displayName>Enable In-System Memory Content Editor feature</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="allowInSystemMemoryContentEditor">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>blockType</spirit:name> + <spirit:displayName>Block type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="blockType">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dataWidth</spirit:name> + <spirit:displayName>Slave S1 Data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dataWidth">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dataWidth2</spirit:name> + <spirit:displayName>Slave S2 Data width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="dataWidth2">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>dualPort</spirit:name> + <spirit:displayName>Dual-port access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="dualPort">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enableDiffWidth</spirit:name> + <spirit:displayName>Enable different width for Dual-port access</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enableDiffWidth">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_enableDiffWidth</spirit:name> + <spirit:displayName>derived_enableDiffWidth</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_enableDiffWidth">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>initMemContent</spirit:name> + <spirit:displayName>Initialize memory content</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="initMemContent">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>initializationFileName</spirit:name> + <spirit:displayName>User created initialization file</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="initializationFileName">onchip_memory2_0.hex</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>enPRInitMode</spirit:name> + <spirit:displayName>Enable Partial Reconfiguration Initialization Mode</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="enPRInitMode">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>instanceID</spirit:name> + <spirit:displayName>Instance ID</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="instanceID">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>memorySize</spirit:name> + <spirit:displayName>Total memory size</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="memorySize">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readDuringWriteMode</spirit:name> + <spirit:displayName>Read During Write Mode</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="readDuringWriteMode">DONT_CARE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simAllowMRAMContentsFile</spirit:name> + <spirit:displayName>Allow MRAM contents file for simulation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="simAllowMRAMContentsFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simMemInitOnlyFilename</spirit:name> + <spirit:displayName>Simulation meminit only has filename</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="simMemInitOnlyFilename">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>singleClockOperation</spirit:name> + <spirit:displayName>Single clock operation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="singleClockOperation">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_singleClockOperation</spirit:name> + <spirit:displayName>derived_singleClockOperation</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_singleClockOperation">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave1Latency</spirit:name> + <spirit:displayName>Slave s1 Latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave1Latency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave2Latency</spirit:name> + <spirit:displayName>Slave s2 Latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave2Latency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useNonDefaultInitFile</spirit:name> + <spirit:displayName>Enable non-default initialization file</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useNonDefaultInitFile">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>copyInitFile</spirit:name> + <spirit:displayName> Copy non-default initialization file to generated folder</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="copyInitFile">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>useShallowMemBlocks</spirit:name> + <spirit:displayName>Minimize memory block usage (may impact fmax)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="useShallowMemBlocks">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writable</spirit:name> + <spirit:displayName>Type</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="writable">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ecc_enabled</spirit:name> + <spirit:displayName>Extend the data width to support ECC bits</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="ecc_enabled">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetrequest_enabled</spirit:name> + <spirit:displayName>Reset Request</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetrequest_enabled">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>autoInitializationFileName</spirit:name> + <spirit:displayName>autoInitializationFileName</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="autoInitializationFileName">qsys_lofar2_unb2b_ring_onchip_memory2_0_onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>deviceFamily</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFeatures</spirit:name> + <spirit:displayName>deviceFeatures</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value> + </spirit:parameter> + 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<spirit:parameter> + <spirit:name>derived_gui_ram_block_type</spirit:name> + <spirit:displayName>derived_gui_ram_block_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_gui_ram_block_type">Automatic</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_is_hardcopy</spirit:name> + <spirit:displayName>derived_is_hardcopy</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_is_hardcopy">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_init_file_name</spirit:name> + <spirit:displayName>derived_init_file_name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_init_file_name">onchip_memory2_0.hex</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CONTENTS_INFO</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CONTENTS_INFO">""</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DUAL_PORT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DUAL_PORT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INIT_CONTENTS_FILE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_CONTENTS_FILE">onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INIT_MEM_CONTENT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_MEM_CONTENT">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.INSTANCE_ID</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INSTANCE_ID">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RAM_BLOCK_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RAM_BLOCK_TYPE">AUTO</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.READ_DURING_WRITE_MODE">DONT_CARE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SINGLE_CLOCK_OP</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SINGLE_CLOCK_OP">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SIZE_MULTIPLE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_MULTIPLE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SIZE_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_VALUE">131072</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.WRITABLE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.WRITABLE">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR">SIM_DIR</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.GENERATE_DAT_SYM">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.GENERATE_HEX</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.GENERATE_HEX">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.HAS_BYTE_LANE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.HAS_BYTE_LANE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.HEX_INSTALL_DIR">QPF_DIR</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_FILENAME">onchip_memory2_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>postgeneration.simulation.init_file.param_name</spirit:name> + <spirit:value spirit:format="string" spirit:id="postgeneration.simulation.init_file.param_name">INIT_FILE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>postgeneration.simulation.init_file.type</spirit:name> + <spirit:value spirit:format="string" spirit:id="postgeneration.simulation.init_file.type">MEM_INIT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk1</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset1</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + 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<key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset1</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>17</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk1" altera:internal="onchip_memory2_0.clk1" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset1" altera:internal="onchip_memory2_0.reset1" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping> + <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="onchip_memory2_0.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="byteenable" altera:internal="byteenable"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write" altera:internal="write"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip new file mode 100644 index 0000000000000000000000000000000000000000..ea2df8b2e342aa6c40268c1e942bb691cd1243a5 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_pps</spirit:library> + <spirit:name>pio_pps</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_pps</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="pio_pps.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="pio_pps.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="pio_pps.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="pio_pps.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="pio_pps.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_pps.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="pio_pps.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="pio_pps.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="pio_pps.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="pio_pps.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..7e149ab40d7b4805e7ed6a02df218de7da4d4faa --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_system_info</spirit:library> + <spirit:name>pio_system_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>4</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>4</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_system_info</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + 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<entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + 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+ <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + 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<name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>7</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="pio_system_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="pio_system_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="pio_system_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="pio_system_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="pio_system_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_system_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="pio_system_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="pio_system_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="pio_system_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="pio_system_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip new file mode 100644 index 0000000000000000000000000000000000000000..10ca8ccbfd75d1ca29bb8b35d266b70b278244f1 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip @@ -0,0 +1,1253 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_wdi</spirit:library> + <spirit:name>pio_wdi</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>external_connection</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>out_port</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>reset_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>s1</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>write_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">NATIVE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" 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spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>altera_avalon_pio</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>write_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>out_port</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_pio_wdi</spirit:library> + <spirit:name>altera_avalon_pio</spirit:name> + <spirit:version>18.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>bitClearingEdgeCapReg</spirit:name> + <spirit:displayName>Enable bit-clearing for edge capture register</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="bitClearingEdgeCapReg">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitModifyingOutReg</spirit:name> + <spirit:displayName>Enable individual bit setting/clearing</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="bitModifyingOutReg">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>captureEdge</spirit:name> + <spirit:displayName>Synchronously capture</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="captureEdge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>direction</spirit:name> + <spirit:displayName>Direction</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="direction">Output</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>edgeType</spirit:name> + <spirit:displayName>Edge Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="edgeType">RISING</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generateIRQ</spirit:name> + <spirit:displayName>Generate IRQ</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="generateIRQ">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>irqType</spirit:name> + <spirit:displayName>IRQ Type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="irqType">LEVEL</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetValue</spirit:name> + <spirit:displayName>Output Port Reset Value</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="resetValue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simDoTestBenchWiring</spirit:name> + <spirit:displayName>Hardwire PIO inputs in test bench</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="simDoTestBenchWiring">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>simDrivenValue</spirit:name> + <spirit:displayName>Drive inputs to field.</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="simDrivenValue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>width</spirit:name> + <spirit:displayName>Width (1-32 bits)</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="width">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>clockRate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_tri</spirit:name> + <spirit:displayName>derived_has_tri</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_tri">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_out</spirit:name> + <spirit:displayName>derived_has_out</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_out">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_in</spirit:name> + <spirit:displayName>derived_has_in</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_in">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_do_test_bench_wiring</spirit:name> + <spirit:displayName>derived_do_test_bench_wiring</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_do_test_bench_wiring">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_capture</spirit:name> + <spirit:displayName>derived_capture</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_capture">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_edge_type</spirit:name> + <spirit:displayName>derived_edge_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_edge_type">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_irq_type</spirit:name> + <spirit:displayName>derived_irq_type</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="derived_irq_type">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>derived_has_irq</spirit:name> + <spirit:displayName>derived_has_irq</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="derived_has_irq">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.CAPTURE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CAPTURE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DATA_WIDTH</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_WIDTH">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DO_TEST_BENCH_WIRING">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DRIVEN_SIM_VALUE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.EDGE_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.EDGE_TYPE">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FREQ</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FREQ">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_IN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_IN">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_OUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_OUT">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.HAS_TRI</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_TRI">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.IRQ_TYPE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.IRQ_TYPE">NONE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RESET_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RESET_VALUE">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.compatible</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,pio-1.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.group</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">gpio</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.name</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">pio</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.params.altr,gpio-bank-width</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,gpio-bank-width">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.params.resetvalue</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.resetvalue">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>32</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>DIRECTION</name> + <displayName>Direction</displayName> + <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>direction</name> + <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>IRQ_MASK</name> + <displayName>Interrupt mask</displayName> + <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> + <addressOffset>0x8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>interruptmask</name> + <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>EDGE_CAP</name> + <displayName>Edge capture</displayName> + <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> + <addressOffset>0xc</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>edgecapture</name> + <description>Edge detection for each input port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>SET_BIT</name> + <displayName>Outset</displayName> + <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x10</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outset</name> + <description>Specifies which bit of the output port to set.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + <register> + <name>CLEAR_BITS</name> + <displayName>Outclear</displayName> + <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x14</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outclear</name> + <description>Specifies which output bit to clear.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="pio_wdi.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="external_connection" altera:internal="pio_wdi.external_connection" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="out_port" altera:internal="out_port"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="pio_wdi.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="pio_wdi.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write_n" altera:internal="write_n"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip new file mode 100644 index 0000000000000000000000000000000000000000..3584b2b2084b0e8b3de58a8e8ab34b0d69093121 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_ram_diag_bg</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_ram_diag_bg</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally 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<spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + 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<consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_ram_diag_bg.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip new file mode 100644 index 0000000000000000000000000000000000000000..976933227447f52628561cd836ad23d86db5013b --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_ram_scrap</spirit:library> + <spirit:name>qsys_lofar2_unb2b_filterbank_ram_scrap</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + 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</parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_scrap.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip new file mode 100644 index 0000000000000000000000000000000000000000..09388c20125191dbe9cffded649c0d3102382db2 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + 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<isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip new file mode 100644 index 0000000000000000000000000000000000000000..b37475205f99f0a7059e2f102eec7c535389c11e --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> 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+ <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip new file mode 100644 index 0000000000000000000000000000000000000000..f8554bf0a6ab0f5015d957c00bb908a9015a5e5e --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_diag_bg</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_diag_bg</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_diag_bg</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + 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spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_diag_bg.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip new file mode 100644 index 0000000000000000000000000000000000000000..0e0f7697225481ed5942bd7a659a48682265fa26 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip new file mode 100644 index 0000000000000000000000000000000000000000..951b7e9303520b56bb6831146679ce46a90b5844 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>6</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>6</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">7</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>512</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + 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<key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip new file mode 100644 index 0000000000000000000000000000000000000000..76151c053edc6f61b82ecb2d7fd2f4d53c3f77dd --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated 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spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" 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<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + 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</spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + 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<spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + 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<width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip new file mode 100644 index 0000000000000000000000000000000000000000..b5a1f35d48e598ab5a848bc68a400b71b7d692df --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + 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<connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip new file mode 100644 index 0000000000000000000000000000000000000000..ec38c192726e2d6c17d74361ed989a42d20bcf27 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</spirit:library> + <spirit:name>reg_dpmm_ctrl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value 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<spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + 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<name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_dpmm_ctrl.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_dpmm_ctrl.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_dpmm_ctrl.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_dpmm_ctrl.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_dpmm_ctrl.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_dpmm_ctrl.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_dpmm_ctrl.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_dpmm_ctrl.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_dpmm_ctrl.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_dpmm_ctrl.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip new file mode 100644 index 0000000000000000000000000000000000000000..0f5e054f33c628f9b08692591e6c8b19c4c28a3e --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_dpmm_data</spirit:library> + <spirit:name>reg_dpmm_data</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address 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spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming 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spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" 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<spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + 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<value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_dpmm_data.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_dpmm_data.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_dpmm_data.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_dpmm_data.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_dpmm_data.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_dpmm_data.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_dpmm_data.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_dpmm_data.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_dpmm_data.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_dpmm_data.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip new file mode 100644 index 0000000000000000000000000000000000000000..dbf526b3079f12e4f3e33c5f966d47c700ccc109 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_epcs</spirit:library> + <spirit:name>reg_epcs</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + 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+ <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> 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<spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + 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<spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + 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<spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + 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<value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_epcs.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_epcs.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_epcs.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_epcs.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_epcs.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_epcs.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_epcs.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_epcs.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_epcs.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_epcs.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..22a40db87ffc00e8b1624aea287af552bd00b2df --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</spirit:library> + <spirit:name>reg_fpga_temp_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + 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<spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + 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<value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_fpga_temp_sens.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_fpga_temp_sens.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_fpga_temp_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_fpga_temp_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_fpga_temp_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_fpga_temp_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_fpga_temp_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_fpga_temp_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_fpga_temp_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_fpga_temp_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..78a692fb5c1f6186e1ae9689f9b5bf3a45df99d7 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</spirit:library> + <spirit:name>reg_fpga_voltage_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" 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<spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" 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<spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>3</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + 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<spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + 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</parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + 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altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_fpga_voltage_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_fpga_voltage_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_fpga_voltage_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_fpga_voltage_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_fpga_voltage_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_fpga_voltage_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_fpga_voltage_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_fpga_voltage_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip new file mode 100644 index 0000000000000000000000000000000000000000..acd9bf189c07f591a1f9ed44ec739e49ecca6198 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</spirit:library> + <spirit:name>reg_mmdp_ctrl</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_ctrl.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_ctrl.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_ctrl.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_ctrl.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_ctrl.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_ctrl.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_ctrl.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_ctrl.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_ctrl.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_ctrl.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip new file mode 100644 index 0000000000000000000000000000000000000000..22acc9f986411e53b4086152350ea3f00ba39f7f --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_mmdp_data</spirit:library> + <spirit:name>reg_mmdp_data</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_mmdp_data</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_data.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_data.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_data.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_data.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_data.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_data.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_data.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_data.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_data.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_data.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip new file mode 100644 index 0000000000000000000000000000000000000000..8e7a6861e728589e2edefa95d96eca32c9c9a711 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_remu</spirit:library> + <spirit:name>reg_remu</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + 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spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + 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<spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + 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<spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_remu</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_remu + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_remu.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_remu.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_remu.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_remu.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_remu.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_remu.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_remu.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_remu.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_remu.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_remu.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..370f47809f2fe4c36b36b451795212e6bebfeb1c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_ring_info</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_ring_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>1</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_ring_info</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..b35f5f1a9bd94661800a218bd26e7192c361ec75 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_ring_lane_info</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_ring_lane_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + 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<parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_ring_lane_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip new file mode 100644 index 0000000000000000000000000000000000000000..74b0536c4f69a68cc1921a0031e232b0c2db7ac4 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip @@ -0,0 +1,1439 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read 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spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + 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<role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip new file mode 100644 index 0000000000000000000000000000000000000000..9f45a30b82feb98b8c909797894d083ff46bb121 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</spirit:library> + <spirit:name>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> 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<value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip new file mode 100644 index 0000000000000000000000000000000000000000..0c062bd66b6127a8292603f8298025c9ba43a1bc --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_unb_pmbus</spirit:library> + <spirit:name>reg_unb_pmbus</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_unb_pmbus</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_unb_pmbus + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" 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</entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + 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</parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_unb_pmbus.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_unb_pmbus.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_unb_pmbus.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_unb_pmbus.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_unb_pmbus.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_unb_pmbus.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_unb_pmbus.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_unb_pmbus.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_unb_pmbus.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_unb_pmbus.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip new file mode 100644 index 0000000000000000000000000000000000000000..82e6df77bfd92fc7a7ccfebbeaa95d8d3ddb5f78 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_unb_sens</spirit:library> + <spirit:name>reg_unb_sens</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>5</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_unb_sens</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_unb_sens + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_unb_sens.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_unb_sens.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_unb_sens.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_unb_sens.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_unb_sens.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_unb_sens.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_unb_sens.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_unb_sens.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_unb_sens.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_unb_sens.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip new file mode 100644 index 0000000000000000000000000000000000000000..864b5eda07034998ebbd6ae08f0e788e7352d9cc --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip @@ -0,0 +1,1447 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_wdi</spirit:library> + <spirit:name>reg_wdi</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_reg_wdi</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element reg_wdi + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="reg_wdi.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="reg_wdi.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="reg_wdi.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="reg_wdi.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="reg_wdi.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="reg_wdi.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="reg_wdi.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="reg_wdi.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="reg_wdi.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="reg_wdi.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip new file mode 100644 index 0000000000000000000000000000000000000000..b49fe3a1002ee208bd681ffe4499499d871d7fc8 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip @@ -0,0 +1,1455 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_rom_system_info</spirit:library> + <spirit:name>rom_system_info</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>address</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_address_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_clk_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>mem</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>address</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_write</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>read</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_read</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>avs_mem_readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + <spirit:displayName>Always burst maximum burst</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bitsPerSymbol</spirit:name> + <spirit:displayName>Bits per symbol</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedAddressOffset</spirit:name> + <spirit:displayName>Bridged Address Offset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgesToMaster</spirit:name> + <spirit:displayName>Bridges to master</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstOnBurstBoundariesOnly</spirit:name> + <spirit:displayName>Burst on burst boundaries only</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>burstcountUnits</spirit:name> + <spirit:displayName>Burstcount units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>constantBurstBehavior</spirit:name> + <spirit:displayName>Constant burst behavior</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>explicitAddressSpan</spirit:name> + <spirit:displayName>Explicit address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>holdTime</spirit:name> + <spirit:displayName>Hold</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>interleaveBursts</spirit:name> + <spirit:displayName>Interleave bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isBigEndian</spirit:name> + <spirit:displayName>Big endian</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isFlash</spirit:name> + <spirit:displayName>Flash memory</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isMemoryDevice</spirit:name> + <spirit:displayName>Memory device</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>isNonVolatileStorage</spirit:name> + <spirit:displayName>Non-volatile storage</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>linewrapBursts</spirit:name> + <spirit:displayName>Linewrap bursts</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumUninterruptedRunLength</spirit:name> + <spirit:displayName>Minimum uninterrupted run length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>printableDevice</spirit:name> + <spirit:displayName>Can receive stdout/stderr</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readLatency</spirit:name> + <spirit:displayName>Read latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitStates</spirit:name> + <spirit:displayName>Read wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>readWaitTime</spirit:name> + <spirit:displayName>Read wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerIncomingSignals</spirit:name> + <spirit:displayName>Register incoming signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>registerOutgoingSignals</spirit:name> + <spirit:displayName>Register outgoing signals</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>setupTime</spirit:name> + <spirit:displayName>Setup</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timingUnits</spirit:name> + <spirit:displayName>Timing units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>transparentBridge</spirit:name> + <spirit:displayName>Transparent bridge</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>waitrequestAllowance</spirit:name> + <spirit:displayName>Waitrequest allowance</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>wellBehavedWaitrequest</spirit:name> + <spirit:displayName>Well-behaved waitrequest</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeLatency</spirit:name> + <spirit:displayName>Write latency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitStates</spirit:name> + <spirit:displayName>Write wait states</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>writeWaitTime</spirit:name> + <spirit:displayName>Write wait</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isFlash</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + </spirit:vendorExtensions> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>read</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_read_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>readdata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_readdata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_reset_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>system_reset</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>reset</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>csi_system_reset</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>synchronousEdges</spirit:name> + <spirit:displayName>Synchronous edges</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>write</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_write_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>writedata</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>export</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>coe_writedata_export</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>associatedClock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>associatedReset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>prSafe</spirit:name> + <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>QUARTUS_SYNTH</spirit:name> + <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier> + <spirit:modelName>avs_common_mm</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>QUARTUS_SYNTH</spirit:localName> + </spirit:fileSetRef> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>csi_system_clk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>csi_system_reset</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>12</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_write</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_read</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>avs_mem_readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_reset_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_clk_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_address_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>12</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_write_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_writedata_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_read_export</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>coe_readdata_export</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>31</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + </spirit:model> + <spirit:vendorExtensions> + <altera:entity_info> + <spirit:vendor>ASTRON</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_rom_system_info</spirit:library> + <spirit:name>avs_common_mm</spirit:name> + <spirit:version>1.0</spirit:version> + </altera:entity_info> + <altera:altera_module_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>g_adr_w</spirit:name> + <spirit:displayName>g_adr_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>g_dat_w</spirit:name> + <spirit:displayName>g_dat_w</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name> + <spirit:displayName>Auto CLOCK_RATE</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element rom_system_info + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="address" altera:internal="rom_system_info.address" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="clk" altera:internal="rom_system_info.clk" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="mem" altera:internal="rom_system_info.mem" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping> + <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="read" altera:internal="rom_system_info.read" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="readdata" altera:internal="rom_system_info.readdata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="rom_system_info.reset" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system" altera:internal="rom_system_info.system" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="system_reset" altera:internal="rom_system_info.system_reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="write" altera:internal="rom_system_info.write" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="writedata" altera:internal="rom_system_info.writedata" altera:type="conduit" altera:dir="end"> + <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip new file mode 100644 index 0000000000000000000000000000000000000000..31c9f82ae973780253038399aeb8afc062087c2c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip @@ -0,0 +1,1361 @@ +<?xml version="1.0" ?> +<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>Intel Corporation</spirit:vendor> + <spirit:library>qsys_lofar2_unb2b_ring_timer_0</spirit:library> + <spirit:name>timer_0</spirit:name> + <spirit:version>18.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>clk</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>clk</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>clk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>clockRate</spirit:name> + <spirit:displayName>Clock rate</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>externallyDriven</spirit:name> + <spirit:displayName>Externally driven</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ptfSchematicName</spirit:name> + <spirit:displayName>PTF schematic name</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>irq</spirit:name> + <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType> + <spirit:slave></spirit:slave> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>irq</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>irq</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>associatedAddressablePoint</spirit:name> + <spirit:displayName>Associated addressable interface</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_lofar2_unb2b_ring_timer_0.s1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedClock</spirit:name> + <spirit:displayName>Associated clock</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>associatedReset</spirit:name> + <spirit:displayName>Associated reset</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bridgedReceiverOffset</spirit:name> + <spirit:displayName>Bridged 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</spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>address</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>writedata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>writedata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>readdata</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>readdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>chipselect</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>write_n</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>write_n</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>addressAlignment</spirit:name> + <spirit:displayName>Slave addressing</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressAlignment">NATIVE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressGroup</spirit:name> + <spirit:displayName>Address group</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressSpan</spirit:name> + <spirit:displayName>Address span</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>addressUnits</spirit:name> + <spirit:displayName>Address units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>alwaysBurstMaxBurst</spirit:name> + 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<spirit:parameter> + <spirit:name>maximumPendingReadTransactions</spirit:name> + <spirit:displayName>Maximum pending read transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>maximumPendingWriteTransactions</spirit:name> + <spirit:displayName>Maximum pending write transactions</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumReadLatency</spirit:name> + <spirit:displayName>minimumReadLatency</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>minimumResponseLatency</spirit:name> + <spirit:displayName>Minimum response latency</spirit:displayName> + <spirit:value spirit:format="long" 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</spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>reset_n</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>address</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>2</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>writedata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>15</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>readdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left>0</spirit:left> + <spirit:right>15</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName> + <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>chipselect</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>STD_LOGIC</spirit:typeName> + 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<spirit:displayName>Period</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="period">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>periodUnits</spirit:name> + <spirit:displayName>Units</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="periodUnits">MSEC</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>resetOutput</spirit:name> + <spirit:displayName>System reset on timeout (Watchdog)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="resetOutput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>snapshot</spirit:name> + <spirit:displayName>Readable snapshot</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="snapshot">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timeoutPulseOutput</spirit:name> + <spirit:displayName>Timeout pulse (1 clock wide)</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="timeoutPulseOutput">false</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemFrequency</spirit:name> + <spirit:displayName>systemFrequency</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemFrequency">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>watchdogPulse</spirit:name> + <spirit:displayName>Watchdog Timer Pulse Length</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="watchdogPulse">2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>timerPreset</spirit:name> + <spirit:displayName>Presets</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="timerPreset">SIMPLE_PERIODIC_INTERRUPT</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>periodUnitsString</spirit:name> + <spirit:displayName>periodUnitsString</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="periodUnitsString">ms</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>valueInSecond</spirit:name> + <spirit:displayName>valueInSecond</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="valueInSecond">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>loadValue</spirit:name> + <spirit:displayName>loadValue</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="loadValue">99999</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>mult</spirit:name> + <spirit:displayName>mult</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="mult">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ticksPerSec</spirit:name> + <spirit:displayName>ticksPerSec</spirit:displayName> + <spirit:value spirit:format="float" spirit:id="ticksPerSec">1000.0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>slave_address_width</spirit:name> + <spirit:displayName>slave_address_width</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="slave_address_width">3</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_module_parameters> + <altera:altera_assignments> + <spirit:parameters> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.ALWAYS_RUN</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALWAYS_RUN">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.COUNTER_SIZE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.COUNTER_SIZE">32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FIXED_PERIOD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FIXED_PERIOD">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.FREQ</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FREQ">100000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.LOAD_VALUE</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.LOAD_VALUE">99999</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.MULT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.MULT">0.001</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.PERIOD</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.PERIOD">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.PERIOD_UNITS</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.PERIOD_UNITS">ms</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.RESET_OUTPUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RESET_OUTPUT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.SNAPSHOT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SNAPSHOT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.TICKS_PER_SEC</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.TICKS_PER_SEC">1000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>embeddedsw.dts.vendor</spirit:name> + <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_assignments> + <altera:altera_system_parameters> + <spirit:parameters> + <spirit:parameter> + <spirit:name>device</spirit:name> + <spirit:displayName>Device</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceFamily</spirit:name> + <spirit:displayName>Device family</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>deviceSpeedGrade</spirit:name> + <spirit:displayName>Device Speed Grade</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>generationId</spirit:name> + <spirit:displayName>Generation Id</spirit:displayName> + <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>bonusData</spirit:name> + <spirit:displayName>bonusData</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="bonusData">bonusData +{ + element timer_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} +</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>hideFromIPCatalog</spirit:name> + <spirit:displayName>Hide from IP Catalog</spirit:displayName> + <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>lockedInterfaceDefinition</spirit:name> + <spirit:displayName>lockedInterfaceDefinition</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>qsys_lofar2_unb2b_ring_timer_0.s1</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isTimerDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>16</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>status</name> + <displayName>Status</displayName> + <description>The status register has two defined bits. TO (timeout), RUN</description> + <addressOffset>0x0</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + <fields> + <field><name>TO</name> + <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + <readAction>clear</readAction> + </field> + <field><name>RUN</name> + <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by + a write operation to the status register.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>2</bitOffset> + <bitWidth>14</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </fields> + </register> + <register> + <name>control</name> + <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description> + <addressOffset>0x1</addressOffset> + <size>16</size> + <access>read-write</access> + <reset> + <value>0x0</value> + </reset> + <field> + <name>ITO</name> + <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CONT</name> + <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>START</name> + <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description> + <bitOffset>2</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>STOP</name> + <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description> + <bitOffset>3</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>4</bitOffset> + <bitWidth>12</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </register> + <register> + <name>${period_name_0}</name> + <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description> + <addressOffset>0x2</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_name_1}</name> + <description></description> + <addressOffset>0x3</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_0}</name> + <description></description> + <addressOffset>0x4</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_1}</name> + <description></description> + <addressOffset>0x5</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_0}</name> + <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description> + <addressOffset>0x6</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_1}</name> + <description></description> + <addressOffset>0x7</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_2}</name> + <description></description> + <addressOffset>0x8</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_3}</name> + <description></description> + <addressOffset>0x9</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars> + <entry> + <key>period_name_1_reset_value</key> + <value>0x1</value> + </entry> + <entry> + <key>snap_0</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0_reset_value</key> + <value>0x869f</value> + </entry> + <entry> + <key>snap_2</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_1</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_3</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0</key> + <value>periodl</value> + </entry> + <entry> + <key>period_name_1</key> + <value>periodh</value> + </entry> + <entry> + <key>period_snap_1</key> + <value>snaph</value> + </entry> + <entry> + <key>period_snap_1_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0</key> + <value>snapl</value> + </entry> + </cmsisVars> + </cmsisInfo> + </interface> + </interfaces> +</boundaryDefinition>]]></spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>systemInfos</spirit:name> + <spirit:displayName>systemInfos</spirit:displayName> + <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>16</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></spirit:value> + </spirit:parameter> + </spirit:parameters> + </altera:altera_system_parameters> + <altera:altera_interface_boundary> + <altera:interface_mapping altera:name="clk" altera:internal="timer_0.clk" altera:type="clock" altera:dir="end"> + <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="irq" altera:internal="timer_0.irq" altera:type="interrupt" altera:dir="end"> + <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="reset" altera:internal="timer_0.reset" altera:type="reset" altera:dir="end"> + <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping> + </altera:interface_mapping> + <altera:interface_mapping altera:name="s1" altera:internal="timer_0.s1" altera:type="avalon" altera:dir="end"> + <altera:port_mapping altera:name="address" altera:internal="address"></altera:port_mapping> + <altera:port_mapping altera:name="chipselect" altera:internal="chipselect"></altera:port_mapping> + <altera:port_mapping altera:name="readdata" altera:internal="readdata"></altera:port_mapping> + <altera:port_mapping altera:name="write_n" altera:internal="write_n"></altera:port_mapping> + <altera:port_mapping altera:name="writedata" altera:internal="writedata"></altera:port_mapping> + </altera:interface_mapping> + </altera:altera_interface_boundary> + <altera:altera_has_warnings>false</altera:altera_has_warnings> + <altera:altera_has_errors>false</altera:altera_has_errors> + </spirit:vendorExtensions> +</spirit:component> \ No newline at end of file diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring.sdc b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring.sdc new file mode 100644 index 0000000000000000000000000000000000000000..ce015b6d6219689533c9506e2b06f5c25c83e9ef --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring.sdc @@ -0,0 +1,104 @@ +############################################################################### +# +# Copyright (C) 2018 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +############################################################################### + +# Constrain the input I/O path +#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs] +#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs] +# Constrain the output I/O path +#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs] +#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs] + + +# False path the PPS to DDIO: +#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}] +#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr} + + +#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] + +#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}] +#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}] + +#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*} + + + +set_time_format -unit ns -decimal_places 3 + +create_clock -period 125Mhz [get_ports {ETH_CLK}] +create_clock -period 200Mhz [get_ports {CLK}] +create_clock -period 100Mhz [get_ports {CLKUSR}] +create_clock -period 644.53125Mhz [get_ports {SA_CLK}] +create_clock -period 644.53125Mhz [get_ports {SB_CLK}] +create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK } + +# Create altera reserved tck to solve unconstrained clock warning. +create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck} + +derive_pll_clocks +derive_clock_uncertainty + +set_clock_groups -asynchronous -group {CLK} +set_clock_groups -asynchronous -group {BCK_REF_CLK} +set_clock_groups -asynchronous -group {CLK_USR} +set_clock_groups -asynchronous -group {CLKUSR} +set_clock_groups -asynchronous -group {SA_CLK} +set_clock_groups -asynchronous -group {SB_CLK} +# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work + +# Altera temp sense clock +set_clock_groups -asynchronous -group [get_clocks altera_ts_clk] + +# ALtera JTAG clock +set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] + +# IOPLL outputs (which have global names defined in the IP qsys settings) +set_clock_groups -asynchronous -group [get_clocks pll_clk20] +set_clock_groups -asynchronous -group [get_clocks pll_clk50] +set_clock_groups -asynchronous -group [get_clocks pll_clk100] +set_clock_groups -asynchronous -group [get_clocks pll_clk125] +set_clock_groups -asynchronous -group [get_clocks pll_clk200] +set_clock_groups -asynchronous -group [get_clocks pll_clk200p] +set_clock_groups -asynchronous -group [get_clocks pll_clk400] + + +# FPLL outputs +#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}] +#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}] +#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}] +#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}] +set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk2}] +set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk3}] + +set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}] + +#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*} + +#set_clock_groups -asynchronous \ +#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \ +#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}] + +# false paths added for the jesd interface as these clocks are independent. +set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}] +set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] +set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}] +set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl new file mode 100644 index 0000000000000000000000000000000000000000..851a631d744084345d1228d08c4c7b09bce10c5c --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl @@ -0,0 +1,534 @@ +############################################################################### +# +# Copyright (C) 2014 +# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +############################################################################### + +source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl +# unb2b_jesd204_pins contains undesired QSFP pinning +#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl +# +#===================== +# QSFP pins +# ==================== + +set_location_assignment PIN_AL32 -to CLKUSR + +set_location_assignment PIN_Y36 -to SA_CLK +set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK +# internal termination should be enabled. +set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK + +set_location_assignment PIN_AH9 -to SB_CLK +set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK +# internal termination should be enabled. +set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK + + +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + + +set_location_assignment PIN_AT31 -to QSFP_RST + +set_location_assignment PIN_AY33 -to QSFP_SCL[0] +set_location_assignment PIN_AY32 -to QSFP_SCL[1] +set_location_assignment PIN_AY30 -to QSFP_SCL[2] +set_location_assignment PIN_AN33 -to QSFP_SCL[3] +set_location_assignment PIN_AN31 -to QSFP_SCL[4] +set_location_assignment PIN_AJ33 -to QSFP_SCL[5] +set_location_assignment PIN_BA32 -to QSFP_SDA[0] +set_location_assignment PIN_BA31 -to QSFP_SDA[1] +set_location_assignment PIN_AP33 -to QSFP_SDA[2] +set_location_assignment PIN_AM33 -to QSFP_SDA[3] +set_location_assignment PIN_AK33 -to QSFP_SDA[4] +set_location_assignment PIN_AH32 -to QSFP_SDA[5] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST + +### QSFP_1_0 +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0] + +### QSFP_1_RX +set_location_assignment PIN_AC38 -to QSFP_1_RX[0] +set_location_assignment PIN_AD40 -to QSFP_1_RX[1] +set_location_assignment PIN_AF40 -to QSFP_1_RX[2] +set_location_assignment PIN_AG38 -to QSFP_1_RX[3] + +### QSFP_1_TX +set_location_assignment PIN_AC42 -to QSFP_1_TX[0] +set_location_assignment PIN_AD44 -to QSFP_1_TX[1] +set_location_assignment PIN_AF44 -to QSFP_1_TX[2] +set_location_assignment PIN_AG42 -to QSFP_1_TX[3] + + +#===================== +# JESD pins +# ==================== +# Pins needed for the 12 channel JESD204B interface to the ADCs +set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF +set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)" +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11] + +#set_location_assignment PIN_B9 -to BCK_RX[0] +set_location_assignment PIN_D9 -to BCK_RX[1] +set_location_assignment PIN_C11 -to BCK_RX[2] +set_location_assignment PIN_F9 -to BCK_RX[3] +set_location_assignment PIN_C7 -to BCK_RX[4] +set_location_assignment PIN_E11 -to BCK_RX[5] +set_location_assignment PIN_E7 -to BCK_RX[6] +set_location_assignment PIN_D5 -to BCK_RX[7] +set_location_assignment PIN_G7 -to BCK_RX[8] +set_location_assignment PIN_F5 -to BCK_RX[9] +set_location_assignment PIN_J7 -to BCK_RX[10] +set_location_assignment PIN_H5 -to BCK_RX[11] +set_location_assignment PIN_L7 -to BCK_RX[12] +set_location_assignment PIN_K5 -to BCK_RX[13] +set_location_assignment PIN_N7 -to BCK_RX[14] +set_location_assignment PIN_M5 -to BCK_RX[15] +set_location_assignment PIN_R7 -to BCK_RX[16] +set_location_assignment PIN_P5 -to BCK_RX[17] +set_location_assignment PIN_U7 -to BCK_RX[18] +set_location_assignment PIN_T5 -to BCK_RX[19] +set_location_assignment PIN_W7 -to BCK_RX[20] +set_location_assignment PIN_V5 -to BCK_RX[21] +set_location_assignment PIN_AA7 -to BCK_RX[22] +set_location_assignment PIN_Y5 -to BCK_RX[23] +set_location_assignment PIN_AC7 -to BCK_RX[24] +set_location_assignment PIN_AB5 -to BCK_RX[25] +set_location_assignment PIN_AE7 -to BCK_RX[26] +set_location_assignment PIN_AD5 -to BCK_RX[27] +set_location_assignment PIN_AG7 -to BCK_RX[28] +set_location_assignment PIN_AF5 -to BCK_RX[29] +set_location_assignment PIN_AJ7 -to BCK_RX[30] +set_location_assignment PIN_AH5 -to BCK_RX[31] +set_location_assignment PIN_AL7 -to BCK_RX[32] +set_location_assignment PIN_AK5 -to BCK_RX[33] +set_location_assignment PIN_AN7 -to BCK_RX[34] +set_location_assignment PIN_AM5 -to BCK_RX[35] +set_location_assignment PIN_AR7 -to BCK_RX[36] +set_location_assignment PIN_AP5 -to BCK_RX[37] +set_location_assignment PIN_AU7 -to BCK_RX[38] +set_location_assignment PIN_AT5 -to BCK_RX[39] +set_location_assignment PIN_AW7 -to BCK_RX[40] +set_location_assignment PIN_AV5 -to BCK_RX[41] +set_location_assignment PIN_BA7 -to BCK_RX[42] +set_location_assignment PIN_AY5 -to BCK_RX[43] +set_location_assignment PIN_BC7 -to BCK_RX[44] +set_location_assignment PIN_BB5 -to BCK_RX[45] +set_location_assignment PIN_AY9 -to BCK_RX[46] +set_location_assignment PIN_BB9 -to BCK_RX[47] + + +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10] +# +#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11] +#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11] +#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47] +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47] +set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47] + + +# Substitute new signal names from the jesd_simple design +#set_location_assignment PIN_BA7 -to BCK_RX[0] + +set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK +set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)" +set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK +set_location_assignment PIN_V9 -to BCK_REF_CLK +set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)" + +set_location_assignment PIN_V12 -to JESD204B_SYSREF +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF + +set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0] +set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1] + + diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys new file mode 100644 index 0000000000000000000000000000000000000000..ed28393abeccadf6702dafb6ea2281382a73ca83 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys @@ -0,0 +1,24727 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="qsys_lofar2_unb2b_ring"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="" + categories="System" + tool="QsysPro" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element avs_eth_0 + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element avs_eth_0.mms_ram + { + datum baseAddress + { + value = "8192"; + type = "String"; + } + } + element avs_eth_0.mms_reg + { + datum baseAddress + { + value = "128"; + type = "String"; + } + } + element avs_eth_0.mms_tse + { + datum baseAddress + { + value = "4096"; + type = "String"; + } + } + element clk_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element cpu_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element cpu_0.debug_mem_slave + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "14336"; + type = "String"; + } + } + element jtag_uart_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element jtag_uart_0.avalon_jtag_slave + { + datum baseAddress + { + value = "13568"; + type = "String"; + } + } + element jtag_uart_0.irq + { + datum _tags + { + value = ""; + type = "String"; + } + } + element onchip_memory2_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element onchip_memory2_0.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "131072"; + type = "String"; + } + } + element pio_pps + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } + } + element pio_pps.mem + { + datum baseAddress + { + value = "13520"; + type = "String"; + } + } + element pio_system_info + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element pio_system_info.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } + element pio_wdi + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element pio_wdi.s1 + { + datum baseAddress + { + value = "12304"; + type = "String"; + } + } + element ram_diag_bg + { + datum _sortIndex + { + value = "33"; + type = "int"; + } + } + element ram_diag_bg.mem + { + datum baseAddress + { + value = "512"; + type = "String"; + } + } + element ram_scrap + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + } + element ram_scrap.mem + { + datum baseAddress + { + value = "2048"; + type = "String"; + } + } + element reg_bsn_monitor_v2_ring_rx + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + } + element reg_bsn_monitor_v2_ring_rx.mem + { + datum baseAddress + { + value = "12800"; + type = "String"; + } + } + element reg_bsn_monitor_v2_ring_tx + { + datum _sortIndex + { + value = "23"; + type = "int"; + } + } + element reg_bsn_monitor_v2_ring_tx.mem + { + datum baseAddress + { + value = "1536"; + type = "String"; + } + } + element reg_diag_bg + { + datum _sortIndex + { + value = "32"; + type = "int"; + } + } + element reg_diag_bg.mem + { + datum baseAddress + { + value = "12320"; + type = "String"; + } + } + element reg_dp_block_validate_bsn_at_sync + { + datum _sortIndex + { + value = "28"; + type = "int"; + } + } + element reg_dp_block_validate_bsn_at_sync.mem + { + datum baseAddress + { + value = "12352"; + type = "String"; + } + } + element reg_dp_block_validate_err + { + datum _sortIndex + { + value = "27"; + type = "int"; + } + } + element reg_dp_block_validate_err.mem + { + datum baseAddress + { + value = "1024"; + type = "String"; + } + } + element reg_dp_xonoff_lane + { + datum _sortIndex + { + value = "25"; + type = "int"; + } + } + element reg_dp_xonoff_lane.mem + { + datum baseAddress + { + value = "12480"; + type = "String"; + } + } + element reg_dp_xonoff_local + { + datum _sortIndex + { + value = "26"; + type = "int"; + } + } + element reg_dp_xonoff_local.mem + { + datum baseAddress + { + value = "12416"; + type = "String"; + } + } + element reg_dpmm_ctrl + { + datum _sortIndex + { + value = "16"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_dpmm_ctrl.mem + { + datum baseAddress + { + value = "13560"; + type = "String"; + } + } + element reg_dpmm_data + { + datum _sortIndex + { + value = "17"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_dpmm_data.mem + { + datum baseAddress + { + value = "13552"; + type = "String"; + } + } + element reg_epcs + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_epcs.mem + { + datum baseAddress + { + value = "13440"; + type = "String"; + } + } + element reg_fpga_temp_sens + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element reg_fpga_temp_sens.mem + { + datum baseAddress + { + value = "13408"; + type = "String"; + } + } + element reg_fpga_voltage_sens + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_fpga_voltage_sens.mem + { + datum baseAddress + { + value = "13312"; + type = "String"; + } + } + element reg_mmdp_ctrl + { + datum _sortIndex + { + value = "18"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_mmdp_ctrl.mem + { + datum baseAddress + { + value = "13544"; + type = "String"; + } + } + element reg_mmdp_data + { + datum _sortIndex + { + value = "19"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_mmdp_data.mem + { + datum baseAddress + { + value = "13536"; + type = "String"; + } + } + element reg_remu + { + datum _sortIndex + { + value = "14"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_remu.mem + { + datum baseAddress + { + value = "13472"; + type = "String"; + } + } + element reg_ring_info + { + datum _sortIndex + { + value = "29"; + type = "int"; + } + } + element reg_ring_info.mem + { + datum baseAddress + { + value = "13504"; + type = "String"; + } + } + element reg_ring_lane_info + { + datum _sortIndex + { + value = "24"; + type = "int"; + } + } + element reg_ring_lane_info.mem + { + datum baseAddress + { + value = "192"; + type = "String"; + } + } + element reg_tr_10gbe_eth10g + { + datum _sortIndex + { + value = "31"; + type = "int"; + } + } + element reg_tr_10gbe_eth10g.mem + { + datum baseAddress + { + value = "12296"; + type = "String"; + } + } + element reg_tr_10gbe_mac + { + datum _sortIndex + { + value = "30"; + type = "int"; + } + } + element reg_tr_10gbe_mac.mem + { + datum baseAddress + { + value = "32768"; + type = "String"; + } + } + element reg_unb_pmbus + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } + element reg_unb_pmbus.mem + { + datum baseAddress + { + value = "256"; + type = "String"; + } + } + element reg_unb_sens + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element reg_unb_sens.mem + { + datum baseAddress + { + value = "12544"; + type = "String"; + } + } + element reg_wdi + { + datum _sortIndex + { + value = "13"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element reg_wdi.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "12288"; + type = "String"; + } + } + element rom_system_info + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } + } + element rom_system_info.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "65536"; + type = "String"; + } + } + element timer_0 + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element timer_0.s1 + { + datum baseAddress + { + value = "13376"; + type = "String"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="10AX115U2F45E1SG" /> + <parameter name="deviceFamily" value="Arria 10" /> + <parameter name="deviceSpeedGrade" value="1" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="false" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="0" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="systemInfos"><![CDATA[<systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>rom_system_info_clk</key> + <value> + <connectionPointName>rom_system_info_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition>]]></parameter> + <parameter name="systemScripts" value="" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="avs_eth_0_clk" + internal="avs_eth_0.clk" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_irq" + internal="avs_eth_0.irq" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_address" + internal="avs_eth_0.ram_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_read" + internal="avs_eth_0.ram_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_readdata" + internal="avs_eth_0.ram_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_write" + internal="avs_eth_0.ram_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_ram_writedata" + internal="avs_eth_0.ram_writedata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_address" + internal="avs_eth_0.reg_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_read" + internal="avs_eth_0.reg_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_readdata" + internal="avs_eth_0.reg_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_write" + internal="avs_eth_0.reg_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reg_writedata" + internal="avs_eth_0.reg_writedata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_reset" + internal="avs_eth_0.reset" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_address" + internal="avs_eth_0.tse_address" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_read" + internal="avs_eth_0.tse_read" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_readdata" + internal="avs_eth_0.tse_readdata" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_waitrequest" + internal="avs_eth_0.tse_waitrequest" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_write" + internal="avs_eth_0.tse_write" + type="conduit" + dir="end" /> + <interface + name="avs_eth_0_tse_writedata" + internal="avs_eth_0.tse_writedata" + type="conduit" + dir="end" /> + <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> + <interface + name="pio_pps_address" + internal="pio_pps.address" + type="conduit" + dir="end" /> + <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" /> + <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" /> + <interface + name="pio_pps_readdata" + internal="pio_pps.readdata" + type="conduit" + dir="end" /> + <interface + name="pio_pps_reset" + internal="pio_pps.reset" + type="conduit" + dir="end" /> + <interface + name="pio_pps_write" + internal="pio_pps.write" + type="conduit" + dir="end" /> + <interface + name="pio_pps_writedata" + internal="pio_pps.writedata" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_address" + internal="pio_system_info.address" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_clk" + internal="pio_system_info.clk" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_read" + internal="pio_system_info.read" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_readdata" + internal="pio_system_info.readdata" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_reset" + internal="pio_system_info.reset" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_write" + internal="pio_system_info.write" + type="conduit" + dir="end" /> + <interface + name="pio_system_info_writedata" + internal="pio_system_info.writedata" + type="conduit" + dir="end" /> + <interface + name="pio_wdi_external_connection" + internal="pio_wdi.external_connection" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_address" + internal="ram_diag_bg.address" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_clk" + internal="ram_diag_bg.clk" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_read" + internal="ram_diag_bg.read" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_readdata" + internal="ram_diag_bg.readdata" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_reset" + internal="ram_diag_bg.reset" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_write" + internal="ram_diag_bg.write" + type="conduit" + dir="end" /> + <interface + name="ram_diag_bg_writedata" + internal="ram_diag_bg.writedata" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_address" + internal="ram_scrap.address" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_clk" + internal="ram_scrap.clk" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_read" + internal="ram_scrap.read" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_readdata" + internal="ram_scrap.readdata" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_reset" + internal="ram_scrap.reset" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_write" + internal="ram_scrap.write" + type="conduit" + dir="end" /> + <interface + name="ram_scrap_writedata" + internal="ram_scrap.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_address" + internal="reg_bsn_monitor_v2_ring_rx.address" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_clk" + internal="reg_bsn_monitor_v2_ring_rx.clk" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_read" + internal="reg_bsn_monitor_v2_ring_rx.read" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_readdata" + internal="reg_bsn_monitor_v2_ring_rx.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_reset" + internal="reg_bsn_monitor_v2_ring_rx.reset" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_write" + internal="reg_bsn_monitor_v2_ring_rx.write" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_rx_writedata" + internal="reg_bsn_monitor_v2_ring_rx.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_address" + internal="reg_bsn_monitor_v2_ring_tx.address" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_clk" + internal="reg_bsn_monitor_v2_ring_tx.clk" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_read" + internal="reg_bsn_monitor_v2_ring_tx.read" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_readdata" + internal="reg_bsn_monitor_v2_ring_tx.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_reset" + internal="reg_bsn_monitor_v2_ring_tx.reset" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_write" + internal="reg_bsn_monitor_v2_ring_tx.write" + type="conduit" + dir="end" /> + <interface + name="reg_bsn_monitor_v2_ring_tx_writedata" + internal="reg_bsn_monitor_v2_ring_tx.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_address" + internal="reg_diag_bg.address" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_clk" + internal="reg_diag_bg.clk" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_read" + internal="reg_diag_bg.read" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_readdata" + internal="reg_diag_bg.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_reset" + internal="reg_diag_bg.reset" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_write" + internal="reg_diag_bg.write" + type="conduit" + dir="end" /> + <interface + name="reg_diag_bg_writedata" + internal="reg_diag_bg.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_address" + internal="reg_dp_block_validate_bsn_at_sync.address" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_clk" + internal="reg_dp_block_validate_bsn_at_sync.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_read" + internal="reg_dp_block_validate_bsn_at_sync.read" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_readdata" + internal="reg_dp_block_validate_bsn_at_sync.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_reset" + internal="reg_dp_block_validate_bsn_at_sync.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_write" + internal="reg_dp_block_validate_bsn_at_sync.write" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_bsn_at_sync_writedata" + internal="reg_dp_block_validate_bsn_at_sync.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_address" + internal="reg_dp_block_validate_err.address" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_clk" + internal="reg_dp_block_validate_err.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_read" + internal="reg_dp_block_validate_err.read" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_readdata" + internal="reg_dp_block_validate_err.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_reset" + internal="reg_dp_block_validate_err.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_write" + internal="reg_dp_block_validate_err.write" + type="conduit" + dir="end" /> + <interface + name="reg_dp_block_validate_err_writedata" + internal="reg_dp_block_validate_err.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_address" + internal="reg_dp_xonoff_lane.address" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_clk" + internal="reg_dp_xonoff_lane.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_read" + internal="reg_dp_xonoff_lane.read" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_readdata" + internal="reg_dp_xonoff_lane.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_reset" + internal="reg_dp_xonoff_lane.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_write" + internal="reg_dp_xonoff_lane.write" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_lane_writedata" + internal="reg_dp_xonoff_lane.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_address" + internal="reg_dp_xonoff_local.address" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_clk" + internal="reg_dp_xonoff_local.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_read" + internal="reg_dp_xonoff_local.read" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_readdata" + internal="reg_dp_xonoff_local.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_reset" + internal="reg_dp_xonoff_local.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_write" + internal="reg_dp_xonoff_local.write" + type="conduit" + dir="end" /> + <interface + name="reg_dp_xonoff_local_writedata" + internal="reg_dp_xonoff_local.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_address" + internal="reg_dpmm_ctrl.address" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_clk" + internal="reg_dpmm_ctrl.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_read" + internal="reg_dpmm_ctrl.read" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_readdata" + internal="reg_dpmm_ctrl.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_reset" + internal="reg_dpmm_ctrl.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_write" + internal="reg_dpmm_ctrl.write" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_ctrl_writedata" + internal="reg_dpmm_ctrl.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_address" + internal="reg_dpmm_data.address" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_clk" + internal="reg_dpmm_data.clk" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_read" + internal="reg_dpmm_data.read" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_readdata" + internal="reg_dpmm_data.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_reset" + internal="reg_dpmm_data.reset" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_write" + internal="reg_dpmm_data.write" + type="conduit" + dir="end" /> + <interface + name="reg_dpmm_data_writedata" + internal="reg_dpmm_data.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_address" + internal="reg_epcs.address" + type="conduit" + dir="end" /> + <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" /> + <interface + name="reg_epcs_read" + internal="reg_epcs.read" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_readdata" + internal="reg_epcs.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_reset" + internal="reg_epcs.reset" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_write" + internal="reg_epcs.write" + type="conduit" + dir="end" /> + <interface + name="reg_epcs_writedata" + internal="reg_epcs.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_address" + internal="reg_fpga_temp_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_clk" + internal="reg_fpga_temp_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_read" + internal="reg_fpga_temp_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_readdata" + internal="reg_fpga_temp_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_reset" + internal="reg_fpga_temp_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_write" + internal="reg_fpga_temp_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_temp_sens_writedata" + internal="reg_fpga_temp_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_address" + internal="reg_fpga_voltage_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_clk" + internal="reg_fpga_voltage_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_read" + internal="reg_fpga_voltage_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_readdata" + internal="reg_fpga_voltage_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_reset" + internal="reg_fpga_voltage_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_write" + internal="reg_fpga_voltage_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_fpga_voltage_sens_writedata" + internal="reg_fpga_voltage_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_address" + internal="reg_mmdp_ctrl.address" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_clk" + internal="reg_mmdp_ctrl.clk" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_read" + internal="reg_mmdp_ctrl.read" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_readdata" + internal="reg_mmdp_ctrl.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_reset" + internal="reg_mmdp_ctrl.reset" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_write" + internal="reg_mmdp_ctrl.write" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_ctrl_writedata" + internal="reg_mmdp_ctrl.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_address" + internal="reg_mmdp_data.address" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_clk" + internal="reg_mmdp_data.clk" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_read" + internal="reg_mmdp_data.read" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_readdata" + internal="reg_mmdp_data.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_reset" + internal="reg_mmdp_data.reset" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_write" + internal="reg_mmdp_data.write" + type="conduit" + dir="end" /> + <interface + name="reg_mmdp_data_writedata" + internal="reg_mmdp_data.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_remu_address" + internal="reg_remu.address" + type="conduit" + dir="end" /> + <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" /> + <interface + name="reg_remu_read" + internal="reg_remu.read" + type="conduit" + dir="end" /> + <interface + name="reg_remu_readdata" + internal="reg_remu.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_remu_reset" + internal="reg_remu.reset" + type="conduit" + dir="end" /> + <interface + name="reg_remu_write" + internal="reg_remu.write" + type="conduit" + dir="end" /> + <interface + name="reg_remu_writedata" + internal="reg_remu.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_address" + internal="reg_ring_info.address" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_clk" + internal="reg_ring_info.clk" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_read" + internal="reg_ring_info.read" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_readdata" + internal="reg_ring_info.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_reset" + internal="reg_ring_info.reset" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_write" + internal="reg_ring_info.write" + type="conduit" + dir="end" /> + <interface + name="reg_ring_info_writedata" + internal="reg_ring_info.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_address" + internal="reg_ring_lane_info.address" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_clk" + internal="reg_ring_lane_info.clk" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_read" + internal="reg_ring_lane_info.read" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_readdata" + internal="reg_ring_lane_info.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_reset" + internal="reg_ring_lane_info.reset" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_write" + internal="reg_ring_lane_info.write" + type="conduit" + dir="end" /> + <interface + name="reg_ring_lane_info_writedata" + internal="reg_ring_lane_info.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_address" + internal="reg_tr_10gbe_eth10g.address" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_clk" + internal="reg_tr_10gbe_eth10g.clk" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_read" + internal="reg_tr_10gbe_eth10g.read" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_readdata" + internal="reg_tr_10gbe_eth10g.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_reset" + internal="reg_tr_10gbe_eth10g.reset" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_write" + internal="reg_tr_10gbe_eth10g.write" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_eth10g_writedata" + internal="reg_tr_10gbe_eth10g.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_address" + internal="reg_tr_10gbe_mac.address" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_clk" + internal="reg_tr_10gbe_mac.clk" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_read" + internal="reg_tr_10gbe_mac.read" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_readdata" + internal="reg_tr_10gbe_mac.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_reset" + internal="reg_tr_10gbe_mac.reset" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_write" + internal="reg_tr_10gbe_mac.write" + type="conduit" + dir="end" /> + <interface + name="reg_tr_10gbe_mac_writedata" + internal="reg_tr_10gbe_mac.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_address" + internal="reg_unb_pmbus.address" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_clk" + internal="reg_unb_pmbus.clk" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_read" + internal="reg_unb_pmbus.read" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_readdata" + internal="reg_unb_pmbus.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_reset" + internal="reg_unb_pmbus.reset" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_write" + internal="reg_unb_pmbus.write" + type="conduit" + dir="end" /> + <interface + name="reg_unb_pmbus_writedata" + internal="reg_unb_pmbus.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_address" + internal="reg_unb_sens.address" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_clk" + internal="reg_unb_sens.clk" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_read" + internal="reg_unb_sens.read" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_readdata" + internal="reg_unb_sens.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_reset" + internal="reg_unb_sens.reset" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_write" + internal="reg_unb_sens.write" + type="conduit" + dir="end" /> + <interface + name="reg_unb_sens_writedata" + internal="reg_unb_sens.writedata" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_address" + internal="reg_wdi.address" + type="conduit" + dir="end" /> + <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" /> + <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" /> + <interface + name="reg_wdi_readdata" + internal="reg_wdi.readdata" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_reset" + internal="reg_wdi.reset" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_write" + internal="reg_wdi.write" + type="conduit" + dir="end" /> + <interface + name="reg_wdi_writedata" + internal="reg_wdi.writedata" + type="conduit" + dir="end" /> + <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> + <interface + name="rom_system_info_address" + internal="rom_system_info.address" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_clk" + internal="rom_system_info.clk" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_read" + internal="rom_system_info.read" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_readdata" + internal="rom_system_info.readdata" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_reset" + internal="rom_system_info.reset" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_write" + internal="rom_system_info.write" + type="conduit" + dir="end" /> + <interface + name="rom_system_info_writedata" + internal="rom_system_info.writedata" + type="conduit" + dir="end" /> + <module + name="avs_eth_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>interrupt</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>ins_interrupt_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>avs_eth_0.mms_reg</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_irq_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mm</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_mm_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mm_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_mm_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_ram</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_ram_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_ram_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_ram_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>2</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_reg</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_reg_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_reg_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_reg_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mms_tse</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>mms_tse_address</name> + <role>address</role> + <direction>Input</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>mms_tse_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mms_tse_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4096</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>mm</value> + </entry> + <entry> + <key>associatedReset</key> + <value>mm_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ram_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_ram_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reg_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reg_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_waitrequest</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_waitrequest_export</name> + <role>export</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>tse_writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_tse_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs2_eth_coe</className> + <version>1.0</version> + <displayName>avs2_eth_coe</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mms_ram</key> + <value> + <connectionPointName>mms_ram</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_ram' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>mms_reg</key> + <value> + <connectionPointName>mms_reg</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_reg' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>mms_tse</key> + <value> + <connectionPointName>mms_tse</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mms_tse' start='0x0' end='0x1000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_avs_eth_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_avs_eth_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="clk_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>100000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_clk_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_clk_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_clk_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_clk_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_clk_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="cpu_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>custom_instruction_master</name> + <type>nios_custom_instruction</type> + <isStart>true</isStart> + <ports> + <port> + <name>dummy_ci_port</name> + <role>readra</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>CIName</key> + <value></value> + </entry> + <entry> + <key>addressWidth</key> + <value>8</value> + </entry> + <entry> + <key>clockCycle</key> + <value>0</value> + </entry> + <entry> + <key>enabled</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>8</value> + </entry> + <entry> + <key>opcodeExtension</key> + <value>0</value> + </entry> + <entry> + <key>sharedCombinationalAndMulticycle</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>data_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>d_address</name> + <role>address</role> + <direction>Output</direction> + <width>18</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>d_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>d_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_debugaccess_to_roms</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>1</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>true</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>true</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>debug_mem_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>debug_mem_slave_address</name> + <role>address</role> + <direction>Input</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>debug_mem_slave_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>debug_mem_slave_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.hideDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>qsys.ui.connect</key> + <value>instruction_master,data_master</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2048</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>true</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>debug_reset_request</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>debug_reset_request</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>instruction_master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>i_address</name> + <role>address</role> + <direction>Output</direction> + <width>18</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>i_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>i_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>i_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>1</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>true</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>true</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>true</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>cpu_0.data_master</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>irqMap</key> + </entry> + <entry> + <key>irqScheme</key> + <value>INDIVIDUAL_REQUESTS</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>reset_req</name> + <role>reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_nios2_gen2</className> + <version>18.0</version> + <displayName>Nios II Processor</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_DOMAIN</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>RESET_DOMAIN</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>50000000</parameterDefaultValue> + <parameterName>clockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_a</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_a</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_b</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_b</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>customInstSlavesSystemInfo_nios_c</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>custom_instruction_master_c</systemInfoArgs> + <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>dataAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>data_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>dataMasterHighPerformanceAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>data_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>dataMasterHighPerformanceMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>data_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>dataSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>data_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>STRATIXIV</parameterDefaultValue> + <parameterName>deviceFamilyName</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>deviceFeaturesSystemInfo</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FEATURES</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>faAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>flash_instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>faSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>flash_instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>instAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>instSlaveMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>instruction_master</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>instruction_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>instructionMasterHighPerformanceMapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>instruction_master_high_performance</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>internalIrqMaskSystemInfo</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>irq</systemInfoArgs> + <systemInfotype>INTERRUPTS_USED</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster0MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster1MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster2MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledDataMaster3MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_WIDTH</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs> + <systemInfotype>ADDRESS_MAP</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_DOMAIN</key> + <value>1</value> + </entry> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + <entry> + <key>RESET_DOMAIN</key> + <value>1</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>custom_instruction_master</key> + <value> + <connectionPointName>custom_instruction_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CUSTOM_INSTRUCTION_SLAVES</key> + <value></value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>data_master</key> + <value> + <connectionPointName>data_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>debug_mem_slave</key> + <value> + <connectionPointName>debug_mem_slave</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>instruction_master</key> + <value> + <connectionPointName>instruction_master</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>irq</key> + <value> + <connectionPointName>irq</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>INTERRUPTS_USED</key> + <value>7</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_cpu_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_cpu_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_cpu_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_cpu_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_cpu_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>debug.hostConnection</key> + <value>type jtag id 70:34|110:135</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIG_ENDIAN</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BREAK_ADDR</key> + <value>0x00003820</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_FREQ</key> + <value>100000000u</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ID_SIZE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_ID_VALUE</key> + <value>0x00000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key> + <value>"tiny"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DCACHE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EXCEPTION_ADDR</key> + <value>0x00020020</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key> + <value></value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ICACHE_SIZE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>embeddedsw.CMacro.OCI_VERSION</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_ADDR</key> + <value>0x00020000</value> + </entry> + <entry> + <key>embeddedsw.configuration.DataCacheVictimBufImpl</key> + <value>ram</value> + </entry> + <entry> + <key>embeddedsw.configuration.HDLSimCachesCleared</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.breakOffset</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.configuration.breakSlave</key> + <value>cpu_0.debug_mem_slave</value> + </entry> + <entry> + <key>embeddedsw.configuration.cpuArchitecture</key> + <value>Nios II</value> + </entry> + <entry> + <key>embeddedsw.configuration.exceptionOffset</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.configuration.exceptionSlave</key> + <value>onchip_memory2_0.s1</value> + </entry> + <entry> + <key>embeddedsw.configuration.resetOffset</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.resetSlave</key> + <value>onchip_memory2_0.s1</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,nios2-1.1</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>cpu</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>nios2</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,exception-addr</key> + <value>0x00020020</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,implementation</key> + <value>"tiny"</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,reset-addr</key> + <value>0x00020000</value> + </entry> + <entry> + <key>embeddedsw.dts.params.clock-frequency</key> + <value>100000000u</value> + </entry> + <entry> + <key>embeddedsw.dts.params.dcache-line-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.dcache-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.icache-line-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.params.icache-size</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="jtag_uart_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>8</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>8</bitWidth> + <access>read-write</access> + </field> + <field><name>rvalid</name> + <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description> + <bitOffset>0xf</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ravail</name> + <description>The number of characters remaining in the read FIFO (after the current read).</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + <register> + <name>CONTROL</name> + <displayName>Control</displayName> + <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>re</name> + <description>Interrupt-enable bit for read interrupts.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>we</name> + <description>Interrupt-enable bit for write interrupts</description> + <bitOffset>0x1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>ri</name> + <description>Indicates that the read interrupt is pending.</description> + <bitOffset>0x8</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>wi</name> + <description>Indicates that the write interrupt is pending.</description> + <bitOffset>0x9</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field><name>ac</name> + <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description> + <bitOffset>0xa</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field><name>wspace</name> + <description>The number of spaces available in the write FIFO</description> + <bitOffset>0x10</bitOffset> + <bitWidth>16</bitWidth> + <access>read-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_jtag_uart</className> + <version>18.0</version> + <displayName>JTAG UART Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>avalonSpec</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>AVALON_SPEC</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clkFreq</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_jtag_uart_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_jtag_uart_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.READ_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.READ_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_DEPTH</key> + <value>64</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITE_THRESHOLD</key> + <value>8</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,juart-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>serial</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>juart</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="onchip_memory2_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk1</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset1</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>reset_req</name> + <role>reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>clken</name> + <role>clken</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk1</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset1</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>131072</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_onchip_memory2</className> + <version>18.0</version> + <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>autoInitializationFileName</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>UNIQUE_ID</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>NONE</parameterDefaultValue> + <parameterName>deviceFamily</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>NONE</parameterDefaultValue> + <parameterName>deviceFeatures</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FEATURES</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>17</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_onchip_memory2_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_onchip_memory2_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CONTENTS_INFO</key> + <value>""</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DUAL_PORT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key> + <value>AUTO</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key> + <value>onchip_memory2_0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INSTANCE_ID</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key> + <value>AUTO</value> + </entry> + <entry> + <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key> + <value>DONT_CARE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SIZE_MULTIPLE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SIZE_VALUE</key> + <value>131072</value> + </entry> + <entry> + <key>embeddedsw.CMacro.WRITABLE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key> + <value>SIM_DIR</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.GENERATE_HEX</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key> + <value>QPF_DIR</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key> + <value>onchip_memory2_0</value> + </entry> + <entry> + <key>postgeneration.simulation.init_file.param_name</key> + <value>INIT_FILE</value> + </entry> + <entry> + <key>postgeneration.simulation.init_file.type</key> + <value>MEM_INIT</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_pps" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_pio_pps</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_pps</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_pps</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_pps</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_pps</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_system_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>5</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>128</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>7</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_pio_system_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_system_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="pio_wdi" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external_connection</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>out_port</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>4</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>32</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>DATA</name> + <displayName>Data</displayName> + <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description> + <addressOffset>0x0</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>data</name> + <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>DIRECTION</name> + <displayName>Direction</displayName> + <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description> + <addressOffset>0x4</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>direction</name> + <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>IRQ_MASK</name> + <displayName>Interrupt mask</displayName> + <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description> + <addressOffset>0x8</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>interruptmask</name> + <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>EDGE_CAP</name> + <displayName>Edge capture</displayName> + <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description> + <addressOffset>0xc</addressOffset> + <size>32</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>edgecapture</name> + <description>Edge detection for each input port.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>SET_BIT</name> + <displayName>Outset</displayName> + <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x10</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outset</name> + <description>Specifies which bit of the output port to set.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + <register> + <name>CLEAR_BITS</name> + <displayName>Outclear</displayName> + <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description> + <addressOffset>0x14</addressOffset> + <size>32</size> + <access>write-only</access> + <resetValue>0x0</resetValue> + <resetMask>0xffffffff</resetMask> + <fields> + <field><name>outclear</name> + <description>Specifies which output bit to clear.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>32</bitWidth> + <access>write-only</access> + </field> + </fields> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_pio</className> + <version>18.0</version> + <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>clockRate</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_pio_wdi</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_pio_wdi</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CAPTURE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATA_WIDTH</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EDGE_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>100000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_IN</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_OUT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.HAS_TRI</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.IRQ_TYPE</key> + <value>NONE</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_VALUE</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,pio-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>gpio</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>pio</value> + </entry> + <entry> + <key>embeddedsw.dts.params.altr,gpio-bank-width</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.dts.params.resetvalue</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="ram_diag_bg" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>512</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_ram_diag_bg</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_diag_bg</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="ram_scrap" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2048</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>11</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_ram_scrap</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_ram_scrap</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_bsn_monitor_v2_ring_rx" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>512</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_bsn_monitor_v2_ring_tx" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>512</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_diag_bg" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_diag_bg</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_diag_bg</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dp_block_validate_bsn_at_sync" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dp_block_validate_err" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>512</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>9</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_block_validate_err</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dp_xonoff_lane" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dp_xonoff_local" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dp_xonoff_local</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dpmm_ctrl" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_ctrl</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_dpmm_data" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_dpmm_data</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_dpmm_data</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_epcs" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_epcs</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_epcs</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_fpga_temp_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_temp_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_fpga_voltage_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_mmdp_ctrl" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_ctrl</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_mmdp_data" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_mmdp_data</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_mmdp_data</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_remu" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_remu</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_remu</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_remu</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_ring_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>16</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>4</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_ring_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_ring_lane_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>64</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>6</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_ring_lane_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_tr_10gbe_eth10g" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_tr_10gbe_mac" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_unb_pmbus" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_pmbus</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_unb_sens" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>256</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>8</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_unb_sens</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_unb_sens</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="reg_wdi" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_reg_wdi</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_reg_wdi</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="rom_system_info" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>address</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_address_export</name> + <role>export</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_clk_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>avs_mem_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>avs_mem_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>avs_mem_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>associatedReset</key> + <value>system_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>1</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>read</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_read_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>readdata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_readdata_export</name> + <role>export</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_reset_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>system_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>csi_system_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>system</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>write</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_write_export</name> + <role>export</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>writedata</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>coe_writedata_export</name> + <role>export</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>avs_common_mm</className> + <version>1.0</version> + <displayName>avs_common_mm</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>system</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>mem</key> + <value> + <connectionPointName>mem</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>system</key> + <value> + <connectionPointName>system</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_rom_system_info</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_rom_system_info</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <module + name="timer_0" + kind="altera_generic_component" + version="1.0" + enabled="1"> + <parameter name="componentDefinition"><![CDATA[<componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>timer_0.s1</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s1</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>address</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isTimerDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" > + <peripherals> + <peripheral> + <name>altera_avalon_timer</name><baseAddress>0x00000000</baseAddress> + <addressBlock> + <offset>0x0</offset> + <size>16</size> + <usage>registers</usage> + </addressBlock> + <registers> + <register> + <name>status</name> + <displayName>Status</displayName> + <description>The status register has two defined bits. TO (timeout), RUN</description> + <addressOffset>0x0</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + <fields> + <field><name>TO</name> + <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description> + <bitOffset>0x0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + <readAction>clear</readAction> + </field> + <field><name>RUN</name> + <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by + a write operation to the status register.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>2</bitOffset> + <bitWidth>14</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </fields> + </register> + <register> + <name>control</name> + <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description> + <addressOffset>0x1</addressOffset> + <size>16</size> + <access>read-write</access> + <reset> + <value>0x0</value> + </reset> + <field> + <name>ITO</name> + <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>CONT</name> + <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <access>read-write</access> + </field> + <field> + <name>START</name> + <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description> + <bitOffset>2</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>STOP</name> + <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description> + <bitOffset>3</bitOffset> + <bitWidth>1</bitWidth> + <access>write-only</access> + </field> + <field> + <name>Reserved</name> + <description>Reserved</description> + <bitOffset>4</bitOffset> + <bitWidth>12</bitWidth> + <access>read-write</access> + <parameters> + <parameter> + <name>Reserved</name> + <value>true</value> + </parameter> + </parameters> + </field> + </register> + <register> + <name>${period_name_0}</name> + <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description> + <addressOffset>0x2</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_name_1}</name> + <description></description> + <addressOffset>0x3</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_name_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_0}</name> + <description></description> + <addressOffset>0x4</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_0_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${period_snap_1}</name> + <description></description> + <addressOffset>0x5</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>${period_snap_1_reset_value}</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_0}</name> + <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description> + <addressOffset>0x6</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_1}</name> + <description></description> + <addressOffset>0x7</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_2}</name> + <description></description> + <addressOffset>0x8</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + <register> + <name>${snap_3}</name> + <description></description> + <addressOffset>0x9</addressOffset> + <size>16</size> + <access>read-write</access> + <resetValue>0x0</resetValue> + <resetMask>0xffff</resetMask> + </register> + </registers> + </peripheral> + </peripherals> +</device> </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars> + <entry> + <key>period_name_1_reset_value</key> + <value>0x1</value> + </entry> + <entry> + <key>snap_0</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0_reset_value</key> + <value>0x869f</value> + </entry> + <entry> + <key>snap_2</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_1</key> + <value>Reserved</value> + </entry> + <entry> + <key>snap_3</key> + <value>Reserved</value> + </entry> + <entry> + <key>period_name_0</key> + <value>periodl</value> + </entry> + <entry> + <key>period_name_1</key> + <value>periodh</value> + </entry> + <entry> + <key>period_snap_1</key> + <value>snaph</value> + </entry> + <entry> + <key>period_snap_1_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0_reset_value</key> + <value>0x0</value> + </entry> + <entry> + <key>period_snap_0</key> + <value>snapl</value> + </entry> + </cmsisVars> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_timer</className> + <version>18.0</version> + <displayName>Interval Timer Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>systemFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>s1</key> + <value> + <connectionPointName>s1</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value><address-map><slave name='s1' start='0x0' end='0x20' datawidth='16' /></address-map></value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>16</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition>]]></parameter> + <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition> + <hdlLibraryName>qsys_lofar2_unb2b_ring_timer_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_timer_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_timer_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>qsys_lofar2_unb2b_ring_timer_0</fileSetName> + <fileSetFixedName>qsys_lofar2_unb2b_ring_timer_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition>]]></parameter> + <parameter name="hlsFile" value="" /> + <parameter name="logicalView">../lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip</parameter> + <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.ALWAYS_RUN</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.COUNTER_SIZE</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FIXED_PERIOD</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.FREQ</key> + <value>100000000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.LOAD_VALUE</key> + <value>99999</value> + </entry> + <entry> + <key>embeddedsw.CMacro.MULT</key> + <value>0.001</value> + </entry> + <entry> + <key>embeddedsw.CMacro.PERIOD</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.PERIOD_UNITS</key> + <value>ms</value> + </entry> + <entry> + <key>embeddedsw.CMacro.RESET_OUTPUT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SNAPSHOT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TICKS_PER_SEC</key> + <value>1000</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition>]]></parameter> + <parameter name="svInterfaceDefinition" value="" /> + </module> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="jtag_uart_0.avalon_jtag_slave"> + <parameter name="baseAddress" value="0x3500" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="cpu_0.debug_mem_slave"> + <parameter name="baseAddress" value="0x3800" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_unb_sens.mem"> + <parameter name="baseAddress" value="0x3100" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="rom_system_info.mem"> + <parameter name="baseAddress" value="0x00010000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="pio_system_info.mem"> + <parameter name="baseAddress" value="0x0000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="pio_pps.mem"> + <parameter name="baseAddress" value="0x34d0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_wdi.mem"> + <parameter name="baseAddress" value="0x3000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_remu.mem"> + <parameter name="baseAddress" value="0x34a0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_epcs.mem"> + <parameter name="baseAddress" value="0x3480" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dpmm_ctrl.mem"> + <parameter name="baseAddress" value="0x34f8" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dpmm_data.mem"> + <parameter name="baseAddress" value="0x34f0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_mmdp_ctrl.mem"> + <parameter name="baseAddress" value="0x34e8" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_mmdp_data.mem"> + <parameter name="baseAddress" value="0x34e0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_fpga_temp_sens.mem"> + <parameter name="baseAddress" value="0x3460" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_unb_pmbus.mem"> + <parameter name="baseAddress" value="0x0100" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_fpga_voltage_sens.mem"> + <parameter name="baseAddress" value="0x3400" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="ram_scrap.mem"> + <parameter name="baseAddress" value="0x0800" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_bsn_monitor_v2_ring_rx.mem"> + <parameter name="baseAddress" value="0x3200" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_bsn_monitor_v2_ring_tx.mem"> + <parameter name="baseAddress" value="0x0600" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dp_xonoff_lane.mem"> + <parameter name="baseAddress" value="0x30c0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dp_xonoff_local.mem"> + <parameter name="baseAddress" value="0x3080" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dp_block_validate_err.mem"> + <parameter name="baseAddress" value="0x0400" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_dp_block_validate_bsn_at_sync.mem"> + <parameter name="baseAddress" value="0x3040" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_ring_info.mem"> + <parameter name="baseAddress" value="0x34c0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_tr_10gbe_mac.mem"> + <parameter name="baseAddress" value="0x8000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_tr_10gbe_eth10g.mem"> + <parameter name="baseAddress" value="0x3008" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_ring_lane_info.mem"> + <parameter name="baseAddress" value="0x00c0" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="reg_diag_bg.mem"> + <parameter name="baseAddress" value="0x3020" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="ram_diag_bg.mem"> + <parameter name="baseAddress" value="0x0200" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="avs_eth_0.mms_ram"> + <parameter name="baseAddress" value="0x2000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="avs_eth_0.mms_reg"> + <parameter name="baseAddress" value="0x0080" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="avs_eth_0.mms_tse"> + <parameter name="baseAddress" value="0x1000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="onchip_memory2_0.s1"> + <parameter name="baseAddress" value="0x00020000" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="pio_wdi.s1"> + <parameter name="baseAddress" value="0x3010" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.data_master" + end="timer_0.s1"> + <parameter name="baseAddress" value="0x3440" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.instruction_master" + end="cpu_0.debug_mem_slave"> + <parameter name="baseAddress" value="0x3800" /> + </connection> + <connection + kind="avalon" + version="18.0" + start="cpu_0.instruction_master" + end="onchip_memory2_0.s1"> + <parameter name="baseAddress" value="0x00020000" /> + </connection> + <connection kind="clock" version="18.0" start="clk_0.clk" end="jtag_uart_0.clk" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="pio_wdi.clk" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="timer_0.clk" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="cpu_0.clk" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="onchip_memory2_0.clk1" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="avs_eth_0.mm" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_unb_sens.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="rom_system_info.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="pio_system_info.system" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="pio_pps.system" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_wdi.system" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_remu.system" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="reg_epcs.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dpmm_ctrl.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_mmdp_data.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dpmm_data.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_mmdp_ctrl.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_fpga_temp_sens.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_unb_pmbus.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_fpga_voltage_sens.system" /> + <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_scrap.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_bsn_monitor_v2_ring_rx.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_bsn_monitor_v2_ring_tx.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_ring_lane_info.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dp_xonoff_lane.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dp_xonoff_local.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dp_block_validate_err.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_dp_block_validate_bsn_at_sync.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_ring_info.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_tr_10gbe_mac.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_tr_10gbe_eth10g.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="reg_diag_bg.system" /> + <connection + kind="clock" + version="18.0" + start="clk_0.clk" + end="ram_diag_bg.system" /> + <connection + kind="interrupt" + version="18.0" + start="cpu_0.irq" + end="avs_eth_0.interrupt" /> + <connection + kind="interrupt" + version="18.0" + start="cpu_0.irq" + end="jtag_uart_0.irq"> + <parameter name="irqNumber" value="1" /> + </connection> + <connection kind="interrupt" version="18.0" start="cpu_0.irq" end="timer_0.irq"> + <parameter name="irqNumber" value="2" /> + </connection> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="avs_eth_0.mm_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="jtag_uart_0.reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="pio_wdi.reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="timer_0.reset" /> + <connection kind="reset" version="18.0" start="clk_0.clk_reset" end="cpu_0.reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="onchip_memory2_0.reset1" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_unb_sens.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="rom_system_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="pio_system_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="pio_pps.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_wdi.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_remu.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_epcs.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dpmm_ctrl.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_mmdp_data.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_mmdp_ctrl.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dpmm_data.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_fpga_temp_sens.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_unb_pmbus.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_fpga_voltage_sens.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="ram_scrap.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_bsn_monitor_v2_ring_rx.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_bsn_monitor_v2_ring_tx.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_ring_lane_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dp_xonoff_local.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dp_block_validate_err.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dp_block_validate_bsn_at_sync.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_ring_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_tr_10gbe_mac.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_tr_10gbe_eth10g.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_dp_xonoff_lane.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="reg_diag_bg.system_reset" /> + <connection + kind="reset" + version="18.0" + start="clk_0.clk_reset" + end="ram_diag_bg.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="avs_eth_0.mm_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="jtag_uart_0.reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="pio_wdi.reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="timer_0.reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="cpu_0.reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="onchip_memory2_0.reset1" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_unb_sens.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="rom_system_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="pio_system_info.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="pio_pps.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_wdi.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_remu.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_epcs.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_dpmm_ctrl.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_mmdp_data.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_dpmm_data.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_mmdp_ctrl.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_fpga_temp_sens.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_unb_pmbus.system_reset" /> + <connection + kind="reset" + version="18.0" + start="cpu_0.debug_reset_request" + end="reg_fpga_voltage_sens.system_reset" /> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" /> +</system> diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..44153f43a312914a79f42322622e0acb776de660 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg @@ -0,0 +1,76 @@ +hdl_lib_name = lofar2_unb2b_ring_full +hdl_library_clause_name = lofar2_unb2b_ring_full_lib +hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_ring +hdl_lib_uses_sim = eth +hdl_lib_technology = ip_arria10_e1sg + + synth_files = + lofar2_unb2b_ring_full.vhd + +test_bench_files = + +regression_test_vhdl = + +[modelsim_project_file] +modelsim_copy_files = + +[quartus_project_file] +synth_top_level_entity = + +quartus_copy_files = + # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../ + ../../quartus . + +quartus_qsf_files = + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf + +# use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz. +quartus_sdc_files = + ../../quartus/lofar2_unb2b_ring.sdc + #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc + +quartus_tcl_files = + ../../quartus/lofar2_unb2b_ring_pins.tcl + +quartus_vhdl_files = + +quartus_qip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_full/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip + +quartus_ip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip + +nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2 diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f8bf762841a19cd05b0abd6f2b4bba258061acd0 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author : R. van der Walle +-- Purpose: +-- Wrapper for Lofar2 SDP ring full design +-- Description: +-- Unb2b version for lab testing +-- Contains complete ring design with all 8 lanes. + + +LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE diag_lib.diag_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; + +ENTITY lofar2_unb2b_ring_full IS + GENERIC ( + g_design_name : STRING := "lofar2_unb2b_ring_full"; + g_design_note : STRING := "Lofar2 Ring full design"; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := "" -- revision ID -- set by QSF + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + -- Transceiver clocks + SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines + + -- front transceivers + QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0'); + QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0); + + -- ring transceivers + RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces + RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + + -- LEDs + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) + + ); +END lofar2_unb2b_ring_full; + +ARCHITECTURE str OF lofar2_unb2b_ring_full IS +BEGIN + + u_revision : ENTITY lofar2_unb2b_ring_lib.lofar2_unb2b_ring + GENERIC MAP ( + g_design_name => g_design_name, + g_design_note => g_design_note, + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id + ) + PORT MAP ( + -- GENERAL + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + + -- I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + -- 1GbE Control Interface + ETH_clk => ETH_clk, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => QSFP_0_RX, + QSFP_0_TX => QSFP_0_TX, + + -- ring transceivers + RING_0_RX => RING_0_RX, + RING_0_TX => RING_0_TX, + RING_1_RX => RING_1_RX, + RING_1_TX => RING_1_TX, + + -- LEDs + QSFP_LED => QSFP_LED + ); + +END str; diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..68e36f783e66c851947adced910b1d78875e8d4b --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg @@ -0,0 +1,76 @@ +hdl_lib_name = lofar2_unb2b_ring_one +hdl_library_clause_name = lofar2_unb2b_ring_one_lib +hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_ring +hdl_lib_uses_sim = eth +hdl_lib_technology = ip_arria10_e1sg + + synth_files = + lofar2_unb2b_ring_one.vhd + +test_bench_files = + +regression_test_vhdl = + +[modelsim_project_file] +modelsim_copy_files = + +[quartus_project_file] +synth_top_level_entity = + +quartus_copy_files = + # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../ + ../../quartus . + +quartus_qsf_files = + $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf + +# use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz. +quartus_sdc_files = + ../../quartus/lofar2_unb2b_ring.sdc + #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc + +quartus_tcl_files = + ../../quartus/lofar2_unb2b_ring_pins.tcl + +quartus_vhdl_files = + +quartus_qip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_one/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip + +quartus_ip_files = + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip + $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip + +nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2 diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2fad382539de10c0df977920b185f23998e50581 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd @@ -0,0 +1,155 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +-- Author : R. van der Walle +-- Purpose: +-- Wrapper for Lofar2 SDP ring one design +-- Description: +-- Unb2b version for lab testing +-- Contains ring design with 1 lane. +-- Remark: +-- Note that the amount of transceivers support 2 lanes, one even and one odd. +-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even). + + +LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE diag_lib.diag_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; + +ENTITY lofar2_unb2b_ring_one IS + GENERIC ( + g_design_name : STRING := "lofar2_unb2b_ring_one"; + g_design_note : STRING := "Lofar2 Ring one design"; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := "" -- revision ID -- set by QSF + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + -- Transceiver clocks + SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines + + -- front transceivers + QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0'); + QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0); + + -- ring transceivers + RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces + RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + + -- LEDs + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) + + ); +END lofar2_unb2b_ring_one; + +ARCHITECTURE str OF lofar2_unb2b_ring_one IS +BEGIN + + u_revision : ENTITY lofar2_unb2b_ring_lib.lofar2_unb2b_ring + GENERIC MAP ( + g_design_name => g_design_name, + g_design_note => g_design_note, + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id + ) + PORT MAP ( + -- GENERAL + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + + -- Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + + -- I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + -- 1GbE Control Interface + ETH_clk => ETH_clk, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT, + + -- Transceiver clocks + SA_CLK => SA_CLK, + + -- front transceivers + QSFP_0_RX => QSFP_0_RX, + QSFP_0_TX => QSFP_0_TX, + + -- ring transceivers + RING_0_RX => RING_0_RX, + RING_0_TX => RING_0_TX, + RING_1_RX => RING_1_RX, + RING_1_TX => RING_1_TX, + + -- LEDs + QSFP_LED => QSFP_LED + ); + +END str; diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a49266604eea6edbb357f3a052c731f96e46d6dc --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd @@ -0,0 +1,994 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Author : R vd Walle +-- Purpose: +-- Design for Lofar2 Ring interface testing. +-- Description: +-- Unb2b version for lab testing, see https://support.astron.nl/confluence/x/jyu7Ag. +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_network_layers_pkg.ALL; +USE common_lib.common_field_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL; +USE diag_lib.diag_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE wpfb_lib.wpfb_pkg.ALL; +USE lofar2_sdp_lib.sdp_pkg.ALL; +USE work.lofar2_unb2b_ring_pkg.ALL; +USE eth_lib.eth_pkg.ALL; +USE ring_lib.ring_pkg.ALL; + + +ENTITY lofar2_unb2b_ring IS + GENERIC ( + g_design_name : STRING := "lofar2_unb2b_ring"; + g_design_note : STRING := "UNUSED"; + g_technology : NATURAL := c_tech_arria10_e1sg; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := ""; -- revision ID -- set by QSF + g_factory_image : BOOLEAN := FALSE; + g_protect_addr_range : BOOLEAN := FALSE + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + -- Transceiver clocks + SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines + -- front transceivers QSFP1 for 10GbE output to CEP. + QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0'); + QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0); + + -- ring transceivers + RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces + RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0); + + -- LEDs + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0) + + ); +END lofar2_unb2b_ring; + + +ARCHITECTURE str OF lofar2_unb2b_ring IS + + -- Revision parameters + CONSTANT c_revision_select : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name); + CONSTANT c_nof_lanes : c_revision_select.N_ring_lanes; + -- Firmware version x.y + CONSTANT c_fw_version : t_unb2b_board_fw_version := (2, 0); + CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M; + CONSTANT c_lofar2_sample_clk_freq : NATURAL := c_sdp_f_adc_MHz * 10**6; -- fixed 200 MHz for LOFAR2.0 stage 1 + + -- QSFP + CONSTANT c_nof_qsfp_bus : NATURAL := 1; + CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus; --4 + + -- RING + CONSTANT c_nof_ring_bus : NATURAL := 2; + CONSTANT c_ring_bus_w : NATURAL := 4; --Using 4 phisically, there are 12 + CONSTANT c_nof_streams_ring : NATURAL := c_ring_bus_w*c_nof_ring_bus; --c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8 + + -- 10GbE + CONSTANT c_nof_even_lanes : NATURAL := ceil_div(c_nof_lanes, 2); -- nof lanes transmitting in positive direction. Using ceil_div as c_nof_lanes might be odd. + CONSTANT c_nof_odd_lanes : NATURAL := c_nof_lanes / 2; -- nof lanes transmitting in negative direction. + CONSTANT c_nof_mac : NATURAL := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48 + + CONSTANT c_lane_data_w : NATURAL := 64; + CONSTANT c_lane_packet_length : NATURAL := 1024; + CONSTANT c_use_dp_layer : BOOLEAN := TRUE; + CONSTANT c_nof_rx_monitors : NATURAL := 1; + CONSTANT c_nof_tx_monitors : NATURAL := 1; + CONSTANT c_err_bi : NATURAL := 0; + CONSTANT c_nof_err_counts : NATURAL := 8; + CONSTANT c_validate_err_fifo_size : NATURAL := 1536; + CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1; + CONSTANT c_validate_channel : BOOLEAN := TRUE; + CONSTANT c_validate_channel_mode : STRING := "="; + CONSTANT c_fifo_tx_fill : NATURAL := c_lane_packet_length; + CONSTANT c_fifo_tx_size : NATURAL := 2 * c_lane_packet_length; + + CONSTANT c_addr_w_reg_ring_lane_info : NATURAL := 1; + CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx : NATURAL := ceil_log2(c_nof_rx_monitors) + 3; + CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_tx : NATURAL := ceil_log2(c_nof_tx_monitors) + 3; + CONSTANT c_addr_w_reg_dp_block_validate_err : NATURAL := ceil_log2(c_nof_err_counts + 3); + CONSTANT c_addr_w_reg_dp_block_validate_bsn_at_sync : NATURAL := ceil_log2(3); + + SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + + -- System + SIGNAL cs_sim : STD_LOGIC; + SIGNAL xo_ethclk : STD_LOGIC; + SIGNAL xo_rst : STD_LOGIC; + SIGNAL xo_rst_n : STD_LOGIC; + SIGNAL mm_clk : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC := '0'; + + SIGNAL dp_pps : STD_LOGIC; + SIGNAL dp_rst : STD_LOGIC; + SIGNAL dp_clk : STD_LOGIC; + + -- PIOs + SIGNAL pout_wdi : STD_LOGIC; + + -- WDI override + SIGNAL reg_wdi_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- PPSH + SIGNAL reg_ppsh_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- UniBoard system info + SIGNAL reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- UniBoard I2C sens + SIGNAL reg_unb_sens_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_unb_sens_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- pm bus + SIGNAL reg_unb_pmbus_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_unb_pmbus_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- FPGA sensors + SIGNAL reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- eth1g + SIGNAL eth1g_mm_rst : STD_LOGIC; + SIGNAL eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers + SIGNAL eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers + SIGNAL eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt + SIGNAL eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory + SIGNAL eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- EPCS read + SIGNAL reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- EPCS write + SIGNAL reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- EPCS status/control + SIGNAL reg_epcs_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- Remote Update + SIGNAL reg_remu_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst; + + -- Scrap ram + SIGNAL ram_scrap_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst; + + ---------------------------------------------- + -- 10 GbE + ---------------------------------------------- + SIGNAL reg_tr_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_tr_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst; + + + SIGNAL reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst; + SIGNAL ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_ring_lane_info_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_ring_lane_info_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_bsn_monitor_v2_ring_rx_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_bsn_monitor_v2_ring_rx_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_bsn_monitor_v2_ring_tx_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_bsn_monitor_v2_ring_tx_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_dp_block_validate_err_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dp_block_validate_err_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_dp_block_validate_bsn_at_sync_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_dp_block_validate_bsn_at_sync_cipo : t_mem_cipo := c_mem_cipo_rst; + + SIGNAL reg_ring_lane_info_copi_arr : t_mem_copi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst); + SIGNAL reg_ring_lane_info_cipo_arr : t_mem_cipo_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst); + SIGNAL reg_bsn_monitor_v2_ring_rx_copi_arr : t_mem_copi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst); + SIGNAL reg_bsn_monitor_v2_ring_rx_cipo_arr : t_mem_cipo_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst); + SIGNAL reg_bsn_monitor_v2_ring_tx_copi_arr : t_mem_copi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst); + SIGNAL reg_bsn_monitor_v2_ring_tx_cipo_arr : t_mem_cipo_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst); + SIGNAL reg_dp_block_validate_err_copi_arr : t_mem_copi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst); + SIGNAL reg_dp_block_validate_err_cipo_arr : t_mem_cipo_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst); + SIGNAL reg_dp_block_validate_bsn_at_sync_copi_arr : t_mem_copi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst); + SIGNAL reg_dp_block_validate_bsn_at_sync_cipo_arr : t_mem_cipo_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst); + + SIGNAL from_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL to_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + + SIGNAL dp_mux_snk_out_2arr : t_dp_siso_2arr_2(c_nof_lanes-1 DOWNTO 0); + SIGNAL dp_mux_snk_in_2arr : t_dp_sosi_2arr_2(c_nof_lanes-1 DOWNTO 0); + + SIGNAL dp_xonoff_lane_src_out_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL dp_xonoff_lane_src_in_arr : t_dp_siso_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + + SIGNAL lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_tx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_tx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_rx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_rx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_tx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL lane_tx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + + SIGNAL tr_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL tr_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + + + SIGNAL bs_sosi : t_dp_sosi := c_dp_sosi_rst; + SIGNAL local_sosi : t_dp_sosi := c_dp_sosi_rst; + + SIGNAL ring_info : t_ring_info; + + -- 10GbE + SIGNAL tr_ref_clk_312 : STD_LOGIC; + SIGNAL tr_ref_clk_156 : STD_LOGIC; + SIGNAL tr_ref_rst_156 : STD_LOGIC; + SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0')); + SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0')); + SIGNAL i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0')); + SIGNAL i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0')); + + + SIGNAL tr_10gbe_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL tr_10gbe_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0); + SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0); + + -- QSFP LEDS + SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + + SIGNAL unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); + SIGNAL unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + +BEGIN + + ----------------------------------------------------------------------------- + -- General control function + ----------------------------------------------------------------------------- + u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board + GENERIC MAP ( + g_sim => g_sim, + g_technology => g_technology, + g_design_name => g_design_name, + g_design_note => g_design_note, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id, + g_fw_version => c_fw_version, + g_mm_clk_freq => c_mm_clk_freq, + g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, + g_aux => c_unb2b_board_aux, + g_factory_image => g_factory_image, + g_protect_addr_range => g_protect_addr_range, + g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M, + g_dp_clk_use_pll => FALSE, + g_udp_offload => TRUE, + g_udp_offload_nof_streams => c_eth_nof_udp_ports + ) + PORT MAP ( + -- Clock an reset signals + cs_sim => cs_sim, + xo_ethclk => xo_ethclk, + xo_rst => xo_rst, + xo_rst_n => xo_rst_n, + + mm_clk => mm_clk, + mm_rst => mm_rst, + + dp_rst => dp_rst, + dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated + dp_pps => dp_pps, + dp_rst_in => dp_rst, + dp_clk_in => dp_clk, + + this_chip_id => this_chip_id, + this_bck_id => this_bck_id, + + -- Toggle WDI + pout_wdi => pout_wdi, + + -- MM buses + -- REMU + reg_remu_mosi => reg_remu_copi, + reg_remu_miso => reg_remu_cipo, + + -- EPCS read + reg_dpmm_data_mosi => reg_dpmm_data_copi, + reg_dpmm_data_miso => reg_dpmm_data_cipo, + reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi, + reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo, + + -- EPCS write + reg_mmdp_data_mosi => reg_mmdp_data_copi, + reg_mmdp_data_miso => reg_mmdp_data_cipo, + reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi, + reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo, + + -- EPCS status/control + reg_epcs_mosi => reg_epcs_copi, + reg_epcs_miso => reg_epcs_cipo, + + -- . Manual WDI override + reg_wdi_mosi => reg_wdi_copi, + reg_wdi_miso => reg_wdi_cipo, + + -- . System_info + reg_unb_system_info_mosi => reg_unb_system_info_copi, + reg_unb_system_info_miso => reg_unb_system_info_cipo, + rom_unb_system_info_mosi => rom_unb_system_info_copi, + rom_unb_system_info_miso => rom_unb_system_info_cipo, + + -- . UniBoard I2C sensors + reg_unb_sens_mosi => reg_unb_sens_copi, + reg_unb_sens_miso => reg_unb_sens_cipo, + + -- . FPGA sensors + reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi, + reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo, + reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi, + reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo, + + reg_unb_pmbus_mosi => reg_unb_pmbus_copi, + reg_unb_pmbus_miso => reg_unb_pmbus_cipo, + + -- . PPSH + reg_ppsh_mosi => reg_ppsh_copi, + reg_ppsh_miso => reg_ppsh_cipo, + + -- eth1g + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_copi, + eth1g_tse_miso => eth1g_tse_cipo, + eth1g_reg_mosi => eth1g_reg_copi, + eth1g_reg_miso => eth1g_reg_cipo, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_copi, + eth1g_ram_miso => eth1g_ram_cipo, + + ram_scrap_mosi => ram_scrap_copi, + ram_scrap_miso => ram_scrap_cipo, + + -- FPGA pins + -- . General + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + -- . Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + -- . I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + -- PM bus + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + -- . 1GbE Control Interface + ETH_clk => ETH_CLK, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT + ); + + ----------------------------------------------------------------------------- + -- MM controller + ----------------------------------------------------------------------------- + u_mmc : ENTITY work.mmc_lofar2_unb2b_ring + GENERIC MAP ( + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr + ) + PORT MAP( + mm_rst => mm_rst, + mm_clk => mm_clk, + + -- PIOs + pout_wdi => pout_wdi, + + -- mm interfaces for control + reg_wdi_copi => reg_wdi_copi, + reg_wdi_cipo => reg_wdi_cipo, + reg_unb_system_info_copi => reg_unb_system_info_copi, + reg_unb_system_info_cipo => reg_unb_system_info_cipo, + rom_unb_system_info_copi => rom_unb_system_info_copi, + rom_unb_system_info_cipo => rom_unb_system_info_cipo, + reg_unb_sens_copi => reg_unb_sens_copi, + reg_unb_sens_cipo => reg_unb_sens_cipo, + reg_unb_pmbus_copi => reg_unb_pmbus_copi, + reg_unb_pmbus_cipo => reg_unb_pmbus_cipo, + reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi, + reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo, + reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi, + reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo, + reg_ppsh_copi => reg_ppsh_copi, + reg_ppsh_cipo => reg_ppsh_cipo, + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_copi => eth1g_tse_copi, + eth1g_tse_cipo => eth1g_tse_cipo, + eth1g_reg_copi => eth1g_reg_copi, + eth1g_reg_cipo => eth1g_reg_cipo, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_copi => eth1g_ram_copi, + eth1g_ram_cipo => eth1g_ram_cipo, + reg_dpmm_data_copi => reg_dpmm_data_copi, + reg_dpmm_data_cipo => reg_dpmm_data_cipo, + reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi, + reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo, + reg_mmdp_data_copi => reg_mmdp_data_copi, + reg_mmdp_data_cipo => reg_mmdp_data_cipo, + reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi, + reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo, + reg_epcs_copi => reg_epcs_copi, + reg_epcs_cipo => reg_epcs_cipo, + reg_remu_copi => reg_remu_copi, + reg_remu_cipo => reg_remu_cipo, + reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi, + reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo, + reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi, + reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo, + reg_diag_bg_copi => reg_diag_bg_copi, + reg_diag_bg_cipo => reg_diag_bg_cipo, + ram_diag_bg_copi => ram_diag_bg_copi, + ram_diag_bg_cipo => ram_diag_bg_cipo, + reg_ring_lane_info_copi => reg_ring_lane_info_copi, + reg_ring_lane_info_cipo => reg_ring_lane_info_cipo, + reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi, + reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo, + reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi, + reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo, + reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi, + reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo, + reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi, + reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo, + reg_ring_info_copi => reg_ring_info_copi, + reg_ring_info_cipo => reg_ring_info_cipo, + reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi, + reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo, + reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi, + reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo, + ram_scrap_copi => ram_scrap_copi, + ram_scrap_cipo => ram_scrap_cipo + ); + + ----------------------------------------------------------------------------- + -- MM Mux + ----------------------------------------------------------------------------- + u_mem_mux_ring_lane_info_info : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => c_nof_lanes, + g_mult_addr_w => c_addr_w_reg_ring_lane_info + ) + PORT MAP ( + mosi => reg_ring_lane_info_copi, + miso => reg_ring_lane_info_cipo, + mosi_arr => reg_ring_lane_info_copi_arr, + miso_arr => reg_ring_lane_info_cipo_arr + ); + + u_mem_mux_bsn_monitor_v2_ring_rx_info : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => c_nof_lanes, + g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx + ) + PORT MAP ( + mosi => reg_bsn_monitor_v2_ring_rx_copi, + miso => reg_bsn_monitor_v2_ring_rx_cipo, + mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr, + miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr + ); + + u_mem_mux_bsn_monitor_v2_ring_tx_info : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => c_nof_lanes, + g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx + ) + PORT MAP ( + mosi => reg_bsn_monitor_v2_ring_tx_copi, + miso => reg_bsn_monitor_v2_ring_tx_cipo, + mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr, + miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr + ); + + u_mem_mux_dp_block_validate_err_info : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => c_nof_lanes, + g_mult_addr_w => c_addr_w_reg_dp_block_validate_err + ) + PORT MAP ( + mosi => reg_dp_block_validate_err_copi, + miso => reg_dp_block_validate_err_cipo, + mosi_arr => reg_dp_block_validate_err_copi_arr, + miso_arr => reg_dp_block_validate_err_cipo_arr + ); + + u_mem_mux_dp_block_validate_bsn_at_sync_info : ENTITY common_lib.common_mem_mux + GENERIC MAP ( + g_nof_mosi => c_nof_lanes, + g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync + ) + PORT MAP ( + mosi => reg_dp_block_validate_bsn_at_sync_copi, + miso => reg_dp_block_validate_bsn_at_sync_cipo, + mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr, + miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr + ); + + ----------------------------------------------------------------------------- + -- MMP diag_block_gen + ----------------------------------------------------------------------------- + u_mmp_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + en_sync => dp_pps, + + reg_bg_ctrl_mosi => reg_diag_bg_copi, + reg_bg_ctrl_miso => reg_diag_bg_cipo, + ram_bg_data_mosi => ram_diag_bg_copi, + ram_bg_data_miso => ram_diag_bg_cipo, + + out_sosi_arr(0) => local_sosi + ); + bs_sosi <= local_sosi; + + ----------------------------------------------------------------------------- + -- MMP dp_xonoff from_lane_sosi + ----------------------------------------------------------------------------- + u_mmp_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff + GENERIC MAP ( + g_nof_streams => c_nof_lanes, + g_default_value => '0' + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_mosi => reg_dp_xonoff_lane_copi, + reg_miso => reg_dp_xonoff_lane_cipo, + + dp_rst => dp_rst, + dp_clk => dp_clk, + + snk_out_arr => OPEN, + snk_in_arr => from_lane_sosi_arr, + + src_in_arr => dp_xonoff_lane_src_in_arr, + src_out_arr => dp_xonoff_lane_src_out_arr + ); + + ----------------------------------------------------------------------------- + -- MMP dp_xonoff local_sosi + ----------------------------------------------------------------------------- + gen_copy_local: FOR I IN 0 TO c_nof_lanes -1 GENERATE + dp_xonoff_local_snk_in_arr(I) <= local_sosi; -- copy local sosi to all lanes + END GENERATE; + + u_mmp_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff + GENERIC MAP ( + g_nof_streams => c_nof_lanes, + g_default_value => '0' + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_mosi => reg_dp_xonoff_local_copi, + reg_miso => reg_dp_xonoff_local_cipo, + + dp_rst => dp_rst, + dp_clk => dp_clk, + + snk_out_arr => OPEN, + snk_in_arr => dp_xonoff_local_snk_in_arr, + + src_in_arr => dp_xonoff_local_src_in_arr, + src_out_arr => dp_xonoff_local_src_out_arr + ); + + ----------------------------------------------------------------------------- + -- DP Mux + ----------------------------------------------------------------------------- + gen_dp_mux: FOR I IN 0 TO c_nof_lanes -1 GENERATE + + dp_xonoff_lane_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(0); + dp_xonoff_local_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(1); + dp_mux_snk_in_2arr(I)(0) <= dp_xonoff_lane_src_out_arr(I); + dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I); + + u_dp_mux : ENTITY dp_lib.dp_mux + GENERIC MAP ( + g_append_channel_lo => FALSE, + g_sel_ctrl_invert => TRUE + ) + PORT MAP ( + rst => dp_rst, + clk => dp_clk, + + snk_out_arr => dp_mux_snk_out_2arr(I), + snk_in_arr => dp_mux_snk_in_2arr(I), + + src_in => c_dp_siso_rdy, + src_out => to_lane_sosi_arr(I) + ); + END GENERATE; + + ----------------------------------------------------------------------------- + -- Ring info + ----------------------------------------------------------------------------- + u_ring_info : ENTITY ring_lib.ring_info + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + + dp_clk => dp_clk, + dp_rst => dp_rst, + + reg_copi => reg_ring_info_copi, + reg_cipo => reg_ring_info_cipo, + + ring_info => ring_info + ); + this_rn <= TO_UVEC(TO_UINT(ID) - TO_UINT(ring_info.O_rn), c_byte_w); + + ----------------------------------------------------------------------------- + -- Ring lane even indices. + ----------------------------------------------------------------------------- + gen_even_lanes: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE + u_ring_lane : ENTITY ring_lib.ring_lane + GENERIC MAP ( + g_lane_direction => 1, -- transport in positive direction. + g_lane_data_w => c_lane_data_w, + g_lane_packet_length => c_lane_packet_length, + g_use_dp_layer => c_use_dp_layer, + g_nof_rx_monitors => c_nof_rx_monitors, + g_nof_tx_monitors => c_nof_tx_monitors, + g_err_bi => c_err_bi, + g_nof_err_counts => c_nof_err_counts, + g_validate_err_fifo_size => c_validate_err_fifo_size, + g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel, + g_validate_channel => c_validate_channel, + g_validate_channel_mode => c_validate_channel_mode + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_clk => dp_clk, + dp_rst => dp_rst, + + from_lane_sosi => from_lane_sosi_arr(2*I), -- even indices + to_lane_sosi => to_lane_sosi_arr(2*I), + lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I), + lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I), + lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I), + lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I), + bs_sosi => bs_sosi, + + reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2*I), + reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2*I), + reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2*I), + reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2*I), + reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2*I), + reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2*I), + reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2*I), + reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2*I), + reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2*I), + reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2*I), + + this_rn => this_rn, + N_rn => ring_info.N_rn, + rx_select => ring_info.rx_select, + tx_select => ring_info.tx_select + ); + END GENERATE; + + ----------------------------------------------------------------------------- + -- Ring lane odd indices. + ----------------------------------------------------------------------------- + gen_odd_lanes : FOR I IN 0 TO c_nof_odd_lanes-1 GENERATE + u_ring_lane : ENTITY ring_lib.ring_lane + GENERIC MAP ( + g_lane_direction => 0, -- transport in negative direction. + g_lane_data_w => c_lane_data_w, + g_lane_packet_length => c_lane_packet_length, + g_use_dp_layer => c_use_dp_layer, + g_nof_rx_monitors => c_nof_rx_monitors, + g_nof_tx_monitors => c_nof_tx_monitors, + g_err_bi => c_err_bi, + g_nof_err_counts => c_nof_err_counts, + g_validate_err_fifo_size => c_validate_err_fifo_size, + g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel, + g_validate_channel => c_validate_channel, + g_validate_channel_mode => c_validate_channel_mode + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_clk => dp_clk, + dp_rst => dp_rst, + + from_lane_sosi => from_lane_sosi_arr(2*I +1), -- odd indices + to_lane_sosi => to_lane_sosi_arr(2*I +1), + lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I), + lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I), + lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I), + lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I), + bs_sosi => bs_sosi, + + reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2*I +1), + reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2*I +1), + reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2*I +1), + reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2*I +1), + reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2*I +1), + reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2*I +1), + reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2*I +1), + reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2*I +1), + reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2*I +1), + reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2*I +1), + + this_rn => this_rn, + N_rn => ring_info.N_rn, + rx_select => ring_info.tx_select, -- reverse tx/rx select for odd indices + tx_select => ring_info.rx_select + ); + END GENERATE; + + ----------------------------------------------------------------------------- + -- Combine seperate signals into array for tr_10GbE + ----------------------------------------------------------------------------- + gen_combine: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE + -- QSFP_RX + lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I) WHEN ring_info.rx_select = '1' ELSE c_dp_sosi_rst; -- rx_select=1 -> even lanes receive from cable + lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I) WHEN ring_info.tx_select = '1' ELSE c_dp_sosi_rst; -- tx_select=1 -> odd lanes receive from cable + -- QSFP_TX + tr_10gbe_snk_in_arr(3*I) <= lane_tx_cable_even_sosi_arr(I) WHEN ring_info.tx_select = '1' ELSE -- tx_select=1 -> even lanes transmit to cable + lane_tx_cable_odd_sosi_arr(I) WHEN ring_info.rx_select = '1' ELSE c_dp_sosi_rst; -- rx_select=1 -> odd lanes transmit to cable + + -- RING_0_RX even lanes receive from RING_0 (from the left) + lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I +1); + -- RING_0_TX odd lanes transmit to RING_0 (to the left) + tr_10gbe_snk_in_arr(3*I +1) <= lane_tx_board_odd_sosi_arr(I); + + -- RING_1_RX odd lanes receive from RING_1 (from the right) + lane_rx_board_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I +2); + -- RING_1_TX even lanes transmit to RING_1 (to the right) + tr_10gbe_snk_in_arr(3*I +2) <= lane_tx_board_odd_sosi_arr(I); + END GENERATE; + + ----------------------------------------------------------------------------- + -- tr_10GbE + ----------------------------------------------------------------------------- + u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE + GENERIC MAP ( + g_sim => g_sim, + g_sim_level => 1, + g_nof_macs => c_nof_mac, + g_direction => "TX_RX", + g_tx_fifo_fill => c_fifo_tx_fill, + g_tx_fifo_size => c_fifo_tx_size + ) + PORT MAP ( + -- Transceiver PLL reference clock + tr_ref_clk_644 => SA_CLK, + tr_ref_clk_312 => tr_ref_clk_312, + tr_ref_clk_156 => tr_ref_clk_156, + tr_ref_rst_156 => tr_ref_rst_156, + + -- MM interface + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_mac_mosi => reg_tr_10GbE_mac_copi, + reg_mac_miso => reg_tr_10GbE_mac_cipo, + + reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi, + reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo, + + -- DP interface + dp_rst => dp_rst, + dp_clk => dp_clk, + + src_out_arr => tr_10gbe_src_out_arr, + src_in_arr => tr_10gbe_src_in_arr, + + snk_out_arr => tr_10gbe_snk_out_arr, + snk_in_arr => tr_10gbe_snk_in_arr, + + -- Serial IO + serial_tx_arr => tr_10gbe_serial_tx_arr, + serial_rx_arr => tr_10gbe_serial_rx_arr + ); + + + ----------------------------------------------------------------------------- + -- Seperate serial tx/rx array + ----------------------------------------------------------------------------- + -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays: + -- QSFP port, RING_0 port and RING_1 port. + gen_seperate: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE + -- QSFP_TX + unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(3*I); + -- QSFP_RX + tr_10gbe_serial_rx_arr(3*I) <= unb2_board_front_io_serial_rx_arr(I); + + -- RING_0_TX + i_RING_TX(0)(I) <= tr_10gbe_serial_tx_arr(3*I +1); + -- RING_0_RX + tr_10gbe_serial_rx_arr(3*I +1) <= i_RING_RX(0)(I); + + -- RING_1_TX + i_RING_TX(1)(I) <= tr_10gbe_serial_tx_arr(3*I +2); + -- RING_1_RX + tr_10gbe_serial_rx_arr(3*I +2) <= i_RING_RX(1)(I); + END GENERATE; + + --------- + -- PLL + --------- + u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks + GENERIC MAP ( + g_technology => g_technology + ) + PORT MAP ( + refclk_644 => SA_CLK, + rst_in => mm_rst, + clk_156 => tr_ref_clk_156, + clk_312 => tr_ref_clk_312, + rst_156 => tr_ref_rst_156, + rst_312 => OPEN + ); + + ------------ + -- Front IO + ------------ + -- put the QSFP_TX/RX ports into arrays + i_QSFP_RX(0) <= QSFP_0_RX; + QSFP_0_TX <= i_QSFP_TX(0); + + u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io + GENERIC MAP ( + g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus + ) + PORT MAP ( + serial_tx_arr => unb2_board_front_io_serial_tx_arr, + serial_rx_arr => unb2_board_front_io_serial_rx_arr, + + green_led_arr => qsfp_green_led_arr, + red_led_arr => qsfp_red_led_arr, + + QSFP_RX => i_QSFP_RX, + QSFP_TX => i_QSFP_TX, + + QSFP_LED => QSFP_LED + ); + + ------------ + -- RING IO + ------------ + i_RING_RX(0) <= RING_0_RX; + i_RING_RX(1) <= RING_1_RX; + RING_0_TX <= i_RING_TX(0); + RING_1_TX <= i_RING_TX(1); + + ------------ + -- LEDs + ------------ + unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0); + u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds + GENERIC MAP ( + g_sim => g_sim, + g_factory_image => g_factory_image, + g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus, + g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period + ) + PORT MAP ( + rst => mm_rst, + clk => mm_clk, + green_led_arr => qsfp_green_led_arr, + red_led_arr => qsfp_red_led_arr, + + tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr + ); + +END str; diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a29810f9731648d6064292ef758d2777479a1bc3 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd @@ -0,0 +1,59 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; + +PACKAGE lofar2_unb2b_ring_pkg IS + + ----------------------------------------------------------------------------- + -- Revision control + ----------------------------------------------------------------------------- + + TYPE t_lofar2_unb2b_ring_config IS RECORD + N_ring_lanes : NATURAL; + END RECORD; + + CONSTANT c_one : t_lofar2_unb2b_ring_config := (1); + CONSTANT c_full : t_lofar2_unb2b_ring_config := (8); + + -- Function to select the revision configuration. + FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_ring_config; + + +END lofar2_unb2b_ring_pkg; + + +PACKAGE BODY lofar2_unb2b_ring_pkg IS + + FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_ring_config IS + BEGIN + IF g_design_name = "lofar2_unb2b_ring_one" THEN RETURN c_one; + ELSE RETURN c_full; + END IF; + END; + + +END lofar2_unb2b_ring_pkg; + diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd new file mode 100644 index 0000000000000000000000000000000000000000..dfc18d9825f75d59cf0244bbf5066b441c7ab2e9 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd @@ -0,0 +1,492 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2020 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL; +USE mm_lib.mm_file_pkg.ALL; +USE mm_lib.mm_file_unb_pkg.ALL; +USE work.qsys_lofar2_unb2b_ring_pkg.ALL; +USE lofar2_sdp_lib.sdp_pkg.ALL; + +ENTITY mmc_lofar2_unb2b_ring IS + GENERIC ( + g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0 + ); + PORT ( + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; + + pout_wdi : OUT STD_LOGIC; + + -- Manual WDI override + reg_wdi_copi : OUT t_mem_copi; + reg_wdi_cipo : IN t_mem_cipo; + + -- system_info + reg_unb_system_info_copi : OUT t_mem_copi; + reg_unb_system_info_cipo : IN t_mem_cipo; + rom_unb_system_info_copi : OUT t_mem_copi; + rom_unb_system_info_cipo : IN t_mem_cipo; + + -- UniBoard I2C sensors + reg_unb_sens_copi : OUT t_mem_copi; + reg_unb_sens_cipo : IN t_mem_cipo; + + reg_fpga_temp_sens_copi : OUT t_mem_copi; + reg_fpga_temp_sens_cipo : IN t_mem_cipo; + reg_fpga_voltage_sens_copi : OUT t_mem_copi; + reg_fpga_voltage_sens_cipo : IN t_mem_cipo; + + reg_unb_pmbus_copi : OUT t_mem_copi; + reg_unb_pmbus_cipo : IN t_mem_cipo; + + -- PPSH + reg_ppsh_copi : OUT t_mem_copi; + reg_ppsh_cipo : IN t_mem_cipo; + + -- eth1g + eth1g_mm_rst : OUT STD_LOGIC; + eth1g_tse_copi : OUT t_mem_copi; + eth1g_tse_cipo : IN t_mem_cipo; + eth1g_reg_copi : OUT t_mem_copi; + eth1g_reg_cipo : IN t_mem_cipo; + eth1g_reg_interrupt : IN STD_LOGIC; + eth1g_ram_copi : OUT t_mem_copi; + eth1g_ram_cipo : IN t_mem_cipo; + + -- EPCS read + reg_dpmm_data_copi : OUT t_mem_copi; + reg_dpmm_data_cipo : IN t_mem_cipo; + reg_dpmm_ctrl_copi : OUT t_mem_copi; + reg_dpmm_ctrl_cipo : IN t_mem_cipo; + + -- EPCS write + reg_mmdp_data_copi : OUT t_mem_copi; + reg_mmdp_data_cipo : IN t_mem_cipo; + reg_mmdp_ctrl_copi : OUT t_mem_copi; + reg_mmdp_ctrl_cipo : IN t_mem_cipo; + + -- EPCS status/control + reg_epcs_copi : OUT t_mem_copi; + reg_epcs_cipo : IN t_mem_cipo; + + -- Remote Update + reg_remu_copi : OUT t_mem_copi; + reg_remu_cipo : IN t_mem_cipo; + + -- BSN Monitor + reg_bsn_monitor_v2_ring_rx_copi : OUT t_mem_copi := c_mem_copi_rst; + reg_bsn_monitor_v2_ring_rx_cipo : IN t_mem_cipo := c_mem_cipo_rst; + + -- BSN Monitor + reg_bsn_monitor_v2_ring_tx_copi : OUT t_mem_copi := c_mem_copi_rst; + reg_bsn_monitor_v2_ring_tx_cipo : IN t_mem_cipo := c_mem_cipo_rst; + + -- BG + reg_diag_bg_copi : OUT t_mem_copi; + reg_diag_bg_cipo : IN t_mem_cipo; + ram_diag_bg_copi : OUT t_mem_copi; + ram_diag_bg_cipo : IN t_mem_cipo; + + -- ring_lane_info + reg_ring_lane_info_copi : OUT t_mem_copi; + reg_ring_lane_info_cipo : IN t_mem_cipo; + + -- Lane xonoff + reg_dp_xonoff_lane_copi : OUT t_mem_copi; + reg_dp_xonoff_lane_cipo : IN t_mem_cipo; + + -- Local xonoff + reg_dp_xonoff_local_copi : OUT t_mem_copi; + reg_dp_xonoff_local_cipo : IN t_mem_cipo; + + -- Local xonoff + reg_dp_block_validate_err_copi : OUT t_mem_copi; + reg_dp_block_validate_err_cipo : IN t_mem_cipo; + + -- Local xonoff + reg_dp_block_validate_bsn_at_sync_copi : OUT t_mem_copi; + reg_dp_block_validate_bsn_at_sync_cipo : IN t_mem_cipo; + + -- ring_info + reg_ring_info_copi : OUT t_mem_copi; + reg_ring_info_cipo : IN t_mem_cipo; + + reg_tr_10GbE_mac_copi : OUT t_mem_copi; + reg_tr_10GbE_mac_cipo : IN t_mem_cipo; + + reg_tr_10GbE_eth10g_copi : OUT t_mem_copi; + reg_tr_10GbE_eth10g_cipo : IN t_mem_cipo; + + -- Scrap ram + ram_scrap_copi : OUT t_mem_copi; + ram_scrap_cipo : IN t_mem_cipo + + ); +END mmc_lofar2_unb2b_ring; + +ARCHITECTURE str OF mmc_lofar2_unb2b_ring IS + + CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr; + CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN"; + + SIGNAL i_reset_n : STD_LOGIC; + + +BEGIN + + ---------------------------------------------------------------------------- + -- MM <-> file I/O for simulation. The files are created in $UPE/sim. + ---------------------------------------------------------------------------- + gen_mm_file_io : IF g_sim = TRUE GENERATE + + u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO") + PORT MAP(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo ); + + u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO") + PORT MAP(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo ); + + u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI") + PORT MAP(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo ); + + u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS") + PORT MAP(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo ); + + u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS") + PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo ); + + u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS") + PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo ); + + u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS") + PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo ); + + u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS") + PORT MAP(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo ); + + -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway. + u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") + PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo ); + + u_mm_file_reg_dp_block_validate_err : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR") + PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo ); + + u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC") + PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo ); + + u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX") + PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo ); + + u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX") + PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo ); + + u_mm_file_reg_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG") + PORT MAP(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo ); + u_mm_file_ram_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG") + PORT MAP(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo ); + + u_mm_file_reg_ring_lane_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO") + PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo ); + + u_mm_file_reg_dp_xonoff_lane : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE") + PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo ); + + u_mm_file_reg_dp_xonoff_local : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL") + PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo ); + + u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO") + PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo); + + u_mm_file_reg_tr_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC") + PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo ); + + u_mm_file_reg_tr_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G") + PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo ); + + u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP") + PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo ); + ---------------------------------------------------------------------------- + -- Procedure that polls a sim control file that can be used to e.g. get + -- the simulation time in ns + ---------------------------------------------------------------------------- + mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat"); + + END GENERATE; + + i_reset_n <= NOT mm_rst; + ---------------------------------------------------------------------------- + -- QSYS for synthesis + ---------------------------------------------------------------------------- + gen_qsys : IF g_sim = FALSE GENERATE + u_qsys : qsys_lofar2_unb2b_ring + PORT MAP ( + + clk_clk => mm_clk, + reset_reset_n => i_reset_n, + + -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board. + pio_wdi_external_connection_export => pout_wdi, + + avs_eth_0_reset_export => eth1g_mm_rst, + avs_eth_0_clk_export => OPEN, + avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0), + avs_eth_0_tse_write_export => eth1g_tse_copi.wr, + avs_eth_0_tse_read_export => eth1g_tse_copi.rd, + avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w-1 DOWNTO 0), + avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w-1 DOWNTO 0), + avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest, + avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0), + avs_eth_0_reg_write_export => eth1g_reg_copi.wr, + avs_eth_0_reg_read_export => eth1g_reg_copi.rd, + avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w-1 DOWNTO 0), + avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w-1 DOWNTO 0), + avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0), + avs_eth_0_ram_write_export => eth1g_ram_copi.wr, + avs_eth_0_ram_read_export => eth1g_ram_copi.rd, + avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w-1 DOWNTO 0), + avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w-1 DOWNTO 0), + avs_eth_0_irq_export => eth1g_reg_interrupt, + + reg_unb_sens_reset_export => OPEN, + reg_unb_sens_clk_export => OPEN, + reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0), + reg_unb_sens_write_export => reg_unb_sens_copi.wr, + reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_unb_sens_read_export => reg_unb_sens_copi.rd, + reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_unb_pmbus_reset_export => OPEN, + reg_unb_pmbus_clk_export => OPEN, + reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0), + reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr, + reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd, + reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_fpga_temp_sens_reset_export => OPEN, + reg_fpga_temp_sens_clk_export => OPEN, + reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0), + reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr, + reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd, + reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_fpga_voltage_sens_reset_export => OPEN, + reg_fpga_voltage_sens_clk_export => OPEN, + reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0), + reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr, + reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd, + reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w-1 DOWNTO 0), + + rom_system_info_reset_export => OPEN, + rom_system_info_clk_export => OPEN, + rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), + rom_system_info_write_export => rom_unb_system_info_copi.wr, + rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0), + rom_system_info_read_export => rom_unb_system_info_copi.rd, + rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0), + + pio_system_info_reset_export => OPEN, + pio_system_info_clk_export => OPEN, + pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), + pio_system_info_write_export => reg_unb_system_info_copi.wr, + pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0), + pio_system_info_read_export => reg_unb_system_info_copi.rd, + pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0), + + pio_pps_reset_export => OPEN, + pio_pps_clk_export => OPEN, + pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0), + pio_pps_write_export => reg_ppsh_copi.wr, + pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w-1 DOWNTO 0), + pio_pps_read_export => reg_ppsh_copi.rd, + pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_wdi_reset_export => OPEN, + reg_wdi_clk_export => OPEN, + reg_wdi_address_export => reg_wdi_copi.address(0 DOWNTO 0), + reg_wdi_write_export => reg_wdi_copi.wr, + reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_wdi_read_export => reg_wdi_copi.rd, + reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_remu_reset_export => OPEN, + reg_remu_clk_export => OPEN, + reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0), + reg_remu_write_export => reg_remu_copi.wr, + reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_remu_read_export => reg_remu_copi.rd, + reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_bsn_monitor_v2_ring_rx_address_export => reg_bsn_monitor_v2_ring_rx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w-1 DOWNTO 0), + reg_bsn_monitor_v2_ring_rx_clk_export => OPEN, + reg_bsn_monitor_v2_ring_rx_read_export => reg_bsn_monitor_v2_ring_rx_copi.rd, + reg_bsn_monitor_v2_ring_rx_readdata_export => reg_bsn_monitor_v2_ring_rx_cipo.rddata(c_word_w-1 DOWNTO 0), + reg_bsn_monitor_v2_ring_rx_reset_export => OPEN, + reg_bsn_monitor_v2_ring_rx_write_export => reg_bsn_monitor_v2_ring_rx_copi.wr, + reg_bsn_monitor_v2_ring_rx_writedata_export => reg_bsn_monitor_v2_ring_rx_copi.wrdata(c_word_w-1 DOWNTO 0), + + reg_bsn_monitor_v2_ring_tx_address_export => reg_bsn_monitor_v2_ring_tx_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w-1 DOWNTO 0), + reg_bsn_monitor_v2_ring_tx_clk_export => OPEN, + reg_bsn_monitor_v2_ring_tx_read_export => reg_bsn_monitor_v2_ring_tx_copi.rd, + reg_bsn_monitor_v2_ring_tx_readdata_export => reg_bsn_monitor_v2_ring_tx_cipo.rddata(c_word_w-1 DOWNTO 0), + reg_bsn_monitor_v2_ring_tx_reset_export => OPEN, + reg_bsn_monitor_v2_ring_tx_write_export => reg_bsn_monitor_v2_ring_tx_copi.wr, + reg_bsn_monitor_v2_ring_tx_writedata_export => reg_bsn_monitor_v2_ring_tx_copi.wrdata(c_word_w-1 DOWNTO 0), + + -- waveform generators (multiplexed) + reg_diag_bg_clk_export => OPEN, + reg_diag_bg_reset_export => OPEN, + reg_diag_bg_address_export => reg_diag_bg_copi.address(c_sdp_reg_diag_bg_addr_w-1 DOWNTO 0), + reg_diag_bg_read_export => reg_diag_bg_copi.rd, + reg_diag_bg_readdata_export => reg_diag_bg_cipo.rddata(c_word_w-1 DOWNTO 0), + reg_diag_bg_write_export => reg_diag_bg_copi.wr, + reg_diag_bg_writedata_export => reg_diag_bg_copi.wrdata(c_word_w-1 DOWNTO 0), + + ram_diag_bg_clk_export => OPEN, + ram_diag_bg_reset_export => OPEN, + ram_diag_bg_address_export => ram_diag_bg_copi.address(c_sdp_ram_diag_bg_addr_w-1 DOWNTO 0), + ram_diag_bg_read_export => ram_diag_bg_copi.rd, + ram_diag_bg_readdata_export => ram_diag_bg_cipo.rddata(c_word_w-1 DOWNTO 0), + ram_diag_bg_write_export => ram_diag_bg_copi.wr, + ram_diag_bg_writedata_export => ram_diag_bg_copi.wrdata(c_word_w-1 DOWNTO 0), + + reg_epcs_reset_export => OPEN, + reg_epcs_clk_export => OPEN, + reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0), + reg_epcs_write_export => reg_epcs_copi.wr, + reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_epcs_read_export => reg_epcs_copi.rd, + reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dpmm_ctrl_reset_export => OPEN, + reg_dpmm_ctrl_clk_export => OPEN, + reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 DOWNTO 0), + reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr, + reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd, + reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_mmdp_data_reset_export => OPEN, + reg_mmdp_data_clk_export => OPEN, + reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 DOWNTO 0), + reg_mmdp_data_write_export => reg_mmdp_data_copi.wr, + reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_mmdp_data_read_export => reg_mmdp_data_copi.rd, + reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dpmm_data_reset_export => OPEN, + reg_dpmm_data_clk_export => OPEN, + reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 DOWNTO 0), + reg_dpmm_data_read_export => reg_dpmm_data_copi.rd, + reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w-1 DOWNTO 0), + reg_dpmm_data_write_export => reg_dpmm_data_copi.wr, + reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w-1 DOWNTO 0), + + reg_mmdp_ctrl_reset_export => OPEN, + reg_mmdp_ctrl_clk_export => OPEN, + reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 DOWNTO 0), + reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd, + reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0), + reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr, + reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0), + + reg_ring_lane_info_clk_export => OPEN, + reg_ring_lane_info_reset_export => OPEN, + reg_ring_lane_info_address_export => reg_ring_lane_info_copi.address(c_sdp_reg_ring_lane_info_addr_w-1 DOWNTO 0), + reg_ring_lane_info_write_export => reg_ring_lane_info_copi.wr, + reg_ring_lane_info_writedata_export => reg_ring_lane_info_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_ring_lane_info_read_export => reg_ring_lane_info_copi.rd, + reg_ring_lane_info_readdata_export => reg_ring_lane_info_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dp_xonoff_lane_clk_export => OPEN, + reg_dp_xonoff_lane_reset_export => OPEN, + reg_dp_xonoff_lane_address_export => reg_dp_xonoff_lane_copi.address(c_sdp_reg_dp_xonoff_lane_addr_w-1 DOWNTO 0), + reg_dp_xonoff_lane_write_export => reg_dp_xonoff_lane_copi.wr, + reg_dp_xonoff_lane_writedata_export => reg_dp_xonoff_lane_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_dp_xonoff_lane_read_export => reg_dp_xonoff_lane_copi.rd, + reg_dp_xonoff_lane_readdata_export => reg_dp_xonoff_lane_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dp_xonoff_local_clk_export => OPEN, + reg_dp_xonoff_local_reset_export => OPEN, + reg_dp_xonoff_local_address_export => reg_dp_xonoff_local_copi.address(c_sdp_reg_dp_xonoff_local_addr_w-1 DOWNTO 0), + reg_dp_xonoff_local_write_export => reg_dp_xonoff_local_copi.wr, + reg_dp_xonoff_local_writedata_export => reg_dp_xonoff_local_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_dp_xonoff_local_read_export => reg_dp_xonoff_local_copi.rd, + reg_dp_xonoff_local_readdata_export => reg_dp_xonoff_local_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dp_block_validate_err_clk_export => OPEN, + reg_dp_block_validate_err_reset_export => OPEN, + reg_dp_block_validate_err_address_export => reg_dp_block_validate_err_copi.address(c_sdp_reg_dp_block_validate_err_addr_w-1 DOWNTO 0), + reg_dp_block_validate_err_write_export => reg_dp_block_validate_err_copi.wr, + reg_dp_block_validate_err_writedata_export => reg_dp_block_validate_err_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_dp_block_validate_err_read_export => reg_dp_block_validate_err_copi.rd, + reg_dp_block_validate_err_readdata_export => reg_dp_block_validate_err_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_dp_block_validate_bsn_at_sync_clk_export => OPEN, + reg_dp_block_validate_bsn_at_sync_reset_export => OPEN, + reg_dp_block_validate_bsn_at_sync_address_export => reg_dp_block_validate_bsn_at_sync_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w-1 DOWNTO 0), + reg_dp_block_validate_bsn_at_sync_write_export => reg_dp_block_validate_bsn_at_sync_copi.wr, + reg_dp_block_validate_bsn_at_sync_writedata_export => reg_dp_block_validate_bsn_at_sync_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_dp_block_validate_bsn_at_sync_read_export => reg_dp_block_validate_bsn_at_sync_copi.rd, + reg_dp_block_validate_bsn_at_sync_readdata_export => reg_dp_block_validate_bsn_at_sync_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_ring_info_clk_export => OPEN, + reg_ring_info_reset_export => OPEN, + reg_ring_info_address_export => reg_ring_info_copi.address(c_sdp_reg_ring_info_addr_w-1 DOWNTO 0), + reg_ring_info_write_export => reg_ring_info_copi.wr, + reg_ring_info_writedata_export => reg_ring_info_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_ring_info_read_export => reg_ring_info_copi.rd, + reg_ring_info_readdata_export => reg_ring_info_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_tr_10GbE_mac_clk_export => OPEN, + reg_tr_10GbE_mac_reset_export => OPEN, + reg_tr_10GbE_mac_address_export => reg_tr_10GbE_mac_copi.address(c_sdp_reg_tr_10GbE_mac_addr_w-1 DOWNTO 0), + reg_tr_10GbE_mac_write_export => reg_tr_10GbE_mac_copi.wr, + reg_tr_10GbE_mac_writedata_export => reg_tr_10GbE_mac_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_tr_10GbE_mac_read_export => reg_tr_10GbE_mac_copi.rd, + reg_tr_10GbE_mac_readdata_export => reg_tr_10GbE_mac_cipo.rddata(c_word_w-1 DOWNTO 0), + + reg_tr_10GbE_eth10g_clk_export => OPEN, + reg_tr_10GbE_eth10g_reset_export => OPEN, + reg_tr_10GbE_eth10g_address_export => reg_tr_10GbE_eth10g_copi.address(c_sdp_reg_tr_10GbE_eth10g_addr_w-1 DOWNTO 0), + reg_tr_10GbE_eth10g_write_export => reg_tr_10GbE_eth10g_copi.wr, + reg_tr_10GbE_eth10g_writedata_export => reg_tr_10GbE_eth10g_copi.wrdata(c_word_w-1 DOWNTO 0), + reg_tr_10GbE_eth10g_read_export => reg_tr_10GbE_eth10g_copi.rd, + reg_tr_10GbE_eth10g_readdata_export => reg_tr_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0), + + ram_scrap_clk_export => OPEN, + ram_scrap_reset_export => OPEN, + ram_scrap_address_export => ram_scrap_copi.address(9-1 DOWNTO 0), + ram_scrap_write_export => ram_scrap_copi.wr, + ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w-1 DOWNTO 0), + ram_scrap_read_export => ram_scrap_copi.rd, + ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w-1 DOWNTO 0) + ); + END GENERATE; +END str; diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..93ac9db79e3f1c1e2d99536b408fc06886a75ec7 --- /dev/null +++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd @@ -0,0 +1,246 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2020 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE qsys_lofar2_unb2b_ring_pkg IS + + ----------------------------------------------------------------------------- + -- this component declaration is copy-pasted from Quartus platform designer: + ----------------------------------------------------------------------------- + + component qsys_lofar2_unb2b_ring is + port ( + avs_eth_0_clk_export : out std_logic; -- export + avs_eth_0_irq_export : in std_logic := 'X'; -- export + avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export + avs_eth_0_ram_read_export : out std_logic; -- export + avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + avs_eth_0_ram_write_export : out std_logic; -- export + avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export + avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export + avs_eth_0_reg_read_export : out std_logic; -- export + avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + avs_eth_0_reg_write_export : out std_logic; -- export + avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export + avs_eth_0_reset_export : out std_logic; -- export + avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export + avs_eth_0_tse_read_export : out std_logic; -- export + avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export + avs_eth_0_tse_write_export : out std_logic; -- export + avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export + clk_clk : in std_logic := 'X'; -- clk + pio_pps_address_export : out std_logic_vector(1 downto 0); -- export + pio_pps_clk_export : out std_logic; -- export + pio_pps_read_export : out std_logic; -- export + pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + pio_pps_reset_export : out std_logic; -- export + pio_pps_write_export : out std_logic; -- export + pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export + pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export + pio_system_info_clk_export : out std_logic; -- export + pio_system_info_read_export : out std_logic; -- export + pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + pio_system_info_reset_export : out std_logic; -- export + pio_system_info_write_export : out std_logic; -- export + pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export + pio_wdi_external_connection_export : out std_logic; -- export + ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export + ram_diag_bg_clk_export : out std_logic; -- export + ram_diag_bg_read_export : out std_logic; -- export + ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + ram_diag_bg_reset_export : out std_logic; -- export + ram_diag_bg_write_export : out std_logic; -- export + ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export + ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export + ram_scrap_clk_export : out std_logic; -- export + ram_scrap_read_export : out std_logic; -- export + ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + ram_scrap_reset_export : out std_logic; -- export + ram_scrap_write_export : out std_logic; -- export + ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(6 downto 0); -- export + reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(6 downto 0); -- export + reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export + reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export + reg_diag_bg_clk_export : out std_logic; -- export + reg_diag_bg_read_export : out std_logic; -- export + reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_diag_bg_reset_export : out std_logic; -- export + reg_diag_bg_write_export : out std_logic; -- export + reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(3 downto 0); -- export + reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export + reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export + reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export + reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export + reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export + reg_dp_block_validate_err_clk_export : out std_logic; -- export + reg_dp_block_validate_err_read_export : out std_logic; -- export + reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dp_block_validate_err_reset_export : out std_logic; -- export + reg_dp_block_validate_err_write_export : out std_logic; -- export + reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export + reg_dp_xonoff_lane_clk_export : out std_logic; -- export + reg_dp_xonoff_lane_read_export : out std_logic; -- export + reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dp_xonoff_lane_reset_export : out std_logic; -- export + reg_dp_xonoff_lane_write_export : out std_logic; -- export + reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export + reg_dp_xonoff_local_clk_export : out std_logic; -- export + reg_dp_xonoff_local_read_export : out std_logic; -- export + reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dp_xonoff_local_reset_export : out std_logic; -- export + reg_dp_xonoff_local_write_export : out std_logic; -- export + reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export + reg_dpmm_ctrl_clk_export : out std_logic; -- export + reg_dpmm_ctrl_read_export : out std_logic; -- export + reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dpmm_ctrl_reset_export : out std_logic; -- export + reg_dpmm_ctrl_write_export : out std_logic; -- export + reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export + reg_dpmm_data_clk_export : out std_logic; -- export + reg_dpmm_data_read_export : out std_logic; -- export + reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_dpmm_data_reset_export : out std_logic; -- export + reg_dpmm_data_write_export : out std_logic; -- export + reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export + reg_epcs_clk_export : out std_logic; -- export + reg_epcs_read_export : out std_logic; -- export + reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_epcs_reset_export : out std_logic; -- export + reg_epcs_write_export : out std_logic; -- export + reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export + reg_fpga_temp_sens_clk_export : out std_logic; -- export + reg_fpga_temp_sens_read_export : out std_logic; -- export + reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_fpga_temp_sens_reset_export : out std_logic; -- export + reg_fpga_temp_sens_write_export : out std_logic; -- export + reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export + reg_fpga_voltage_sens_clk_export : out std_logic; -- export + reg_fpga_voltage_sens_read_export : out std_logic; -- export + reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_fpga_voltage_sens_reset_export : out std_logic; -- export + reg_fpga_voltage_sens_write_export : out std_logic; -- export + reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export + reg_mmdp_ctrl_clk_export : out std_logic; -- export + reg_mmdp_ctrl_read_export : out std_logic; -- export + reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_mmdp_ctrl_reset_export : out std_logic; -- export + reg_mmdp_ctrl_write_export : out std_logic; -- export + reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export + reg_mmdp_data_clk_export : out std_logic; -- export + reg_mmdp_data_read_export : out std_logic; -- export + reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_mmdp_data_reset_export : out std_logic; -- export + reg_mmdp_data_write_export : out std_logic; -- export + reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_remu_address_export : out std_logic_vector(2 downto 0); -- export + reg_remu_clk_export : out std_logic; -- export + reg_remu_read_export : out std_logic; -- export + reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_remu_reset_export : out std_logic; -- export + reg_remu_write_export : out std_logic; -- export + reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export + reg_ring_info_clk_export : out std_logic; -- export + reg_ring_info_read_export : out std_logic; -- export + reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_ring_info_reset_export : out std_logic; -- export + reg_ring_info_write_export : out std_logic; -- export + reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export + reg_ring_lane_info_clk_export : out std_logic; -- export + reg_ring_lane_info_read_export : out std_logic; -- export + reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_ring_lane_info_reset_export : out std_logic; -- export + reg_ring_lane_info_write_export : out std_logic; -- export + reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export + reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export + reg_tr_10gbe_eth10g_read_export : out std_logic; -- export + reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export + reg_tr_10gbe_eth10g_write_export : out std_logic; -- export + reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export + reg_tr_10gbe_mac_clk_export : out std_logic; -- export + reg_tr_10gbe_mac_read_export : out std_logic; -- export + reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_tr_10gbe_mac_reset_export : out std_logic; -- export + reg_tr_10gbe_mac_write_export : out std_logic; -- export + reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export + reg_unb_pmbus_clk_export : out std_logic; -- export + reg_unb_pmbus_read_export : out std_logic; -- export + reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_unb_pmbus_reset_export : out std_logic; -- export + reg_unb_pmbus_write_export : out std_logic; -- export + reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export + reg_unb_sens_clk_export : out std_logic; -- export + reg_unb_sens_read_export : out std_logic; -- export + reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_unb_sens_reset_export : out std_logic; -- export + reg_unb_sens_write_export : out std_logic; -- export + reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export + reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export + reg_wdi_clk_export : out std_logic; -- export + reg_wdi_read_export : out std_logic; -- export + reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_wdi_reset_export : out std_logic; -- export + reg_wdi_write_export : out std_logic; -- export + reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export + reset_reset_n : in std_logic := 'X'; -- reset_n + rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export + rom_system_info_clk_export : out std_logic; -- export + rom_system_info_read_export : out std_logic; -- export + rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + rom_system_info_reset_export : out std_logic; -- export + rom_system_info_write_export : out std_logic; -- export + rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export + ); + end component qsys_lofar2_unb2b_ring; +END qsys_lofar2_unb2b_ring_pkg; + diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd index 2f75f2f098ace38313417f95651dfd84db0232e0..134b80aa33fee8a984a5e9a0d60fe94f8023ba5e 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd @@ -228,7 +228,7 @@ BEGIN GENERIC MAP ( g_complex => TRUE, g_representation => "SIGNED", - g_lsb_w => c_sdp_W_bf_fraction, + g_lsb_w => c_sdp_W_bf_weight_fraction, g_lsb_round => TRUE, g_lsb_round_clip => FALSE, g_msb_clip => FALSE, diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd index eb1ff3b7ffa9399c4eecdf6cac9570efecf6530f..b945f7d6941896b98ec58077718a4450a3fb239a 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd @@ -69,6 +69,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS CONSTANT c_crosslets_info_dly : NATURAL := 1; + CONSTANT c_col_select_addr_w : NATURAL := ceil_log2(c_sdp_Q_fft * c_sdp_N_sub); CONSTANT c_row_select_slv_w : NATURAL := ceil_log2(c_sdp_P_pfb); CONSTANT c_row_select_pipeline : NATURAL := 1; CONSTANT c_out_sosi_pipeline : NATURAL := 1; @@ -232,7 +233,7 @@ BEGIN END IF; v.col_select_mosi.rd := '1'; - v.col_select_mosi.address(c_sdp_crosslets_index_w-1 DOWNTO 0) := TO_UVEC(c_sdp_Q_fft*v_offsets(r.offset_index) + r.col_index, c_sdp_crosslets_index_w); + v.col_select_mosi.address(c_col_select_addr_w-1 DOWNTO 0) := TO_UVEC(c_sdp_Q_fft*v_offsets(r.offset_index) + r.col_index, c_col_select_addr_w); v.row_select_slv := TO_UVEC(r.row_index, c_row_select_slv_w); END IF; END IF; diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd index 547b1301ff19305c0f30051aeb7338b251818620..aeaa4b503ef02754561922705d2f9803c9444a18 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd @@ -74,6 +74,7 @@ PACKAGE sdp_pkg is CONSTANT c_sdp_N_pn_lb : NATURAL := 16; CONSTANT c_sdp_N_pol : NATURAL := 2; CONSTANT c_sdp_N_pol_bf : NATURAL := 2; + CONSTANT c_sdp_N_ring_lanes_max: NATURAL := 8; CONSTANT c_sdp_N_sub : NATURAL := 512; CONSTANT c_sdp_N_taps : NATURAL := 16; CONSTANT c_sdp_P_sq : NATURAL := 9; @@ -87,27 +88,29 @@ PACKAGE sdp_pkg is CONSTANT c_sdp_V_si_histogram : NATURAL := 512; CONSTANT c_sdp_W_adc : NATURAL := 14; CONSTANT c_sdp_W_adc_jesd : NATURAL := 16; - CONSTANT c_sdp_W_beamlet : NATURAL := 8; - CONSTANT c_sdp_W_beamlet_scale : NATURAL := 16; - CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18; - CONSTANT c_sdp_W_bf_magnitude : NATURAL := 1; - CONSTANT c_sdp_W_bf_weight : NATURAL := 16; - CONSTANT c_sdp_W_crosslet : NATURAL := 16; CONSTANT c_sdp_W_fir_coef : NATURAL := 16; + CONSTANT c_sdp_W_subband : NATURAL := 18; + CONSTANT c_sdp_W_crosslet : NATURAL := 16; + CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18; + CONSTANT c_sdp_W_beamlet : NATURAL := 8; CONSTANT c_sdp_W_gn_id : NATURAL := 5; CONSTANT c_sdp_W_statistic : NATURAL := 64; - CONSTANT c_sdp_W_sub_magnitude : NATURAL := 2; - CONSTANT c_sdp_W_sub_weight : NATURAL := 16; - CONSTANT c_sdp_W_subband : NATURAL := 18; + CONSTANT c_sdp_W_sub_weight : NATURAL := 16; -- = w in s(w, p), s = signed + CONSTANT c_sdp_W_sub_weight_fraction : NATURAL := 13; -- = p in s(w, p) + CONSTANT c_sdp_W_sub_weight_magnitude : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 2 + CONSTANT c_sdp_W_beamlet_scale : NATURAL := 16; -- = w in u(w, p), u = unsigned + CONSTANT c_sdp_W_beamlet_scale_fraction : NATURAL := 15; -- = p in u(w, p) + CONSTANT c_sdp_W_beamlet_scale_magnitude : NATURAL := c_sdp_W_beamlet_scale - c_sdp_W_beamlet_scale_fraction; -- = 1 + CONSTANT c_sdp_W_bf_weight : NATURAL := 16; -- = w in s(w, p), s = signed + CONSTANT c_sdp_W_bf_weight_fraction : NATURAL := 14; -- = p in s(w, p) + CONSTANT c_sdp_W_bf_weight_magnitude : NATURAL := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1; -- = 1 -- Derived constants CONSTANT c_sdp_FS_adc : NATURAL := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0 CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft; CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps; CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc; - CONSTANT c_sdp_W_bf_fraction : NATURAL := c_sdp_W_bf_weight - c_sdp_W_bf_magnitude -1; CONSTANT c_sdp_W_bf_product : NATURAL := c_sdp_W_subband + c_sdp_W_bf_weight -1; - CONSTANT c_sdp_W_sub_fraction : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_magnitude -1; CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn; -- @@ -342,6 +345,21 @@ PACKAGE sdp_pkg is CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4; CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) ); + -- RING MM address widths + CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4; + CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4; + CONSTANT c_sdp_reg_ring_lane_info_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; + CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; + CONSTANT c_sdp_reg_dp_xonoff_local_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; + CONSTANT c_sdp_reg_dp_block_validate_err_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4; + CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1; + CONSTANT c_sdp_reg_ring_info_addr_w : NATURAL := 2; + CONSTANT c_sdp_reg_tr_10GbE_mac_addr_w : NATURAL := 13; + CONSTANT c_sdp_reg_tr_10GbE_eth10g_addr_w : NATURAL := 1; + CONSTANT c_sdp_reg_diag_bg_addr_w : NATURAL := 3; + CONSTANT c_sdp_ram_diag_bg_addr_w : NATURAL := 7; + + END PACKAGE sdp_pkg; PACKAGE BODY sdp_pkg IS diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd index fe03722c40bc586c45be832055c6648b1bc144fe..7ae6012f078832edcae802a8e94dec511874f292 100644 --- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd +++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd @@ -146,7 +146,7 @@ BEGIN GENERIC MAP ( g_complex => TRUE, g_representation => "SIGNED", - g_lsb_w => c_sdp_W_sub_fraction, + g_lsb_w => c_sdp_W_sub_weight_fraction, g_lsb_round => TRUE, g_lsb_round_clip => FALSE, g_msb_clip => TRUE, diff --git a/applications/lofar2/model/lofar_station_firmware_model.py b/applications/lofar2/model/lofar_station_firmware_model.py index 11d1ecea593fa4ed270aa474893e58b13f3d8121..260a77962ccbad1ff2479816808e98f616312415 100644 --- a/applications/lofar2/model/lofar_station_firmware_model.py +++ b/applications/lofar2/model/lofar_station_firmware_model.py @@ -148,21 +148,21 @@ N_sub = 512 # = N_fft / N_complex W_fsub_proc = math.log(math.sqrt(N_sub), 2) # = 4.5, processing gain of F_sub in number of bits N_int_sub = 195312.5 -W_se_weight = 16 -W_se_magnitude = 1 -W_se_fraction = 14 -c_se_unit_weight = 2**W_se_fraction -W_bf_weight = 16 -W_bf_magnitude = 1 -W_bf_fraction = 14 -c_bf_unit_weight = 2**W_sub_fraction +W_sub_weight = 16 # signed +W_sub_weight_fraction = 13 +W_sub_weight_magnitude = W_sub_weight - W_sub_weight_fraction - 1 +c_sub_weight_unit = 2**W_sub_weight_fraction -W_beamlet_scale = 16 -W_beamlet_scale_magnitude = 1 -W_beamlet_scale_fraction = 14 -c_beamlet_scale_unit = 2**W_beamlet_scale_fraction +W_bf_weight = 16 # signed +W_bf_weight_fraction = 14 +W_bf_weight_magnitude = W_bf_weight - W_bf_weight_fraction - 1 +c_bf_weight_unit = 2**W_bf_weight_fraction +W_beamlet_scale = 16 # unsigned +W_beamlet_scale_fraction = 15 +W_beamlet_scale_magnitude = W_beamlet_scale - W_beamlet_scale_fraction +c_beamlet_scale_unit = 2**W_beamlet_scale_fraction W_sst_fraction = 4 # Extra fraction bits for SST subband input compared to W_adc W_sst_in = 18 # Word width in number of bits of SST subband data input, = W_adc + W_sst_fraction @@ -312,8 +312,8 @@ if 'dynamic' in models: # Derived gains # Aperif BF subband CB voltage weight -subWeight = c_sub_unit_weight * subWeightAdjust # = 16384 = 2**14 * 1.0 -bfWeight = c_bf_unit_weight * bfWeightAdjust # = 16384 = 2**14 * 1.0 +subWeight = c_sub_weight_unit * subWeightAdjust # = 16384 = 2**14 * 1.0 +bfWeight = c_bf_weight_unit * bfWeightAdjust # = 16384 = 2**14 * 1.0 if quantize: subWeight = np.round(subWeight) bfWeight = np.round(bfWeight) diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0b33ed4c02331e284be62af8c60356aebc66870d --- /dev/null +++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml @@ -0,0 +1,266 @@ +schema_name : args +schema_version: 1.0 +schema_type : fpga + +hdl_library_name: unb2c_test +fpga_name : unb2c_test +fpga_description: "FPGA design unb2c_test" +parameters: + - { name: c_nof_streams_1GbE_UDP, value: 2 } + - { name: c_def_1GbE_block_size, value: 20 } + - { name: c_nof_streams_10GbE_UDP, value: 72 } + - { name: c_def_10GbE_block_size, value: 900 } + - { name: c_nof_streams_qsfp, value: 24 } + - { name: c_nof_streams_ring, value: 24 } + - { name: c_nof_streams_back0, value: 24 } + - { name: c_ddr_db_buf_nof_data, value: 1024 } + - { name: c_nof_streams_jesd204b, value: 12 } + - { name: c_jesd_db_buf_nof_data, value: 131072 } + +peripherals: + # ctrl_unb2c_board + - peripheral_name: unb2c_board/system_info + lock_base_address: 0x10000 + mm_port_names: + - ROM_SYSTEM_INFO + - PIO_SYSTEM_INFO + + - peripheral_name: unb2c_board/wdi + mm_port_names: + - REG_WDI + + - peripheral_name: unb2c_board/unb2_fpga_sens + mm_port_names: + - REG_FPGA_TEMP_SENS + - REG_FPGA_VOLTAGE_SENS + + - peripheral_name: unb2c_board/ram_scrap + mm_port_names: + - RAM_SCRAP + + - peripheral_name: eth/eth + mm_port_names: + - AVS_ETH_0_TSE + - AVS_ETH_0_REG + - AVS_ETH_0_RAM + + - peripheral_name: ppsh/ppsh + mm_port_names: + - PIO_PPS + + - peripheral_name: epcs/epcs + mm_port_names: + - REG_EPCS + + - peripheral_name: dp/dpmm + mm_port_names: + - REG_DPMM_CTRL + - REG_DPMM_DATA + + - peripheral_name: dp/mmdp + mm_port_names: + - REG_MMDP_CTRL + - REG_MMDP_DATA + + - peripheral_name: remu/remu + mm_port_names: + - REG_REMU + + # Heater + - peripheral_name: util/heater + mm_port_names: + - REG_HEATER + + # 1GbE + - peripheral_name: diag/diag_block_gen + peripheral_group: eth_1gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP } + - { name: g_buf_dat_w, value: 32 } + - { name: g_buf_addr_w, value: ceil_log2(c_def_1GbE_block_size) } + mm_port_names: + - REG_DIAG_BG_1GBE + - RAM_DIAG_BG_1GBE + + - peripheral_name: diag/diag_tx_seq + peripheral_group: eth_1gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP } + mm_port_names: + - REG_DIAG_TX_SEQ_1GBE + + - peripheral_name: dp/dp_bsn_monitor + peripheral_group: eth_1gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP } + mm_port_names: + - REG_BSN_MONITOR_1GBE + + - peripheral_name: diag/diag_data_buffer + peripheral_group: eth_1gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP } + - { name: g_data_w, value: 32 } + - { name: g_nof_data, value: c_def_1GbE_block_size } + mm_port_names: + - REG_DIAG_DATA_BUFFER_1GBE + - RAM_DIAG_DATA_BUFFER_1GBE + + - peripheral_name: diag/diag_rx_seq + peripheral_group: eth_1gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_1GbE_UDP } + mm_port_names: + - REG_DIAG_TX_SEQ_1GBE + + # 10GbE + - peripheral_name: diag/diag_block_gen + peripheral_group: eth_10gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP } + - { name: g_buf_dat_w, value: 64 } + - { name: g_buf_addr_w, value: ceil_log2(c_def_10GbE_block_size) } + mm_port_names: + - REG_DIAG_BG_10GBE + - RAM_DIAG_BG_10GBE + + - peripheral_name: diag/diag_tx_seq + peripheral_group: eth_10gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP } + mm_port_names: + - REG_DIAG_TX_SEQ_10GBE + + - peripheral_name: dp/dp_bsn_monitor + peripheral_group: eth_10gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP } + mm_port_names: + - REG_BSN_MONITOR_10GBE + + - peripheral_name: diag/diag_data_buffer + peripheral_group: eth_10gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP } + - { name: g_data_w, value: 64 } + - { name: g_nof_data, value: c_def_10GbE_block_size } + mm_port_names: + - REG_DIAG_DATA_BUFFER_10GBE + - RAM_DIAG_DATA_BUFFER_10GBE + + - peripheral_name: diag/diag_rx_seq + peripheral_group: eth_10gbe + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_10GbE_UDP } + mm_port_names: + - REG_DIAG_TX_SEQ_10GBE + + - peripheral_name: tr_10GbE/tr_10GbE_unb2legacy + peripheral_group: qsfp_ring + parameter_overrides: + - { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring } + mm_port_names: + - REG_TR_10GBE_QSFP_RING + + - peripheral_name: tr_10GbE/tr_10GbE_eth10g + peripheral_group: qsfp_ring + parameter_overrides: + - { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring } + mm_port_names: + - REG_ETH10G_QSFP_RING + + - peripheral_name: tr_10GbE/tr_10GbE_unb2legacy + peripheral_group: back0 + parameter_overrides: + - { name: g_nof_macs, value: c_nof_streams_back0 } + mm_port_names: + - REG_TR_10GBE_BACK0 + + - peripheral_name: tr_10GbE/tr_10GbE_eth10g + peripheral_group: back0 + parameter_overrides: + - { name: g_nof_macs, value: c_nof_streams_back0 } + mm_port_names: + - REG_ETH10G_BACK0 + + # DDR4 : MB I + - peripheral_name: ddr/io_ddr + peripheral_group: MB_I + mm_port_names: + - REG_IO_DDR_MB_I + + - peripheral_name: diag/diag_tx_seq + peripheral_group: MB_I + mm_port_names: + - REG_DIAG_TX_SEQ_DDR_MB_I + + - peripheral_name: diag/diag_rx_seq + peripheral_group: MB_I + mm_port_names: + - REG_DIAG_RX_SEQ_DDR_MB_I + + - peripheral_name: diag/diag_data_buffer + peripheral_group: ddr_MB_I + parameter_overrides: + - { name: g_data_w, value: 32 } + - { name: g_nof_data, value: c_ddr_db_buf_nof_data } + mm_port_names: + - REG_DIAG_DATA_BUFFER_DDR_MB_I + - RAM_DIAG_DATA_BUFFER_DDR_MB_I + + # DDR4 : MB II + - peripheral_name: ddr/io_ddr + peripheral_group: MB_II + mm_port_names: + - REG_IO_DDR_MB_II + + - peripheral_name: diag/diag_tx_seq + peripheral_group: MB_II + mm_port_names: + - REG_DIAG_TX_SEQ_DDR_MB_II + + - peripheral_name: diag/diag_rx_seq + peripheral_group: MB_II + mm_port_names: + - REG_DIAG_RX_SEQ_DDR_MB_II + + - peripheral_name: diag/diag_data_buffer + peripheral_group: ddr_MB_II + parameter_overrides: + - { name: g_data_w, value: 32 } + - { name: g_nof_data, value: c_ddr_db_buf_nof_data } + mm_port_names: + - REG_DIAG_DATA_BUFFER_DDR_MB_II + - RAM_DIAG_DATA_BUFFER_DDR_MB_II + + # JESD + - peripheral_name: tech_jesd204b/jesd_ctrl + mm_port_names: + - PIO_JESD_CTRL + + - peripheral_name: tech_jesd204b/jesd204b_arria10 + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_jesd204b } + mm_port_names: + - JESD204B + + - peripheral_name: dp/dp_bsn_source + mm_port_names: + - REG_BSN_SOURCE + + - peripheral_name: dp/dp_bsn_monitor + peripheral_group: input + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_jesd204b } + mm_port_names: + - REG_BSN_MONITOR_INPUT + + - peripheral_name: diag/diag_data_buffer + peripheral_group: bsn + parameter_overrides: + - { name: g_nof_streams, value: c_nof_streams_jesd204b } + - { name: g_data_w, value: 16 } + - { name: g_nof_data, value: c_jesd_db_buf_nof_data } + mm_port_names: + - REG_DIAG_DATA_BUFFER_BSN + - RAM_DIAG_DATA_BUFFER_BSN diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold new file mode 100644 index 0000000000000000000000000000000000000000..cf11530f03b11841fe27976ab2c48add046d1660 --- /dev/null +++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold @@ -0,0 +1,593 @@ +fpga_name = unb2c_test +number_of_columns = 13 +# There can be multiple lines with a single key. The host should ignore unknown keys. +# The lines with columns follow after the number_of_columns keys. The host should ignore +# the extra columns in case the mmap contains more columns than the host expects. +# +# col 1: mm_port_name, if - then it is part of previous MM port. +# col 2: number of peripherals, if - then it is part of previous peripheral. +# col 3: number of mm_ports, if - then it is part of previous MM port. +# col 4: mm_port_type, if - then it is part of previous MM port. +# col 5: field_name +# col 6: field start address (in MM words) +# col 7: number of fields, if - then it is part of previous field_name. +# col 8: field access_mode, if - then it is part of previous field_name. +# col 9: field radix, if - then it is part of previous field_name. +# col 10: field mm_mask +# col 11: field user_mask, if - then it is same as mm_mask +# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port +# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port +# +# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 +# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- ----- + ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - - + PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - - + - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - - + - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - - + - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - - + - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - - + - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - - + - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - - + - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - - + - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - - + - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - - + - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - - + - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - - + - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - - + - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - - + REG_WDI 1 1 REG wdi_override 0x00080000 1 WO uint32 b[31:0] - - - + REG_FPGA_TEMP_SENS 1 1 REG temp 0x00100000 1 RO uint32 b[31:0] - - - + REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00100000 6 RO uint32 b[31:0] - - - + RAM_SCRAP 1 1 RAM data 0x00180000 512 RW uint32 b[31:0] - - - + AVS_ETH_0_TSE 1 1 REG status 0x00200000 1024 RO uint32 b[31:0] - - - + AVS_ETH_0_REG 1 1 REG status 0x00200000 12 RO uint32 b[31:0] - - - + AVS_ETH_0_RAM 1 1 RAM data 0x00200400 1024 RW uint32 b[31:0] - - - + PIO_PPS 1 1 REG capture_cnt 0x00280000 1 RO uint32 b[29:0] - - - + - - - - stable 0x00280000 1 RO uint32 b[30:30] - - - + - - - - toggle 0x00280000 1 RO uint32 b[31:31] - - - + - - - - expected_cnt 0x00280001 1 RW uint32 b[27:0] - - - + - - - - edge 0x00280001 1 RW uint32 b[31:31] - - - + - - - - offset_cnt 0x00280002 1 RO uint32 b[27:0] - - - + REG_EPCS 1 1 REG addr 0x00300000 1 WO uint32 b[23:0] - - - + - - - - rden 0x00300001 1 WO uint32 b[0:0] - - - + - - - - read_bit 0x00300002 1 WO uint32 b[0:0] - - - + - - - - write_bit 0x00300003 1 WO uint32 b[0:0] - - - + - - - - sector_erase 0x00300004 1 WO uint32 b[0:0] - - - + - - - - busy 0x00300005 1 RO uint32 b[0:0] - - - + - - - - unprotect 0x00300006 1 WO uint32 b[31:0] - - - + REG_DPMM_CTRL 1 1 REG rd_usedw 0x00380000 1 RO uint32 b[31:0] - - - + REG_DPMM_DATA 1 1 FIFO data 0x00380400 1 RO uint32 b[31:0] - - - + REG_MMDP_CTRL 1 1 REG wr_usedw 0x00400000 1 RO uint32 b[31:0] - - - + - - - - wr_availw 0x00400001 1 RO uint32 b[31:0] - - - + REG_MMDP_DATA 1 1 FIFO data 0x00400400 1 WO uint32 b[31:0] - - - + REG_REMU 1 1 REG reconfigure 0x00480000 1 WO uint32 b[31:0] - - - + - - - - param 0x00480001 1 WO uint32 b[2:0] - - - + - - - - read_param 0x00480002 1 WO uint32 b[0:0] - - - + - - - - write_param 0x00480003 1 WO uint32 b[0:0] - - - + - - - - data_out 0x00480004 1 RO uint32 b[23:0] - - - + - - - - data_in 0x00480005 1 WO uint32 b[23:0] - - - + - - - - busy 0x00480006 1 RO uint32 b[0:0] - - - + REG_HEATER 1 1 REG enable 0x00500000 25 RW uint32 b[31:0] - - - + REG_DIAG_BG_1GBE 1 1 REG enable 0x00580000 1 RW uint32 b[0:0] - - - + - - - - enable_sync 0x00580000 1 RW uint32 b[1:1] - - - + - - - - samples_per_packet 0x00580001 1 RW uint32 b[31:0] - - - + - - - - blocks_per_sync 0x00580002 1 RW uint32 b[31:0] - - - + - - - - gapsize 0x00580003 1 RW uint32 b[31:0] - - - + - - - - mem_low_adrs 0x00580004 1 RW uint32 b[31:0] - - - + - - - - mem_high_adrs 0x00580005 1 RW uint32 b[31:0] - - - + - - - - bsn_init 0x00580006 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x00580007 - - - b[31:0] b[63:32] - - + RAM_DIAG_BG_1GBE 1 2 RAM data 0x00580400 32 RW uint32 b[31:0] - - 32 + REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00600000 1 RW uint32 b[2:0] - - 4 + - - - - init 0x00600001 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00600002 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00600003 1 RW uint32 b[31:0] - - - + REG_BSN_MONITOR_1GBE 1 2 REG xon_stable 0x00680000 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x00680000 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x00680000 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x00680001 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00680002 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x00680003 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x00680004 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x00680005 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x00680006 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00680007 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x00680008 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_1GBE 1 2 REG sync_cnt 0x00700000 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x00700001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_1GBE 1 2 RAM data 0x00700400 20 RW uint32 b[31:0] - - 32 + REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00780000 1 RW uint32 b[1:0] - - 8 + - - - - result 0x00780001 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00780002 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00780003 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00780004 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00780005 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00780006 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00780007 1 RW uint32 b[31:0] - - - + REG_DIAG_BG_10GBE 1 1 REG enable 0x00800000 1 RW uint32 b[0:0] - - - + - - - - enable_sync 0x00800000 1 RW uint32 b[1:1] - - - + - - - - samples_per_packet 0x00800001 1 RW uint32 b[31:0] - - - + - - - - blocks_per_sync 0x00800002 1 RW uint32 b[31:0] - - - + - - - - gapsize 0x00800003 1 RW uint32 b[31:0] - - - + - - - - mem_low_adrs 0x00800004 1 RW uint32 b[31:0] - - - + - - - - mem_high_adrs 0x00800005 1 RW uint32 b[31:0] - - - + - - - - bsn_init 0x00800006 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x00800007 - - - b[31:0] b[63:32] - - + RAM_DIAG_BG_10GBE 1 72 RAM data 0x00840000 1024 RW uint32 b[31:0] b[31:0] - 2048 + - - - - - 0x00840001 - - - b[31:0] b[63:32] - - + REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00880000 1 RW uint32 b[2:0] - - 4 + - - - - init 0x00880001 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00880002 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00880003 1 RW uint32 b[31:0] - - - + REG_BSN_MONITOR_10GBE 1 72 REG xon_stable 0x00900000 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x00900000 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x00900000 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x00900001 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00900002 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x00900003 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x00900004 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x00900005 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x00900006 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00900007 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x00900008 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_10GBE 1 72 REG sync_cnt 0x00980000 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x00980001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_10GBE 1 72 RAM data 0x009c0000 900 RW uint32 b[31:0] b[31:0] - 2048 + - - - - - 0x009c0001 - - - b[31:0] b[63:32] - - + REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00a00000 1 RW uint32 b[1:0] - - 8 + - - - - result 0x00a00001 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00a00002 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00a00003 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00a00004 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00a00005 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00a00006 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00a00007 1 RW uint32 b[31:0] - - - + REG_TR_10GBE_QSFP_RING 1 48 REG rx_transfer_control 0x00a80000 1 RW uint32 b[0:0] - - 1 + - - - - rx_transfer_status 0x00a80001 1 RO uint32 b[0:0] - - - + - - - - tx_transfer_control 0x00a80002 1 RW uint32 b[0:0] - - - + - - - - rx_padcrc_control 0x00a80040 1 RW uint32 b[1:0] - - - + - - - - rx_crccheck_control 0x00a80080 1 RW uint32 b[1:0] - - - + - - - - rx_pktovrflow_error 0x00a800c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a800c1 - - - b[31:0] b[31:0] - - + - - - - rx_pktovrflow_etherstatsdropevents 0x00a800c2 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a800c3 - - - b[31:0] b[31:0] - - + - - - - rx_lane_decoder_preamble_control 0x00a80100 1 RW uint32 b[0:0] - - - + - - - - rx_preamble_inserter_control 0x00a80140 1 RW uint32 b[0:0] - - - + - - - - rx_frame_control 0x00a80800 1 RW uint32 b[19:0] - - - + - - - - rx_frame_maxlength 0x00a80801 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr0 0x00a80802 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr1 0x00a80803 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_0 0x00a80804 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_1 0x00a80805 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_0 0x00a80806 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_1 0x00a80807 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_0 0x00a80808 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_1 0x00a80809 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_0 0x00a8080a 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_1 0x00a8080b 1 RW uint32 b[15:0] - - - + - - - - rx_pfc_control 0x00a80818 1 RW uint32 b[16:0] - - - + - - - - rx_stats_clr 0x00a80c00 1 RW uint32 b[0:0] - - - + - - - - rx_stats_framesok 0x00a80c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c03 - - - b[31:0] b[31:0] - - + - - - - rx_stats_frameserr 0x00a80c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c05 - - - b[31:0] b[31:0] - - + - - - - rx_stats_framescrcerr 0x00a80c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c07 - - - b[31:0] b[31:0] - - + - - - - rx_stats_octetsok 0x00a80c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c09 - - - b[31:0] b[31:0] - - + - - - - rx_stats_pausemacctrl_frames 0x00a80c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c0b - - - b[31:0] b[31:0] - - + - - - - rx_stats_iferrors 0x00a80c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c0d - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_framesok 0x00a80c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c0f - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_frameserr 0x00a80c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c11 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastframesok 0x00a80c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c13 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicast_frameserr 0x00a80c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c15 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastframesok 0x00a80c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c17 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcast_frameserr 0x00a80c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c19 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatsoctets 0x00a80c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c1b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatspkts 0x00a80c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c1d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_undersizepkts 0x00a80c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c1f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_oversizepkts 0x00a80c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c21 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts64octets 0x00a80c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c23 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts65to127octets 0x00a80c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c25 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts128to255octets 0x00a80c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c27 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts256to511octets 0x00a80c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c29 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts512to1023octets 0x00a80c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c2b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstat_pkts1024to1518octets 0x00a80c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c2d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts1519toxoctets 0x00a80c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c2f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_fragments 0x00a80c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c31 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_jabbers 0x00a80c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c33 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatscrcerr 0x00a80c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c35 - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicastmacctrlframes 0x00a80c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c37 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastmac_ctrlframes 0x00a80c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c39 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastmac_ctrlframes 0x00a80c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c3b - - - b[31:0] b[31:0] - - + - - - - rx_stats_pfcmacctrlframes 0x00a80c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a80c3d - - - b[31:0] b[31:0] - - + - - - - tx_transfer_status 0x00a81001 1 RO uint32 b[0:0] - - - + - - - - tx_padins_control 0x00a81040 1 RW uint32 b[0:0] - - - + - - - - tx_crcins_control 0x00a81080 1 RW uint32 b[1:0] - - - + - - - - tx_pktunderflow_error 0x00a810c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a810c1 - - - b[31:0] b[31:0] - - + - - - - tx_preamble_control 0x00a81100 1 RW uint32 b[0:0] - - - + - - - - tx_pauseframe_control 0x00a81140 1 RW uint32 b[1:0] - - - + - - - - tx_pauseframe_quanta 0x00a81141 1 RW uint32 b[15:0] - - - + - - - - tx_pauseframe_enable 0x00a81142 1 RW uint32 b[0:0] - - - + - - - - pfc_pause_quanta_0 0x00a81180 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_1 0x00a81181 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_2 0x00a81182 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_3 0x00a81183 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_4 0x00a81184 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_5 0x00a81185 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_6 0x00a81186 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_7 0x00a81187 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_0 0x00a81190 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_1 0x00a81191 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_2 0x00a81192 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_3 0x00a81193 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_4 0x00a81194 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_5 0x00a81195 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_6 0x00a81196 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_7 0x00a81197 1 RW uint32 b[31:0] - - - + - - - - tx_pfc_priority_enable 0x00a811a0 1 RW uint32 b[7:0] - - - + - - - - tx_addrins_control 0x00a81200 1 RW uint32 b[0:0] - - - + - - - - tx_addrins_macaddr0 0x00a81201 1 RW uint32 b[31:0] - - - + - - - - tx_addrins_macaddr1 0x00a81202 1 RW uint32 b[15:0] - - - + - - - - tx_frame_maxlength 0x00a81801 1 RW uint32 b[15:0] - - - + - - - - tx_stats_clr 0x00a81c00 1 RW uint32 b[0:0] - - - + - - - - tx_stats_framesok 0x00a81c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c03 - - - b[31:0] b[31:0] - - + - - - - tx_stats_frameserr 0x00a81c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c05 - - - b[31:0] b[31:0] - - + - - - - tx_stats_framescrcerr 0x00a81c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c07 - - - b[31:0] b[31:0] - - + - - - - tx_stats_octetsok 0x00a81c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c09 - - - b[31:0] b[31:0] - - + - - - - tx_stats_pausemacctrl_frames 0x00a81c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c0b - - - b[31:0] b[31:0] - - + - - - - tx_stats_iferrors 0x00a81c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c0d - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_framesok 0x00a81c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c0f - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_frameserr 0x00a81c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c11 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastframesok 0x00a81c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c13 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicast_frameserr 0x00a81c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c15 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastframesok 0x00a81c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c17 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcast_frameserr 0x00a81c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c19 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatsoctets 0x00a81c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c1b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatspkts 0x00a81c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c1d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_undersizepkts 0x00a81c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c1f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_oversizepkts 0x00a81c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c21 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts64octets 0x00a81c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c23 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts65to127octets 0x00a81c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c25 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts128to255octets 0x00a81c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c27 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts256to511octets 0x00a81c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c29 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts512to1023octets 0x00a81c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c2b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstat_pkts1024to1518octets 0x00a81c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c2d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts1519toxoctets 0x00a81c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c2f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_fragments 0x00a81c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c31 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_jabbers 0x00a81c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c33 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatscrcerr 0x00a81c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c35 - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicastmacctrlframes 0x00a81c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c37 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastmac_ctrlframes 0x00a81c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c39 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastmac_ctrlframes 0x00a81c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c3b - - - b[31:0] b[31:0] - - + - - - - tx_stats_pfcmacctrlframes 0x00a81c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00a81c3d - - - b[31:0] b[31:0] - - + REG_ETH10G_QSFP_RING 1 48 REG tx_snk_out_xon 0x00b00000 1 RO uint32 b[0:0] - - 1 + - - - - xgmii_tx_ready 0x00b00000 1 RO uint32 b[1:1] - - - + - - - - xgmii_link_status 0x00b00000 1 RO uint32 b[3:2] - - - + REG_TR_10GBE_BACK0 1 24 REG rx_transfer_control 0x00b80000 1 RW uint32 b[0:0] - - 1 + - - - - rx_transfer_status 0x00b80001 1 RO uint32 b[0:0] - - - + - - - - tx_transfer_control 0x00b80002 1 RW uint32 b[0:0] - - - + - - - - rx_padcrc_control 0x00b80040 1 RW uint32 b[1:0] - - - + - - - - rx_crccheck_control 0x00b80080 1 RW uint32 b[1:0] - - - + - - - - rx_pktovrflow_error 0x00b800c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b800c1 - - - b[31:0] b[31:0] - - + - - - - rx_pktovrflow_etherstatsdropevents 0x00b800c2 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b800c3 - - - b[31:0] b[31:0] - - + - - - - rx_lane_decoder_preamble_control 0x00b80100 1 RW uint32 b[0:0] - - - + - - - - rx_preamble_inserter_control 0x00b80140 1 RW uint32 b[0:0] - - - + - - - - rx_frame_control 0x00b80800 1 RW uint32 b[19:0] - - - + - - - - rx_frame_maxlength 0x00b80801 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr0 0x00b80802 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr1 0x00b80803 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_0 0x00b80804 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_1 0x00b80805 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_0 0x00b80806 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_1 0x00b80807 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_0 0x00b80808 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_1 0x00b80809 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_0 0x00b8080a 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_1 0x00b8080b 1 RW uint32 b[15:0] - - - + - - - - rx_pfc_control 0x00b80818 1 RW uint32 b[16:0] - - - + - - - - rx_stats_clr 0x00b80c00 1 RW uint32 b[0:0] - - - + - - - - rx_stats_framesok 0x00b80c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c03 - - - b[31:0] b[31:0] - - + - - - - rx_stats_frameserr 0x00b80c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c05 - - - b[31:0] b[31:0] - - + - - - - rx_stats_framescrcerr 0x00b80c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c07 - - - b[31:0] b[31:0] - - + - - - - rx_stats_octetsok 0x00b80c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c09 - - - b[31:0] b[31:0] - - + - - - - rx_stats_pausemacctrl_frames 0x00b80c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c0b - - - b[31:0] b[31:0] - - + - - - - rx_stats_iferrors 0x00b80c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c0d - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_framesok 0x00b80c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c0f - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_frameserr 0x00b80c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c11 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastframesok 0x00b80c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c13 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicast_frameserr 0x00b80c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c15 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastframesok 0x00b80c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c17 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcast_frameserr 0x00b80c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c19 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatsoctets 0x00b80c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c1b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatspkts 0x00b80c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c1d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_undersizepkts 0x00b80c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c1f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_oversizepkts 0x00b80c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c21 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts64octets 0x00b80c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c23 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts65to127octets 0x00b80c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c25 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts128to255octets 0x00b80c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c27 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts256to511octets 0x00b80c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c29 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts512to1023octets 0x00b80c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c2b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstat_pkts1024to1518octets 0x00b80c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c2d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts1519toxoctets 0x00b80c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c2f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_fragments 0x00b80c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c31 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_jabbers 0x00b80c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c33 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatscrcerr 0x00b80c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c35 - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicastmacctrlframes 0x00b80c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c37 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastmac_ctrlframes 0x00b80c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c39 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastmac_ctrlframes 0x00b80c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c3b - - - b[31:0] b[31:0] - - + - - - - rx_stats_pfcmacctrlframes 0x00b80c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b80c3d - - - b[31:0] b[31:0] - - + - - - - tx_transfer_status 0x00b81001 1 RO uint32 b[0:0] - - - + - - - - tx_padins_control 0x00b81040 1 RW uint32 b[0:0] - - - + - - - - tx_crcins_control 0x00b81080 1 RW uint32 b[1:0] - - - + - - - - tx_pktunderflow_error 0x00b810c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b810c1 - - - b[31:0] b[31:0] - - + - - - - tx_preamble_control 0x00b81100 1 RW uint32 b[0:0] - - - + - - - - tx_pauseframe_control 0x00b81140 1 RW uint32 b[1:0] - - - + - - - - tx_pauseframe_quanta 0x00b81141 1 RW uint32 b[15:0] - - - + - - - - tx_pauseframe_enable 0x00b81142 1 RW uint32 b[0:0] - - - + - - - - pfc_pause_quanta_0 0x00b81180 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_1 0x00b81181 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_2 0x00b81182 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_3 0x00b81183 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_4 0x00b81184 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_5 0x00b81185 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_6 0x00b81186 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_7 0x00b81187 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_0 0x00b81190 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_1 0x00b81191 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_2 0x00b81192 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_3 0x00b81193 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_4 0x00b81194 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_5 0x00b81195 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_6 0x00b81196 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_7 0x00b81197 1 RW uint32 b[31:0] - - - + - - - - tx_pfc_priority_enable 0x00b811a0 1 RW uint32 b[7:0] - - - + - - - - tx_addrins_control 0x00b81200 1 RW uint32 b[0:0] - - - + - - - - tx_addrins_macaddr0 0x00b81201 1 RW uint32 b[31:0] - - - + - - - - tx_addrins_macaddr1 0x00b81202 1 RW uint32 b[15:0] - - - + - - - - tx_frame_maxlength 0x00b81801 1 RW uint32 b[15:0] - - - + - - - - tx_stats_clr 0x00b81c00 1 RW uint32 b[0:0] - - - + - - - - tx_stats_framesok 0x00b81c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c03 - - - b[31:0] b[31:0] - - + - - - - tx_stats_frameserr 0x00b81c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c05 - - - b[31:0] b[31:0] - - + - - - - tx_stats_framescrcerr 0x00b81c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c07 - - - b[31:0] b[31:0] - - + - - - - tx_stats_octetsok 0x00b81c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c09 - - - b[31:0] b[31:0] - - + - - - - tx_stats_pausemacctrl_frames 0x00b81c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c0b - - - b[31:0] b[31:0] - - + - - - - tx_stats_iferrors 0x00b81c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c0d - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_framesok 0x00b81c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c0f - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_frameserr 0x00b81c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c11 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastframesok 0x00b81c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c13 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicast_frameserr 0x00b81c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c15 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastframesok 0x00b81c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c17 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcast_frameserr 0x00b81c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c19 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatsoctets 0x00b81c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c1b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatspkts 0x00b81c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c1d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_undersizepkts 0x00b81c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c1f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_oversizepkts 0x00b81c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c21 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts64octets 0x00b81c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c23 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts65to127octets 0x00b81c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c25 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts128to255octets 0x00b81c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c27 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts256to511octets 0x00b81c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c29 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts512to1023octets 0x00b81c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c2b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstat_pkts1024to1518octets 0x00b81c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c2d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts1519toxoctets 0x00b81c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c2f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_fragments 0x00b81c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c31 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_jabbers 0x00b81c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c33 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatscrcerr 0x00b81c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c35 - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicastmacctrlframes 0x00b81c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c37 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastmac_ctrlframes 0x00b81c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c39 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastmac_ctrlframes 0x00b81c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c3b - - - b[31:0] b[31:0] - - + - - - - tx_stats_pfcmacctrlframes 0x00b81c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00b81c3d - - - b[31:0] b[31:0] - - + REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00c00000 1 RO uint32 b[0:0] - - 1 + - - - - xgmii_tx_ready 0x00c00000 1 RO uint32 b[1:1] - - - + - - - - xgmii_link_status 0x00c00000 1 RO uint32 b[3:2] - - - + REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00c80000 1 WO uint32 b[0:0] - - - + - - - - wr_not_rd 0x00c80001 1 WO uint32 b[0:0] - - - + - - - - done 0x00c80002 1 RO uint32 b[0:0] - - - + - - - - address 0x00c80005 1 WO uint32 b[31:0] - - - + - - - - burstsize 0x00c80006 1 WO uint32 b[31:0] - - - + - - - - flush 0x00c80007 1 RW uint32 b[0:0] - - - + REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00d00000 1 RW uint32 b[2:0] - - - + - - - - init 0x00d00001 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00d00002 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00d00003 1 RW uint32 b[31:0] - - - + REG_DIAG_RX_SEQ_DDR_MB_I 1 1 REG control 0x00d80000 1 RW uint32 b[1:0] - - - + - - - - result 0x00d80001 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00d80002 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00d80003 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00d80004 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00d80005 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00d80006 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00d80007 1 RW uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00e00000 1 RO uint32 b[31:0] - - - + - - - - word_cnt 0x00e00001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00e00400 1024 RW uint32 b[31:0] - - - + REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00e80000 1 WO uint32 b[0:0] - - - + - - - - wr_not_rd 0x00e80001 1 WO uint32 b[0:0] - - - + - - - - done 0x00e80002 1 RO uint32 b[0:0] - - - + - - - - address 0x00e80005 1 WO uint32 b[31:0] - - - + - - - - burstsize 0x00e80006 1 WO uint32 b[31:0] - - - + - - - - flush 0x00e80007 1 RW uint32 b[0:0] - - - + REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00f00000 1 RW uint32 b[2:0] - - - + - - - - init 0x00f00001 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00f00002 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00f00003 1 RW uint32 b[31:0] - - - + REG_DIAG_RX_SEQ_DDR_MB_II 1 1 REG control 0x00f80000 1 RW uint32 b[1:0] - - - + - - - - result 0x00f80001 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00f80002 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00f80003 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00f80004 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00f80005 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00f80006 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00f80007 1 RW uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_DDR_MB_II 1 1 REG sync_cnt 0x01000000 1 RO uint32 b[31:0] - - - + - - - - word_cnt 0x01000001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x01000400 1024 RW uint32 b[31:0] - - - + PIO_JESD_CTRL 1 1 REG enable 0x01080000 1 RW uint32 b[30:0] - - - + - - - - reset 0x01080000 1 RW uint32 b[31:31] - - - + JESD204B 1 12 REG rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - 256 + - - - - rx_syncn_sysref_ctrl 0x01100015 1 RW uint32 b[24:0] - - - + - - - - rx_csr_sysref_always_on 0x01100015 1 RW uint32 b[1:1] - - - + - - - - rx_csr_rbd_offset 0x01100015 1 RW uint32 b[10:3] - - - + - - - - rx_csr_lmfc_offset 0x01100015 1 RW uint32 b[19:12] - - - + - - - - rx_err0 0x01100018 1 RW uint32 b[8:0] - - - + - - - - rx_err1 0x01100019 1 RW uint32 b[9:0] - - - + - - - - csr_dev_syncn 0x01100020 1 RO uint32 b[0:0] - - - + - - - - csr_rbd_count 0x01100020 1 RO uint32 b[10:3] - - - + - - - - rx_status1 0x01100021 1 RW uint32 b[23:0] - - - + - - - - rx_status2 0x01100022 1 RW uint32 b[23:0] - - - + - - - - rx_status3 0x01100023 1 RW uint32 b[7:0] - - - + - - - - rx_ilas_csr_l 0x01100025 1 RW uint32 b[4:0] - - - + - - - - rx_ilas_csr_f 0x01100025 1 RW uint32 b[15:8] - - - + - - - - rx_ilas_csr_k 0x01100025 1 RW uint32 b[20:16] - - - + - - - - rx_ilas_csr_m 0x01100025 1 RW uint32 b[31:24] - - - + - - - - rx_ilas_csr_n 0x01100026 1 RW uint32 b[4:0] - - - + - - - - rx_ilas_csr_cs 0x01100026 1 RW uint32 b[7:6] - - - + - - - - rx_ilas_csr_np 0x01100026 1 RW uint32 b[12:8] - - - + - - - - rx_ilas_csr_subclassv 0x01100026 1 RW uint32 b[15:13] - - - + - - - - rx_ilas_csr_s 0x01100026 1 RW uint32 b[20:16] - - - + - - - - rx_ilas_csr_jesdv 0x01100026 1 RW uint32 b[23:21] - - - + - - - - rx_ilas_csr_cf 0x01100026 1 RW uint32 b[28:24] - - - + - - - - rx_ilas_csr_hd 0x01100026 1 RW uint32 b[31:31] - - - + - - - - rx_status4 0x0110003c 1 RW uint32 b[15:0] - - - + - - - - rx_status5 0x0110003d 1 RW uint32 b[15:0] - - - + - - - - rx_status6 0x0110003e 1 RW uint32 b[23:0] - - - + - - - - rx_status7 0x0110003f 1 RO uint32 b[31:0] - - - + REG_BSN_SOURCE 1 1 REG dp_on 0x01180000 1 RW uint32 b[0:0] - - - + - - - - dp_on_pps 0x01180000 1 RW uint32 b[1:1] - - - + - - - - nof_block_per_sync 0x01180001 1 RW uint32 b[31:0] - - - + - - - - bsn 0x01180002 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x01180003 - - - b[31:0] b[63:32] - - + REG_BSN_MONITOR_INPUT 1 12 REG xon_stable 0x01200000 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x01200000 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x01200000 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x01200001 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x01200002 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x01200003 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x01200004 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x01200005 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x01200006 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x01200007 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x01200008 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x01280000 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x01280001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x01400000 131072 RW uint32 b[31:0] b[15:0] - 131072 \ No newline at end of file diff --git a/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold new file mode 100644 index 0000000000000000000000000000000000000000..1a6fd7ca8c6dc6885306579da9b11ec7756b27ae --- /dev/null +++ b/boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold @@ -0,0 +1,593 @@ +fpga_name = unb2c_test +number_of_columns = 13 +# There can be multiple lines with a single key. The host should ignore unknown keys. +# The lines with columns follow after the number_of_columns keys. The host should ignore +# the extra columns in case the mmap contains more columns than the host expects. +# +# col 1: mm_port_name, if - then it is part of previous MM port. +# col 2: number of peripherals, if - then it is part of previous peripheral. +# col 3: number of mm_ports, if - then it is part of previous MM port. +# col 4: mm_port_type, if - then it is part of previous MM port. +# col 5: field_name +# col 6: field start address (in MM words) +# col 7: number of fields, if - then it is part of previous field_name. +# col 8: field access_mode, if - then it is part of previous field_name. +# col 9: field radix, if - then it is part of previous field_name. +# col 10: field mm_mask +# col 11: field user_mask, if - then it is same as mm_mask +# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port +# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port +# +# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 +# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- ----- + ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - - + PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - - + - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - - + - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - - + - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - - + - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - - + - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - - + - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - - + - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - - + - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - - + - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - - + - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - - + - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - - + - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - - + - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - - + REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - - + REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000da8 1 RO uint32 b[31:0] - - - + REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000d60 6 RO uint32 b[31:0] - - - + RAM_SCRAP 1 1 RAM data 0x00000e00 512 RW uint32 b[31:0] - - - + AVS_ETH_0_TSE 1 1 REG status 0x00000800 1024 RO uint32 b[31:0] - - - + AVS_ETH_0_REG 1 1 REG status 0x00000d40 12 RO uint32 b[31:0] - - - + AVS_ETH_0_RAM 1 1 RAM data 0x00007c00 1024 RW uint32 b[31:0] - - - + PIO_PPS 1 1 REG capture_cnt 0x00000dc0 1 RO uint32 b[29:0] - - - + - - - - stable 0x00000dc0 1 RO uint32 b[30:30] - - - + - - - - toggle 0x00000dc0 1 RO uint32 b[31:31] - - - + - - - - expected_cnt 0x00000dc1 1 RW uint32 b[27:0] - - - + - - - - edge 0x00000dc1 1 RW uint32 b[31:31] - - - + - - - - offset_cnt 0x00000dc2 1 RO uint32 b[27:0] - - - + REG_EPCS 1 1 REG addr 0x00000d98 1 WO uint32 b[23:0] - - - + - - - - rden 0x00000d99 1 WO uint32 b[0:0] - - - + - - - - read_bit 0x00000d9a 1 WO uint32 b[0:0] - - - + - - - - write_bit 0x00000d9b 1 WO uint32 b[0:0] - - - + - - - - sector_erase 0x00000d9c 1 WO uint32 b[0:0] - - - + - - - - busy 0x00000d9d 1 RO uint32 b[0:0] - - - + - - - - unprotect 0x00000d9e 1 WO uint32 b[31:0] - - - + REG_DPMM_CTRL 1 1 REG rd_usedw 0x00000dcc 1 RO uint32 b[31:0] - - - + REG_DPMM_DATA 1 1 FIFO data 0x00000dca 1 RO uint32 b[31:0] - - - + REG_MMDP_CTRL 1 1 REG wr_usedw 0x00000dc8 1 RO uint32 b[31:0] - - - + - - - - wr_availw 0x00000dc9 1 RO uint32 b[31:0] - - - + REG_MMDP_DATA 1 1 FIFO data 0x00000dc6 1 WO uint32 b[31:0] - - - + REG_REMU 1 1 REG reconfigure 0x00000da0 1 WO uint32 b[31:0] - - - + - - - - param 0x00000da1 1 WO uint32 b[2:0] - - - + - - - - read_param 0x00000da2 1 WO uint32 b[0:0] - - - + - - - - write_param 0x00000da3 1 WO uint32 b[0:0] - - - + - - - - data_out 0x00000da4 1 RO uint32 b[23:0] - - - + - - - - data_in 0x00000da5 1 WO uint32 b[23:0] - - - + - - - - busy 0x00000da6 1 RO uint32 b[0:0] - - - + REG_HEATER 1 1 REG enable 0x00000020 25 RW uint32 b[31:0] - - - + REG_DIAG_BG_1GBE 1 1 REG enable 0x00000d90 1 RW uint32 b[0:0] - - - + - - - - enable_sync 0x00000d90 1 RW uint32 b[1:1] - - - + - - - - samples_per_packet 0x00000d91 1 RW uint32 b[31:0] - - - + - - - - blocks_per_sync 0x00000d92 1 RW uint32 b[31:0] - - - + - - - - gapsize 0x00000d93 1 RW uint32 b[31:0] - - - + - - - - mem_low_adrs 0x00000d94 1 RW uint32 b[31:0] - - - + - - - - mem_high_adrs 0x00000d95 1 RW uint32 b[31:0] - - - + - - - - bsn_init 0x00000d96 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x00000d97 - - - b[31:0] b[63:32] - - + RAM_DIAG_BG_1GBE 1 2 RAM data 0x00006000 32 RW uint32 b[31:0] - - 32 + REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00000dbc 1 RW uint32 b[2:0] - - 4 + - - - - init 0x00000dbd 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00000dbe 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00000dbf 1 RW uint32 b[31:0] - - - + REG_BSN_MONITOR_1GBE 1 2 REG xon_stable 0x00000d20 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x00000d20 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x00000d20 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x00000d21 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00000d22 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x00000d23 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x00000d24 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x00000d25 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x00000d26 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00000d27 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x00000d28 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_1GBE 1 2 REG sync_cnt 0x00000d00 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x00000d01 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_1GBE 1 2 RAM data 0x00006800 20 RW uint32 b[31:0] - - 32 + REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00000dbc 1 RW uint32 b[1:0] - - 8 + - - - - result 0x00000dbd 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00000dbe 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00000dbf 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00000dc0 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00000dc1 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00000dc2 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00000dc3 1 RW uint32 b[31:0] - - - + REG_DIAG_BG_10GBE 1 1 REG enable 0x00000d88 1 RW uint32 b[0:0] - - - + - - - - enable_sync 0x00000d88 1 RW uint32 b[1:1] - - - + - - - - samples_per_packet 0x00000d89 1 RW uint32 b[31:0] - - - + - - - - blocks_per_sync 0x00000d8a 1 RW uint32 b[31:0] - - - + - - - - gapsize 0x00000d8b 1 RW uint32 b[31:0] - - - + - - - - mem_low_adrs 0x00000d8c 1 RW uint32 b[31:0] - - - + - - - - mem_high_adrs 0x00000d8d 1 RW uint32 b[31:0] - - - + - - - - bsn_init 0x00000d8e 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x00000d8f - - - b[31:0] b[63:32] - - + RAM_DIAG_BG_10GBE 1 72 RAM data 0x00020000 1024 RW uint32 b[31:0] b[31:0] - 2048 + - - - - - 0x00020001 - - - b[31:0] b[63:32] - - + REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00000d50 1 RW uint32 b[2:0] - - 4 + - - - - init 0x00000d51 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00000d52 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00000d53 1 RW uint32 b[31:0] - - - + REG_BSN_MONITOR_10GBE 1 72 REG xon_stable 0x00007000 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x00007000 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x00007000 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x00007001 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00007002 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x00007003 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x00007004 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x00007005 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x00007006 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00007007 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x00007008 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_10GBE 1 72 REG sync_cnt 0x00000040 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x00000041 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_10GBE 1 72 RAM data 0x00140000 900 RW uint32 b[31:0] b[31:0] - 2048 + - - - - - 0x00140001 - - - b[31:0] b[63:32] - - + REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00000d50 1 RW uint32 b[1:0] - - 8 + - - - - result 0x00000d51 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00000d52 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00000d53 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00000d54 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00000d55 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00000d56 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00000d57 1 RW uint32 b[31:0] - - - + REG_TR_10GBE_QSFP_RING 1 48 REG rx_transfer_control 0x00080000 1 RW uint32 b[0:0] - - 1 + - - - - rx_transfer_status 0x00080001 1 RO uint32 b[0:0] - - - + - - - - tx_transfer_control 0x00080002 1 RW uint32 b[0:0] - - - + - - - - rx_padcrc_control 0x00080040 1 RW uint32 b[1:0] - - - + - - - - rx_crccheck_control 0x00080080 1 RW uint32 b[1:0] - - - + - - - - rx_pktovrflow_error 0x000800c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x000800c1 - - - b[31:0] b[31:0] - - + - - - - rx_pktovrflow_etherstatsdropevents 0x000800c2 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x000800c3 - - - b[31:0] b[31:0] - - + - - - - rx_lane_decoder_preamble_control 0x00080100 1 RW uint32 b[0:0] - - - + - - - - rx_preamble_inserter_control 0x00080140 1 RW uint32 b[0:0] - - - + - - - - rx_frame_control 0x00080800 1 RW uint32 b[19:0] - - - + - - - - rx_frame_maxlength 0x00080801 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr0 0x00080802 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr1 0x00080803 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_0 0x00080804 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_1 0x00080805 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_0 0x00080806 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_1 0x00080807 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_0 0x00080808 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_1 0x00080809 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_0 0x0008080a 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_1 0x0008080b 1 RW uint32 b[15:0] - - - + - - - - rx_pfc_control 0x00080818 1 RW uint32 b[16:0] - - - + - - - - rx_stats_clr 0x00080c00 1 RW uint32 b[0:0] - - - + - - - - rx_stats_framesok 0x00080c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c03 - - - b[31:0] b[31:0] - - + - - - - rx_stats_frameserr 0x00080c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c05 - - - b[31:0] b[31:0] - - + - - - - rx_stats_framescrcerr 0x00080c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c07 - - - b[31:0] b[31:0] - - + - - - - rx_stats_octetsok 0x00080c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c09 - - - b[31:0] b[31:0] - - + - - - - rx_stats_pausemacctrl_frames 0x00080c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c0b - - - b[31:0] b[31:0] - - + - - - - rx_stats_iferrors 0x00080c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c0d - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_framesok 0x00080c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c0f - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_frameserr 0x00080c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c11 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastframesok 0x00080c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c13 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicast_frameserr 0x00080c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c15 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastframesok 0x00080c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c17 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcast_frameserr 0x00080c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c19 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatsoctets 0x00080c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c1b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatspkts 0x00080c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c1d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_undersizepkts 0x00080c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c1f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_oversizepkts 0x00080c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c21 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts64octets 0x00080c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c23 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts65to127octets 0x00080c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c25 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts128to255octets 0x00080c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c27 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts256to511octets 0x00080c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c29 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts512to1023octets 0x00080c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c2b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstat_pkts1024to1518octets 0x00080c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c2d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts1519toxoctets 0x00080c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c2f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_fragments 0x00080c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c31 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_jabbers 0x00080c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c33 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatscrcerr 0x00080c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c35 - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicastmacctrlframes 0x00080c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c37 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastmac_ctrlframes 0x00080c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c39 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastmac_ctrlframes 0x00080c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c3b - - - b[31:0] b[31:0] - - + - - - - rx_stats_pfcmacctrlframes 0x00080c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00080c3d - - - b[31:0] b[31:0] - - + - - - - tx_transfer_status 0x00081001 1 RO uint32 b[0:0] - - - + - - - - tx_padins_control 0x00081040 1 RW uint32 b[0:0] - - - + - - - - tx_crcins_control 0x00081080 1 RW uint32 b[1:0] - - - + - - - - tx_pktunderflow_error 0x000810c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x000810c1 - - - b[31:0] b[31:0] - - + - - - - tx_preamble_control 0x00081100 1 RW uint32 b[0:0] - - - + - - - - tx_pauseframe_control 0x00081140 1 RW uint32 b[1:0] - - - + - - - - tx_pauseframe_quanta 0x00081141 1 RW uint32 b[15:0] - - - + - - - - tx_pauseframe_enable 0x00081142 1 RW uint32 b[0:0] - - - + - - - - pfc_pause_quanta_0 0x00081180 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_1 0x00081181 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_2 0x00081182 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_3 0x00081183 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_4 0x00081184 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_5 0x00081185 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_6 0x00081186 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_7 0x00081187 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_0 0x00081190 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_1 0x00081191 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_2 0x00081192 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_3 0x00081193 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_4 0x00081194 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_5 0x00081195 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_6 0x00081196 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_7 0x00081197 1 RW uint32 b[31:0] - - - + - - - - tx_pfc_priority_enable 0x000811a0 1 RW uint32 b[7:0] - - - + - - - - tx_addrins_control 0x00081200 1 RW uint32 b[0:0] - - - + - - - - tx_addrins_macaddr0 0x00081201 1 RW uint32 b[31:0] - - - + - - - - tx_addrins_macaddr1 0x00081202 1 RW uint32 b[15:0] - - - + - - - - tx_frame_maxlength 0x00081801 1 RW uint32 b[15:0] - - - + - - - - tx_stats_clr 0x00081c00 1 RW uint32 b[0:0] - - - + - - - - tx_stats_framesok 0x00081c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c03 - - - b[31:0] b[31:0] - - + - - - - tx_stats_frameserr 0x00081c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c05 - - - b[31:0] b[31:0] - - + - - - - tx_stats_framescrcerr 0x00081c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c07 - - - b[31:0] b[31:0] - - + - - - - tx_stats_octetsok 0x00081c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c09 - - - b[31:0] b[31:0] - - + - - - - tx_stats_pausemacctrl_frames 0x00081c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c0b - - - b[31:0] b[31:0] - - + - - - - tx_stats_iferrors 0x00081c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c0d - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_framesok 0x00081c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c0f - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_frameserr 0x00081c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c11 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastframesok 0x00081c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c13 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicast_frameserr 0x00081c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c15 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastframesok 0x00081c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c17 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcast_frameserr 0x00081c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c19 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatsoctets 0x00081c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c1b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatspkts 0x00081c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c1d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_undersizepkts 0x00081c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c1f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_oversizepkts 0x00081c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c21 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts64octets 0x00081c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c23 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts65to127octets 0x00081c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c25 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts128to255octets 0x00081c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c27 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts256to511octets 0x00081c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c29 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts512to1023octets 0x00081c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c2b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstat_pkts1024to1518octets 0x00081c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c2d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts1519toxoctets 0x00081c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c2f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_fragments 0x00081c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c31 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_jabbers 0x00081c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c33 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatscrcerr 0x00081c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c35 - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicastmacctrlframes 0x00081c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c37 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastmac_ctrlframes 0x00081c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c39 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastmac_ctrlframes 0x00081c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c3b - - - b[31:0] b[31:0] - - + - - - - tx_stats_pfcmacctrlframes 0x00081c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00081c3d - - - b[31:0] b[31:0] - - + REG_ETH10G_QSFP_RING 1 48 REG tx_snk_out_xon 0x00000080 1 RO uint32 b[0:0] - - 1 + - - - - xgmii_tx_ready 0x00000080 1 RO uint32 b[1:1] - - - + - - - - xgmii_link_status 0x00000080 1 RO uint32 b[3:2] - - - + REG_TR_10GBE_BACK0 1 24 REG rx_transfer_control 0x00100000 1 RW uint32 b[0:0] - - 1 + - - - - rx_transfer_status 0x00100001 1 RO uint32 b[0:0] - - - + - - - - tx_transfer_control 0x00100002 1 RW uint32 b[0:0] - - - + - - - - rx_padcrc_control 0x00100040 1 RW uint32 b[1:0] - - - + - - - - rx_crccheck_control 0x00100080 1 RW uint32 b[1:0] - - - + - - - - rx_pktovrflow_error 0x001000c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x001000c1 - - - b[31:0] b[31:0] - - + - - - - rx_pktovrflow_etherstatsdropevents 0x001000c2 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x001000c3 - - - b[31:0] b[31:0] - - + - - - - rx_lane_decoder_preamble_control 0x00100100 1 RW uint32 b[0:0] - - - + - - - - rx_preamble_inserter_control 0x00100140 1 RW uint32 b[0:0] - - - + - - - - rx_frame_control 0x00100800 1 RW uint32 b[19:0] - - - + - - - - rx_frame_maxlength 0x00100801 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr0 0x00100802 1 RW uint32 b[15:0] - - - + - - - - rx_frame_addr1 0x00100803 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_0 0x00100804 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr0_1 0x00100805 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_0 0x00100806 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr1_1 0x00100807 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_0 0x00100808 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr2_1 0x00100809 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_0 0x0010080a 1 RW uint32 b[15:0] - - - + - - - - rx_frame_spaddr3_1 0x0010080b 1 RW uint32 b[15:0] - - - + - - - - rx_pfc_control 0x00100818 1 RW uint32 b[16:0] - - - + - - - - rx_stats_clr 0x00100c00 1 RW uint32 b[0:0] - - - + - - - - rx_stats_framesok 0x00100c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c03 - - - b[31:0] b[31:0] - - + - - - - rx_stats_frameserr 0x00100c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c05 - - - b[31:0] b[31:0] - - + - - - - rx_stats_framescrcerr 0x00100c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c07 - - - b[31:0] b[31:0] - - + - - - - rx_stats_octetsok 0x00100c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c09 - - - b[31:0] b[31:0] - - + - - - - rx_stats_pausemacctrl_frames 0x00100c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c0b - - - b[31:0] b[31:0] - - + - - - - rx_stats_iferrors 0x00100c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c0d - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_framesok 0x00100c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c0f - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicast_frameserr 0x00100c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c11 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastframesok 0x00100c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c13 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicast_frameserr 0x00100c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c15 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastframesok 0x00100c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c17 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcast_frameserr 0x00100c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c19 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatsoctets 0x00100c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c1b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatspkts 0x00100c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c1d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_undersizepkts 0x00100c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c1f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_oversizepkts 0x00100c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c21 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts64octets 0x00100c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c23 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts65to127octets 0x00100c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c25 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts128to255octets 0x00100c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c27 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts256to511octets 0x00100c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c29 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts512to1023octets 0x00100c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c2b - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstat_pkts1024to1518octets 0x00100c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c2d - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_pkts1519toxoctets 0x00100c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c2f - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_fragments 0x00100c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c31 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstats_jabbers 0x00100c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c33 - - - b[31:0] b[31:0] - - + - - - - rx_stats_etherstatscrcerr 0x00100c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c35 - - - b[31:0] b[31:0] - - + - - - - rx_stats_unicastmacctrlframes 0x00100c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c37 - - - b[31:0] b[31:0] - - + - - - - rx_stats_multicastmac_ctrlframes 0x00100c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c39 - - - b[31:0] b[31:0] - - + - - - - rx_stats_broadcastmac_ctrlframes 0x00100c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c3b - - - b[31:0] b[31:0] - - + - - - - rx_stats_pfcmacctrlframes 0x00100c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00100c3d - - - b[31:0] b[31:0] - - + - - - - tx_transfer_status 0x00101001 1 RO uint32 b[0:0] - - - + - - - - tx_padins_control 0x00101040 1 RW uint32 b[0:0] - - - + - - - - tx_crcins_control 0x00101080 1 RW uint32 b[1:0] - - - + - - - - tx_pktunderflow_error 0x001010c0 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x001010c1 - - - b[31:0] b[31:0] - - + - - - - tx_preamble_control 0x00101100 1 RW uint32 b[0:0] - - - + - - - - tx_pauseframe_control 0x00101140 1 RW uint32 b[1:0] - - - + - - - - tx_pauseframe_quanta 0x00101141 1 RW uint32 b[15:0] - - - + - - - - tx_pauseframe_enable 0x00101142 1 RW uint32 b[0:0] - - - + - - - - pfc_pause_quanta_0 0x00101180 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_1 0x00101181 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_2 0x00101182 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_3 0x00101183 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_4 0x00101184 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_5 0x00101185 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_6 0x00101186 1 RW uint32 b[31:0] - - - + - - - - pfc_pause_quanta_7 0x00101187 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_0 0x00101190 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_1 0x00101191 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_2 0x00101192 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_3 0x00101193 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_4 0x00101194 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_5 0x00101195 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_6 0x00101196 1 RW uint32 b[31:0] - - - + - - - - pfc_holdoff_quanta_7 0x00101197 1 RW uint32 b[31:0] - - - + - - - - tx_pfc_priority_enable 0x001011a0 1 RW uint32 b[7:0] - - - + - - - - tx_addrins_control 0x00101200 1 RW uint32 b[0:0] - - - + - - - - tx_addrins_macaddr0 0x00101201 1 RW uint32 b[31:0] - - - + - - - - tx_addrins_macaddr1 0x00101202 1 RW uint32 b[15:0] - - - + - - - - tx_frame_maxlength 0x00101801 1 RW uint32 b[15:0] - - - + - - - - tx_stats_clr 0x00101c00 1 RW uint32 b[0:0] - - - + - - - - tx_stats_framesok 0x00101c02 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c03 - - - b[31:0] b[31:0] - - + - - - - tx_stats_frameserr 0x00101c04 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c05 - - - b[31:0] b[31:0] - - + - - - - tx_stats_framescrcerr 0x00101c06 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c07 - - - b[31:0] b[31:0] - - + - - - - tx_stats_octetsok 0x00101c08 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c09 - - - b[31:0] b[31:0] - - + - - - - tx_stats_pausemacctrl_frames 0x00101c0a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c0b - - - b[31:0] b[31:0] - - + - - - - tx_stats_iferrors 0x00101c0c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c0d - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_framesok 0x00101c0e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c0f - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicast_frameserr 0x00101c10 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c11 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastframesok 0x00101c12 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c13 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicast_frameserr 0x00101c14 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c15 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastframesok 0x00101c16 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c17 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcast_frameserr 0x00101c18 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c19 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatsoctets 0x00101c1a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c1b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatspkts 0x00101c1c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c1d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_undersizepkts 0x00101c1e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c1f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_oversizepkts 0x00101c20 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c21 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts64octets 0x00101c22 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c23 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts65to127octets 0x00101c24 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c25 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts128to255octets 0x00101c26 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c27 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts256to511octets 0x00101c28 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c29 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts512to1023octets 0x00101c2a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c2b - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstat_pkts1024to1518octets 0x00101c2c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c2d - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_pkts1519toxoctets 0x00101c2e 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c2f - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_fragments 0x00101c30 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c31 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstats_jabbers 0x00101c32 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c33 - - - b[31:0] b[31:0] - - + - - - - tx_stats_etherstatscrcerr 0x00101c34 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c35 - - - b[31:0] b[31:0] - - + - - - - tx_stats_unicastmacctrlframes 0x00101c36 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c37 - - - b[31:0] b[31:0] - - + - - - - tx_stats_multicastmac_ctrlframes 0x00101c38 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c39 - - - b[31:0] b[31:0] - - + - - - - tx_stats_broadcastmac_ctrlframes 0x00101c3a 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c3b - - - b[31:0] b[31:0] - - + - - - - tx_stats_pfcmacctrlframes 0x00101c3c 1 RO uint64 b[3:0] b[35:32] - - + - - - - - 0x00101c3d - - - b[31:0] b[31:0] - - + REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00000c80 1 RO uint32 b[0:0] - - 1 + - - - - xgmii_tx_ready 0x00000c80 1 RO uint32 b[1:1] - - - + - - - - xgmii_link_status 0x00000c80 1 RO uint32 b[3:2] - - - + REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00160000 1 WO uint32 b[0:0] - - - + - - - - wr_not_rd 0x00160001 1 WO uint32 b[0:0] - - - + - - - - done 0x00160002 1 RO uint32 b[0:0] - - - + - - - - address 0x00160005 1 WO uint32 b[31:0] - - - + - - - - burstsize 0x00160006 1 WO uint32 b[31:0] - - - + - - - - flush 0x00160007 1 RW uint32 b[0:0] - - - + REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00000db8 1 RW uint32 b[2:0] - - - + - - - - init 0x00000db9 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00000dba 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00000dbb 1 RW uint32 b[31:0] - - - + REG_DIAG_RX_SEQ_DDR_MB_I 1 1 REG control 0x00000d78 1 RW uint32 b[1:0] - - - + - - - - result 0x00000d79 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00000d7a 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00000d7b 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00000d7c 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00000d7d 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00000d7e 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00000d7f 1 RW uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00000cc0 1 RO uint32 b[31:0] - - - + - - - - word_cnt 0x00000cc1 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00003800 1024 RW uint32 b[31:0] - - - + REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00010000 1 WO uint32 b[0:0] - - - + - - - - wr_not_rd 0x00010001 1 WO uint32 b[0:0] - - - + - - - - done 0x00010002 1 RO uint32 b[0:0] - - - + - - - - address 0x00010005 1 WO uint32 b[31:0] - - - + - - - - burstsize 0x00010006 1 WO uint32 b[31:0] - - - + - - - - flush 0x00010007 1 RW uint32 b[0:0] - - - + REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00000db4 1 RW uint32 b[2:0] - - - + - - - - init 0x00000db5 1 RW uint32 b[31:0] - - - + - - - - tx_cnt 0x00000db6 1 RO uint32 b[31:0] - - - + - - - - modulo 0x00000db7 1 RW uint32 b[31:0] - - - + REG_DIAG_RX_SEQ_DDR_MB_II 1 1 REG control 0x00000d70 1 RW uint32 b[1:0] - - - + - - - - result 0x00000d71 1 RO uint32 b[1:0] - - - + - - - - rx_cnt 0x00000d72 1 RO uint32 b[31:0] - - - + - - - - rx_sample 0x00000d73 1 RO uint32 b[31:0] - - - + - - - - step_0 0x00000d74 1 RW uint32 b[31:0] - - - + - - - - step_1 0x00000d75 1 RW uint32 b[31:0] - - - + - - - - step_2 0x00000d76 1 RW uint32 b[31:0] - - - + - - - - step_3 0x00000d77 1 RW uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_DDR_MB_II 1 1 REG sync_cnt 0x00000c20 1 RO uint32 b[31:0] - - - + - - - - word_cnt 0x00000c21 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x00003000 1024 RW uint32 b[31:0] - - - + PIO_JESD_CTRL 1 1 REG enable 0x00000c02 1 RW uint32 b[30:0] - - - + - - - - reset 0x00000c02 1 RW uint32 b[31:31] - - - + JESD204B 1 12 REG rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - 256 + - - - - rx_syncn_sysref_ctrl 0x00002015 1 RW uint32 b[24:0] - - - + - - - - rx_csr_sysref_always_on 0x00002015 1 RW uint32 b[1:1] - - - + - - - - rx_csr_rbd_offset 0x00002015 1 RW uint32 b[10:3] - - - + - - - - rx_csr_lmfc_offset 0x00002015 1 RW uint32 b[19:12] - - - + - - - - rx_err0 0x00002018 1 RW uint32 b[8:0] - - - + - - - - rx_err1 0x00002019 1 RW uint32 b[9:0] - - - + - - - - csr_dev_syncn 0x00002020 1 RO uint32 b[0:0] - - - + - - - - csr_rbd_count 0x00002020 1 RO uint32 b[10:3] - - - + - - - - rx_status1 0x00002021 1 RW uint32 b[23:0] - - - + - - - - rx_status2 0x00002022 1 RW uint32 b[23:0] - - - + - - - - rx_status3 0x00002023 1 RW uint32 b[7:0] - - - + - - - - rx_ilas_csr_l 0x00002025 1 RW uint32 b[4:0] - - - + - - - - rx_ilas_csr_f 0x00002025 1 RW uint32 b[15:8] - - - + - - - - rx_ilas_csr_k 0x00002025 1 RW uint32 b[20:16] - - - + - - - - rx_ilas_csr_m 0x00002025 1 RW uint32 b[31:24] - - - + - - - - rx_ilas_csr_n 0x00002026 1 RW uint32 b[4:0] - - - + - - - - rx_ilas_csr_cs 0x00002026 1 RW uint32 b[7:6] - - - + - - - - rx_ilas_csr_np 0x00002026 1 RW uint32 b[12:8] - - - + - - - - rx_ilas_csr_subclassv 0x00002026 1 RW uint32 b[15:13] - - - + - - - - rx_ilas_csr_s 0x00002026 1 RW uint32 b[20:16] - - - + - - - - rx_ilas_csr_jesdv 0x00002026 1 RW uint32 b[23:21] - - - + - - - - rx_ilas_csr_cf 0x00002026 1 RW uint32 b[28:24] - - - + - - - - rx_ilas_csr_hd 0x00002026 1 RW uint32 b[31:31] - - - + - - - - rx_status4 0x0000203c 1 RW uint32 b[15:0] - - - + - - - - rx_status5 0x0000203d 1 RW uint32 b[15:0] - - - + - - - - rx_status6 0x0000203e 1 RW uint32 b[23:0] - - - + - - - - rx_status7 0x0000203f 1 RO uint32 b[31:0] - - - + REG_BSN_SOURCE 1 1 REG dp_on 0x00000db0 1 RW uint32 b[0:0] - - - + - - - - dp_on_pps 0x00000db0 1 RW uint32 b[1:1] - - - + - - - - nof_block_per_sync 0x00000db1 1 RW uint32 b[31:0] - - - + - - - - bsn 0x00000db2 1 RW uint64 b[31:0] b[31:0] - - + - - - - - 0x00000db3 - - - b[31:0] b[63:32] - - + REG_BSN_MONITOR_INPUT 1 12 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - 16 + - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - - + - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - - + - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00000102 - - - b[31:0] b[63:32] - - + - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - - + - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - - + - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - - + - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - - + - - - - - 0x00000107 - - - b[31:0] b[63:32] - - + - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - - + REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00001000 1 RO uint32 b[31:0] - - 2 + - - - - word_cnt 0x00001001 1 RO uint32 b[31:0] - - - + RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 131072 RW uint32 b[31:0] b[15:0] - 131072 \ No newline at end of file diff --git a/doc/erko_hdl_design_article.txt b/doc/erko_hdl_design_article.txt index f33018fb8cf93b0123681154e039cd08b261fa8f..4f6b4339456ac650d68d892fe9f6e06fd0a1f2c8 100644 --- a/doc/erko_hdl_design_article.txt +++ b/doc/erko_hdl_design_article.txt @@ -111,10 +111,16 @@ Implementation steps: SIGNAL r : t_reg; SIGNAL nxt_r : t_reg; - . -- Memoryless signals in p_comb (wires used as local auxiliary variables) - SIGNAL s : t_comb; + . -- Memoryless signals and auxiliary variables in p_comb + -- . For unique representation of variables in p_comb as signal wires, the p_comb + -- should assign each field in t_comb only once to a variable. It is allowed to + -- reasign a t_comb variable in p_comb, so use it as a temporary auxiliary + -- variable, but then only the last assignment value will be visible via the + -- signal dbg_wires in the Wave window. + SIGNAL dbg_wires : t_comb; - . -- Structural signals (wires used to connect components and IO) + . -- Structural signals (wires used to connect r, nxt_r to other components and to + -- the entity IO) . -- Pipeline registers SIGNAL in_data_p : ... @@ -135,8 +141,9 @@ Implementation steps: -- State variable VARIABLE v : t_reg; -- Auxiliary variables - VARIABLE v_* -- optional, use to improve code readability - -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ? + --VARIABLE v_* -- optional, use to improve code readability + -- -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ? + VARIABLE w : t_comb; BEGIN v := r; -- default keep existing state v.* := ...; -- default force specific values, e.g. set strobes to '0', @@ -152,7 +159,7 @@ Implementation steps: nxt_r <= v; -- memory less signals, only for view in wave window - s <= d; + dbg_wires <= w; END PROCESS; . -- Pipelining diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg index 573c1a56f9f3c6b1f054c8b8d5af998d8b1ca4cc..6e815027bcfc900a809dc93fecf5bf33026710ee 100644 --- a/libraries/base/common/hdllib.cfg +++ b/libraries/base/common/hdllib.cfg @@ -192,6 +192,7 @@ test_bench_files = tb/vhdl/tb_requantize.vhd tb/vhdl/tb_resize.vhd tb/vhdl/tb_round.vhd + tb/vhdl/tb_common_to_sreal.vhd tb/vhdl/tb_delta_cycle_demo.vhd tb/vhdl/tb_mms_common_variable_delay.vhd @@ -220,6 +221,7 @@ regression_test_vhdl = tb/vhdl/tb_resize.vhd #tb/vhdl/tb_round.vhd -- has no self verification yet tb/vhdl/tb_requantize.vhd + tb/vhdl/tb_common_to_sreal.vhd tb/vhdl/tb_common_pulse_delay.vhd tb/vhdl/tb_tb_common_adder_tree.vhd diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd index e5093bd08e56674e7712ca98d0794a8636bfff1c..55a7a6a8446deaa3f36105b592d966a147a37d67 100644 --- a/libraries/base/common/src/vhdl/common_pkg.vhd +++ b/libraries/base/common/src/vhdl/common_pkg.vhd @@ -370,11 +370,16 @@ PACKAGE common_pkg IS FUNCTION TO_UVEC(dec, w : NATURAL) RETURN STD_LOGIC_VECTOR; FUNCTION TO_SVEC(dec, w : INTEGER) RETURN STD_LOGIC_VECTOR; - + FUNCTION TO_SVEC_32(dec : INTEGER) RETURN STD_LOGIC_VECTOR; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements - - FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR) RETURN REAL; -- convert unsigned slv of any length to REAL - FUNCTION TO_SREAL(svec : STD_LOGIC_VECTOR) RETURN REAL; -- convert signed slv of any length to REAL + + FUNCTION TO_UINT(udec : REAL; w, resolution_w : INTEGER) RETURN NATURAL; -- REAL >= 0 to NATURAL fixed point number + FUNCTION TO_SINT(sdec : REAL; w, resolution_w : INTEGER) RETURN INTEGER; -- REAL to INTEGER fixed point number + FUNCTION TO_UVEC(udec : REAL; w, resolution_w : INTEGER) RETURN STD_LOGIC_VECTOR; -- REAL >= 0 to unsigned SLV fixed point number + FUNCTION TO_SVEC(sdec : REAL; w, resolution_w : INTEGER) RETURN STD_LOGIC_VECTOR; -- REAL to signed SLV fixed point number + + FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR) RETURN REAL; -- convert unsigned slv of any length to REAL, fixed point number with resolution = 1 + FUNCTION TO_SREAL(svec : STD_LOGIC_VECTOR) RETURN REAL; -- convert signed slv of any length to REAL, fixed point number with resolution = 1 FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR; resolution_w : INTEGER) RETURN REAL; -- convert unsigned fixed point slv of any length, and with resolution of 2**resolution_w, to REAL FUNCTION TO_SREAL(svec : STD_LOGIC_VECTOR; resolution_w : INTEGER) RETURN REAL; -- convert signed fixed point slv of any length, and with resolution of 2**resolution_w, to REAL @@ -1807,67 +1812,164 @@ PACKAGE BODY common_pkg IS BEGIN RETURN STD_LOGIC_VECTOR(TO_SIGNED(dec, w)); END; - + FUNCTION TO_SVEC_32(dec : INTEGER) RETURN STD_LOGIC_VECTOR IS BEGIN RETURN TO_SVEC(dec, 32); END; + FUNCTION TO_UINT(udec : REAL; w, resolution_w : INTEGER) RETURN NATURAL IS + CONSTANT c_resolution : REAL := 1.0 / 2.0**REAL(resolution_w); + CONSTANT c_ureal : REAL := ROUND(udec / c_resolution); -- rounds away from zero + BEGIN + IF udec >= 0.0 THEN + RETURN TO_SINT(udec, w + 1, resolution_w); -- w + 1, because unsigned has no sign bit + ELSE + REPORT "Negative REAL clipped to INTEGER 0 : " & REAL'IMAGE(c_ureal) & " --> 0" SEVERITY WARNING; + RETURN 0; + END IF; + END; + + FUNCTION TO_SINT(sdec : REAL; w, resolution_w : INTEGER) RETURN INTEGER IS + CONSTANT c_max : REAL := 2.0**REAL(w - 1) - 1.0; + CONSTANT c_min : REAL := -2.0**REAL(w - 1); + CONSTANT c_resolution : REAL := 1.0 / 2.0**REAL(resolution_w); + CONSTANT c_sreal : REAL := ROUND(sdec / c_resolution); -- rounds away from zero + CONSTANT c_sint : INTEGER := INTEGER(c_sreal); + BEGIN + IF c_sreal >= c_min THEN + IF c_sreal <= c_max THEN + RETURN c_sint; + ELSE + REPORT "REAL clipped to INTEGER max : " & REAL'IMAGE(c_sreal) & " --> " & INTEGER'IMAGE(INTEGER(c_max)) SEVERITY WARNING; + RETURN INTEGER(c_max); -- clip to max + END IF; + ELSE + REPORT "REAL clipped to INTEGER min : " & REAL'IMAGE(c_sreal) & " --> " & INTEGER'IMAGE(INTEGER(c_min)) SEVERITY WARNING; + RETURN INTEGER(c_min); -- clip to min + END IF; + END; + + FUNCTION TO_UVEC(udec : REAL; w, resolution_w : INTEGER) RETURN STD_LOGIC_VECTOR IS + -- Determine range that fits w bits + CONSTANT c_uvec_max : STD_LOGIC_VECTOR(w-1 DOWNTO 0) := (OTHERS => '1'); + CONSTANT c_max : REAL := 2.0**REAL(w) - 1.0; + CONSTANT c_resolution : REAL := 1.0 / 2.0**REAL(resolution_w); + VARIABLE v_ureal : REAL := ROUND(udec / c_resolution); -- rounds away from zero + -- Convert to uvec + VARIABLE v_floor : REAL := 0.0; + VARIABLE v_uvec : STD_LOGIC_VECTOR(w-1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + IF udec >= 0.0 THEN + IF v_ureal <= c_max THEN + -- Avoid using INTEGER, which is limited to 32 bit, by determining per + -- bit whether the REAL value contributes to it. + -- If the REAL, after fixed point scaling by c_resolution, fits in w + -- bits, then the remainer v_floor after w times dividing by 2.0 will + -- be 0.0, because 2**w * 0.5 = 2**(w-1). For example u(4,0) = 7.0 + -- yields: + -- 7.0 / 2 = 3.5 --> [0] = '1' + -- floor(3.5) = 3.0 / 2 = 1.5 --> [1] = '1' + -- floor(1.5) = 1.0 / 2 = 0.5 --> [2] = '1' + -- floor(0.5) = 0.0 / 2 = 0.0 --> [3] = '0' + -- so u(4,0) = 7.0 yields remainder 0.0 and SLV[3:0] = "0111" + -- similar u(4,0) = 8.0 yields remainder 0.5 and SLV[3:0] = "1000" + -- and u(4,0) > 8.0 yields remainder >= 0.5 + FOR I IN 0 TO w-1 LOOP + v_ureal := v_ureal / 2.0; + v_floor := floor(v_ureal); + IF v_ureal > v_floor THEN + v_uvec(I) := '1'; + END IF; + v_ureal := v_floor; + END LOOP; + ASSERT v_floor = 0.0 REPORT "Unexpected TO_UVEC REAL remainder : " & REAL'IMAGE(v_floor) & " /= 0.0" SEVERITY FAILURE; + RETURN v_uvec; + ELSE + REPORT "Positive REAL clipped to UVEC max : " & REAL'IMAGE(v_ureal) & " --> " & REAL'IMAGE(c_max) SEVERITY WARNING; + RETURN c_uvec_max; + END IF; + ELSE + REPORT "Negative REAL clipped to UVEC 0 : " & REAL'IMAGE(v_ureal) & " --> 0" SEVERITY WARNING; + RETURN TO_UVEC(0, w); + END IF; + END; + + FUNCTION TO_SVEC(sdec : REAL; w, resolution_w : INTEGER) RETURN STD_LOGIC_VECTOR IS + -- Determine range that fits w bits + CONSTANT c_svec_max : STD_LOGIC_VECTOR(w-1 DOWNTO 0) := '0' & (w-2 DOWNTO 0 => '1'); + CONSTANT c_svec_min : STD_LOGIC_VECTOR(w-1 DOWNTO 0) := '1' & (w-2 DOWNTO 0 => '0'); + CONSTANT c_max : REAL := 2.0**REAL(w - 1) - 1.0; + CONSTANT c_min : REAL := -2.0**REAL(w - 1); + CONSTANT c_resolution : REAL := 1.0 / 2.0**REAL(resolution_w); + CONSTANT c_sreal : REAL := ROUND(sdec / c_resolution); -- rounds away from zero + -- Convert to positive using TO_UVEC, so if sdec is negative, then + -- negate sdec to have positive c_udec. + CONSTANT c_pos : BOOLEAN := sdec >= 0.0; + CONSTANT c_udec : REAL := sel_a_b(c_pos, sdec, -sdec); + -- Determine SLV value for positive REAL, use w+1 to fit negate of most negative value + CONSTANT c_uvec : STD_LOGIC_VECTOR(w DOWNTO 0) := TO_UVEC(c_udec, w + 1, resolution_w); + -- Back to signed, so if sdec is negative, then negate c_uvec to have positive c_svec + CONSTANT c_svec : STD_LOGIC_VECTOR(w DOWNTO 0) := sel_a_b(c_pos, c_uvec, NEGATE_SVEC(c_uvec)); + BEGIN + IF c_sreal >= c_min THEN + IF c_sreal <= c_max THEN + RETURN c_svec(w-1 DOWNTO 0); + ELSE + REPORT "REAL clipped to SVEC max : " & REAL'IMAGE(c_sreal) & " --> " & REAL'IMAGE(c_max) SEVERITY WARNING; + RETURN c_svec_max; -- clip to max + END IF; + ELSE + REPORT "REAL clipped to SVEC min : " & REAL'IMAGE(c_sreal) & " --> " & REAL'IMAGE(c_min) SEVERITY WARNING; + RETURN c_svec_min; -- clip to min + END IF; + END; + FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR) RETURN REAL IS CONSTANT c_len : NATURAL := uvec'LENGTH; - VARIABLE v_uvec : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0) := uvec; + CONSTANT c_uvec : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0) := uvec; VARIABLE v_real : REAL := 0.0; BEGIN -- Avoid using INTEGER, which is limited to 32 bit, by determining per bit whether it contributes to the REAL value FOR I IN 0 TO c_len-1 LOOP - IF v_uvec(I)='1' THEN - v_real := v_real + 2**REAL(I); + IF c_uvec(I)='1' THEN + v_real := v_real + 2.0**REAL(I); END IF; END LOOP; RETURN v_real; END; FUNCTION TO_SREAL(svec : STD_LOGIC_VECTOR) RETURN REAL IS - CONSTANT c_len : NATURAL := svec'LENGTH + 1; -- use +1 so the v_uvec can also fit abs() of most negative is -1 * -2**(c_len-1) - VARIABLE v_pos : BOOLEAN := TRUE; - VARIABLE v_uvec : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0) := RESIZE_SVEC(svec, c_len); - VARIABLE v_real : REAL := 0.0; - BEGIN - -- Negate svec to have positive v_uvec. - IF SIGNED(svec) < 0 THEN - v_pos := FALSE; - v_uvec := INCR_UVEC(NOT svec, 1); -- negate the svec to make it positive - END IF; + -- Increase vector length by +1 so the c_uvec can also fit abs() of most negative is -1 * -2**(c_len-1) + CONSTANT c_len : NATURAL := svec'LENGTH + 1; + CONSTANT c_svec : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0) := RESIZE_SVEC(svec, c_len); + -- If c_svec is negative, then negate c_svec to have positive c_uvec. + CONSTANT c_pos : BOOLEAN := SIGNED(svec) >= 0; + CONSTANT c_uvec : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0) := sel_a_b(c_pos, c_svec, NEGATE_SVEC(c_svec)); -- Determine REAL value for positive - v_real := TO_UREAL(v_uvec); + CONSTANT c_real : REAL := TO_UREAL(c_uvec); + BEGIN -- Update the sign - IF v_pos THEN - RETURN v_real; - ELSE - RETURN -v_real; - END IF; + RETURN sel_a_b(c_pos, c_real, -c_real); END; FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR; resolution_w : INTEGER) RETURN REAL IS - -- First convert as unsigned integer: - VARIABLE v_real : REAL := TO_UREAL(uvec); BEGIN - -- Then scale to real (see TO_SREAL) - RETURN v_real * 2.0**REAL(resolution_w); + -- First convert as unsigned integer, then scale to real. See TO_SREAL() + -- for interpretation of resolution_w + RETURN TO_UREAL(uvec) / 2.0**REAL(resolution_w); END; FUNCTION TO_SREAL(svec : STD_LOGIC_VECTOR; resolution_w : INTEGER) RETURN REAL IS - -- First convert as signed integer: - VARIABLE v_real : REAL := TO_SREAL(svec); BEGIN - -- Then scale to real: + -- First convert as unsigned integer, then scale to real -- . The resolution_w is the number of bits that LSbit 0 in svec(HIGH-1 DOWNTO 0) is after -- (when resolution_w > 0), or before (when resolution_w < 0) the fixed point. - -- . The real value is then scaled by scaling the integer value by 2**(-1 * resolution_w): + -- . The real value is then scaled by scaling the integer value by 1.0 / 2**(resolution_w): -- . resolution_w = 0 : scale by 2**0 = 1, so no scaling and the value is treated as an integer -- . resolution_w < 0 : scale up -- . resolution_w > 0 : scale down - RETURN v_real * 2.0**REAL(-1 * resolution_w); + RETURN TO_SREAL(svec) / 2.0**REAL(resolution_w); END; @@ -1931,7 +2033,10 @@ PACKAGE BODY common_pkg IS FUNCTION NEGATE_SVEC(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN -- use NUMERIC_STD to avoid range limitation of 32b INTEGER + -- default approach RETURN STD_LOGIC_VECTOR(-SIGNED(vec)); -- negate by multiplying by -1 + -- alternative equivalent approach + -- RETURN INCR_UVEC(NOT vec, 1); -- negate by using two complement negate END; -- Negate vec, but avoid overflow by forcing -min to +max. Use w <= vec'LENGTH. diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd new file mode 100644 index 0000000000000000000000000000000000000000..302b0b85dce3b85c575cfec017a3f356eaa64cce --- /dev/null +++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd @@ -0,0 +1,191 @@ +-- -------------------------------------------------------------------------- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- -------------------------------------------------------------------------- +-- +-- Author: E. Kooistra, 13 okt 2021 +-- Purpose: Verify to_sreal() and to_svec() from common_pkg.vhd +-- Description: +-- The tb shows how a REAL value is represented by a fixed point SLV. The +-- signed REAL value is denoted as s(w, p) as defined and explained in []: +-- +-- s = sign bit, value +1 or -1 +-- w = width in number of bits of the SLV +-- p = position of the fixed point in the SLV, p = 0 for integers, p > 0 +-- for p bit fraction, p < 0 for scale factor 2**p +-- +-- The resolution of the REAL value is r = 1/2**p. +-- +-- . to_svec() converts a fixed point INTEGER or SLV into a REAL value +-- . to_sreal() converts a REAL value into a fixed point SLV or INTEGER +-- +-- The tb verifies that a_slv(w-1:0) = to_svec(to_sreal(a_slv(w-1:0))). +-- +-- References: +-- [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers +-- +-- Usage: +-- > as 5, observe signed signals with radix decimal, and observe unsigned +-- signals with radix unsigend. +-- > run -all +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE work.common_pkg.ALL; + + +ENTITY tb_common_to_sreal IS +END tb_common_to_sreal; + +ARCHITECTURE tb OF tb_common_to_sreal IS + + CONSTANT clk_period : TIME := 10 ns; + + CONSTANT c_resolution_w : NATURAL := 5; + CONSTANT c_width : NATURAL := 4; + CONSTANT c_min : INTEGER := -2**(c_width-1); + CONSTANT c_max : INTEGER := 2**(c_width-1)-1; + + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC := '1'; + SIGNAL rst : STD_LOGIC := '1'; + + SIGNAL a_real : REAL := 0.0; + SIGNAL a_sint : INTEGER := 0; + SIGNAL a_uint : NATURAL := 0; + SIGNAL a_slv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); -- signed slv + SIGNAL a_ulv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); -- unsigned slv + SIGNAL dbg_resolution_w : INTEGER := 0; + SIGNAL dbg_resolution : REAL := 0.0; + + PROCEDURE proc_wait_some_cycles(SIGNAL clk : IN STD_LOGIC; + c_nof_cycles : IN NATURAL) IS + BEGIN + FOR I IN 0 TO c_nof_cycles-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP; + END proc_wait_some_cycles; + +BEGIN + + -- Stimuli + clk <= NOT clk OR tb_end AFTER clk_period/2; + rst <= '1', '0' AFTER 3*clk_period; + + -- Testbench end + p_tb : PROCESS + VARIABLE v_slv : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE v_real : REAL; + BEGIN + -- Simulator evaluates process until first WAIT at startup 0 ps, but + -- simulator does not recognise WAIT in proc_wait_some_cycles() then. + -- Therefore add WAIT here to avoid ASSERT messages that occur later. + WAIT UNTIL rising_edge(clk); + proc_wait_some_cycles(clk, 10); + + -- Try all v_slv for c_width and resolutions beyond c_width + FOR R IN -c_resolution_w TO c_resolution_w LOOP + dbg_resolution_w <= R; + dbg_resolution <= 1.0 / 2.0**REAL(R); + FOR I IN c_min TO c_max LOOP + v_slv := TO_SVEC(I, c_width); + -- Convert fixed point v_slv with binary point at resolution width R, to real and back to slv + v_real := TO_SREAL(v_slv, R); + -- Show as signals in Wave window + a_real <= v_real; + a_sint <= TO_SINT(v_real, c_width, R); + a_slv <= TO_SVEC(v_real, c_width, R); + IF I >= 0 THEN + a_uint <= TO_UINT(v_real, c_width, R); + a_ulv <= TO_UVEC(v_real, c_width, R); + END IF; + WAIT UNTIL rising_edge(clk); + -- Verify + ASSERT a_sint = I REPORT "Wrong REAL to INTEGER conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR; + ASSERT a_slv = v_slv REPORT "Wrong REAL to SLV conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR; + IF I >= 0 THEN + ASSERT a_uint = I REPORT "Wrong REAL to NATURAL conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR; + ASSERT a_ulv = v_slv REPORT "Wrong REAL to unsigned SLV conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR; + END IF; + END LOOP; + proc_wait_some_cycles(clk, 10); + END LOOP; + + proc_wait_some_cycles(clk, 10); + + -- Try overflow + -- . No overflow with 4 bit integers for -16.49 : +15.49 + v_real := -9.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -9.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -8.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -8.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + proc_wait_some_cycles(clk, 5); + + -- . Just overflow with 4 bit integers for -16.5 : +15.5 + v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + proc_wait_some_cycles(clk, 5); + + -- . Negative clip to 0 for unsigned + v_real := -3.0; a_real <= v_real; a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + ASSERT a_uint = 0 REPORT "Unexpected TO_UINT(< 0) : " & INTEGER'IMAGE(a_uint) & " /= 0" SEVERITY ERROR; + ASSERT TO_UINT(a_ulv) = 0 REPORT "Unexpected TO_UVEC(< 0) : " & INTEGER'IMAGE(TO_UINT(a_ulv)) & " /= 0" SEVERITY ERROR; + + proc_wait_some_cycles(clk, 5); + -- . Large overflow with 4 bit integers for << -16.5 : >> +15.5 + v_real := -68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + v_real := 68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk); + + proc_wait_some_cycles(clk, 10); + tb_end <= '1'; + WAIT; + END PROCESS; + + -- TO_SINT() and TO_SVEC() must always yield same result + ASSERT a_sint = TO_SINT(a_slv) REPORT "Unexpected difference between TO_SINT() and TO_SVEC() :" & + INTEGER'IMAGE(a_sint) & " /= " & INTEGER'IMAGE(TO_SINT(a_slv)) SEVERITY ERROR; + + -- TO_UINT() and TO_UVEC() must always yield same result + ASSERT a_uint = TO_UINT(a_ulv) REPORT "Unexpected difference between TO_UINT() and TO_UVEC() :" & + INTEGER'IMAGE(a_uint) & " /= " & INTEGER'IMAGE(TO_SINT(a_ulv)) SEVERITY ERROR; +END tb; diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml index 8081e7e15c2f3168838d7ac8112d02f52d705ccb..ec4f28671473375570d764b2d7df883483f142e3 100644 --- a/libraries/base/diag/diag.peripheral.yaml +++ b/libraries/base/diag/diag.peripheral.yaml @@ -31,22 +31,22 @@ peripherals: 1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase 2 = repeat, outputs WG buffer waveform repeatedly 3 = single, outputs WG buffer waveform once" - address_offset: 0x0 + address_offset: 0 * MM_BUS_SIZE bit_offset: 0 mm_width: 8 - - field_name: phase field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)." - address_offset: 0x4 + address_offset: 1 * MM_BUS_SIZE bit_offset: 0 mm_width: 16 - - field_name: freq field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz." - address_offset: 0x8 + address_offset: 2 * MM_BUS_SIZE bit_offset: 0 mm_width: 31 - - field_name: ampl field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping." - address_offset: 0xC + address_offset: 3 * MM_BUS_SIZE bit_offset: 0 mm_width: 17 # MM port for mms_diag_wg_wideband.vhd @@ -59,7 +59,7 @@ peripherals: - - field_name: data field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)." number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd - address_offset: 0x0 + address_offset: 0 * MM_BUS_SIZE mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd - peripheral_name: diag_data_buffer # pi_diag_data_buffer.py @@ -80,11 +80,11 @@ peripherals: fields: - - field_name: sync_cnt field_description: "Number of times the DB has been written." - address_offset: 0x0 + address_offset: 0 * MM_BUS_SIZE access_mode: RO - - field_name: word_cnt field_description: "Number data words in the DB." - address_offset: 0x4 + address_offset: 1 * MM_BUS_SIZE access_mode: RO # MM port for mms_diag_data_buffer.vhd - mm_port_name: RAM_DIAG_DB @@ -96,6 +96,170 @@ peripherals: - - field_name: data field_description: "" number_of_fields: g_nof_data - address_offset: 0x0 - mm_width: g_data_w - + address_offset: 0 * MM_BUS_SIZE + user_width: g_data_w + + - peripheral_name: diag_block_gen # pi_diag_block_gen.py + peripheral_description: "Block generator (BG)" + parameters: + # Parameters of mms_diag_block_gen.vhd + - { name: g_nof_streams, value: 1 } + - { name: g_buf_dat_w, value: 16 } + - { name: g_buf_addr_w, value: 7 } + mm_ports: + # MM port for mms_diag_block_gen.vhd + - mm_port_name: REG_DIAG_BG + mm_port_type: REG + mm_port_span: 8 * MM_BUS_SIZE + mm_port_description: "Block generator control." + number_of_mm_ports: 1 + fields: + - - field_name: enable + field_description: "Starts the block generator." + address_offset: 0 * MM_BUS_SIZE + bit_offset: 0 + mm_width: 1 + - - field_name: enable_sync + field_description: "Starts the block generator at the next sync pulse when enable is set to 1." + address_offset: 0 * MM_BUS_SIZE + bit_offset: 1 + mm_width: 1 + - - field_name: samples_per_packet + field_description: "Number of samples per packet." + address_offset: 1 * MM_BUS_SIZE + - - field_name: blocks_per_sync + field_description: "Number blocks per sync interval." + address_offset: 2 * MM_BUS_SIZE + - - field_name: gapsize + field_description: "The gap size between blocks in clock cycles." + address_offset: 3 * MM_BUS_SIZE + - - field_name: mem_low_adrs + field_description: "Start address of memory to use for block generator" + address_offset: 4 * MM_BUS_SIZE + - - field_name: mem_high_adrs + field_description: "End address of memory to use for block generator." + address_offset: 5 * MM_BUS_SIZE + - - field_name: bsn_init + field_description: "Initial BSN." + address_offset: 6 * MM_BUS_SIZE + user_width: 64 + radix: uint64 + + # MM port for mms_diag_block_gen.vhd + - mm_port_name: RAM_DIAG_BG + mm_port_type: RAM + mm_port_span: ceil_pow2( 2**g_buf_addr_w * ceil_div(g_buf_dat_w, c_word_w)) * MM_BUS_SIZE + mm_port_description: "Block generator buffer memory, contains the data patterns to be generated." + number_of_mm_ports: g_nof_streams + fields: + - - field_name: data + field_description: "Block generator buffer memory." + number_of_fields: 2**g_buf_addr_w + address_offset: 0 * MM_BUS_SIZE + user_width: g_buf_dat_w + + - peripheral_name: diag_tx_seq # pi_diag_tx_seq.py + peripheral_description: "TX test sequence" + parameters: + # Parameters of mms_diag_tx_seq.vhd + - { name: g_nof_streams, value: 1 } + - { name: g_mm_broadcast, value: False } + mm_ports: + # MM port for mms_diag_tx_seq.vhd + - mm_port_name: REG_DIAG_TX_SEQ + mm_port_type: REG + mm_port_span: 4 * MM_BUS_SIZE + mm_port_description: "TX test sequence control." + number_of_mm_ports: sel_a_b(g_mm_broadcast, 1, g_nof_streams) + fields: + - - field_name: control + field_description: | + "Control register containing diag_dc = [2], diag_sel = [1], diag_en = [0]. + diag_en + '0' = init and disable output sequence + '1' = enable output sequence + diag_sel + '0' = generate PSRG data + '1' = generate CNTR data + diag_dc + '0' = Output sequence data (as selected by diag_sel) + '1' = Output constant data (value as set by diag_init)" + address_offset: 0 * MM_BUS_SIZE + mm_width: 3 + - - field_name: init + field_description: "Initial data value." + address_offset: 1 * MM_BUS_SIZE + - - field_name: tx_cnt + field_description: | + "Counts the number of valid output data that was transmitted on stream 0 + since diag_en went active. An incrementing tx_cnt shows that data is + being transmitted." + address_offset: 2 * MM_BUS_SIZE + access_mode: RO + - - field_name: modulo + field_description: "A modulo can be used with CNTR data which results in a sequence with values of (cnt MOD modulo)" + address_offset: 3 * MM_BUS_SIZE + + - peripheral_name: diag_rx_seq # pi_diag_rx_seq.py + peripheral_description: "RX test sequence" + parameters: + # Parameters of mms_diag_rx_seq.vhd + - { name: g_nof_streams, value: 1 } + mm_ports: + # MM port for mms_diag_rx_seq.vhd + - mm_port_name: REG_DIAG_RX_SEQ + mm_port_type: REG + mm_port_span: 8 * MM_BUS_SIZE + mm_port_description: "RX test sequence control." + number_of_mm_ports: g_nof_streams + fields: + - - field_name: control + field_description: | + "Control register containing diag_sel = [1], diag_en = [0]. + diag_en + '0' = stop and reset input sequence verification + '1' = enable input sequence verification + diag_sel + '0' = verify PSRG data + '1' = verify CNTR data" + address_offset: 0 * MM_BUS_SIZE + mm_width: 2 + - - field_name: result + field_description: | + "result register containing res_val_n = [1], res_ok_n = [0]. + res_val_n + '0' = No valid data is being received. + '1' = At least two valid data have been received. + res_ok_n + '0' = All data that has been received so far is correct. + '1' = At least 1 data word was received with errors" + address_offset: 1 * MM_BUS_SIZE + access_mode: RO + mm_width: 2 + - - field_name: rx_cnt + field_description: | + "the number of valid input data that was received since diag_en + went active. An incrementing rx_cnt shows that data is being received." + address_offset: 2 * MM_BUS_SIZE + access_mode: RO + - - field_name: rx_sample + field_description: | + "The rx_sample keeps the last valid in_dat value. When diag_en='0' it is + reset to 0. Reading rx_sample via MM gives an impression of the valid + in_dat activity." + address_offset: 3 * MM_BUS_SIZE + access_mode: RO + - - field_name: step_0 + field_description: "step_0 = diag_steps_arr[0] which defines the allowed COUNTER increment values" + address_offset: 4 * MM_BUS_SIZE + - - field_name: step_1 + field_description: "step_1 = diag_steps_arr[1] which defines the allowed COUNTER increment values" + address_offset: 5 * MM_BUS_SIZE + - - field_name: step_2 + field_description: "step_2 = diag_steps_arr[2] which defines the allowed COUNTER increment values" + address_offset: 6 * MM_BUS_SIZE + - - field_name: step_3 + field_description: "step_3 = diag_steps_arr[3] which defines the allowed COUNTER increment values" + address_offset: 7 * MM_BUS_SIZE + + diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml index d8d9608200d771b0c21ab97fe5e6be2860649253..ee3a7a47297301add7cc24d3007f258f4b36a963 100644 --- a/libraries/base/dp/dp.peripheral.yaml +++ b/libraries/base/dp/dp.peripheral.yaml @@ -358,7 +358,7 @@ peripherals: - - field_name: sync_timeout field_description: "Data stream sync did not occur during last sync interval." address_offset: 0x0 - bit_offset: 1 + bit_offset: 2 mm_width: 1 access_mode: RO - - field_name: bsn_at_sync diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd index 37b58b49b76f0b9a8cdf48339be448a2de30a941..795c772f562a4c8e01bd747ff4e3c6bc49016fed 100644 --- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd +++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd @@ -124,7 +124,11 @@ BEGIN IF r.busy = '0' AND start_pulse = '1' THEN -- initiate next block v.busy := '1'; - ELSIF r.busy = '1' THEN + END IF; + + -- use v.busy, instead of r.busy, to allow start_pulse at mm_done, to + -- support zero gaps between output blocks + IF v.busy = '1' THEN IF out_siso.ready = '1' THEN -- continue with block mm_mosi.rd <= '1'; diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd index 87dcb99739f0d7daec770140c9dc65d42511126d..e94cd4efd070011f1e89c84d1ca3ffdd8a6c89ed 100644 --- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd +++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd @@ -26,13 +26,17 @@ -- input stream that is ahead of the other remote input streams. After a -- certain number of blocks on input 0, the same block on all remote -- inputs should also have arrived. If not then they are replaced by --- replacement data. The output streams are paced by the block rate of input 0. --- The user has to read the block within the block period. +-- replacement data. The output streams are paced by the block rate of +-- input 0. The user has to read the block within the block period. -- -- Features: --- . uses lost_data flag and replacement data to replace lost input blocks +-- . The g_block_size <= block period, so supports input blocks arriving +-- with or without data valid gaps +-- . uses replacement data to replace lost input blocks and channel bit 0 as +-- lost_data flag -- . uses replacement data to replace disabled input streams --- . output block can be read in arbitrary order +-- . output block can be read in arbitrary order via g_use_mm_output = TRUE +-- . output block can be streamed via g_use_mm_output = FALSE -- -- For more detailed description see: -- https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+aligner+v2 @@ -53,22 +57,23 @@ USE work.dp_stream_pkg.ALL; ENTITY dp_bsn_align_v2 IS GENERIC ( - g_nof_streams : NATURAL; -- number of input and output streams - g_bsn_latency_max : NATURAL; -- Maximum travel latency of a remote block in number of block periods T_blk + g_nof_streams : NATURAL; -- >= 2, number of input and output streams + g_bsn_latency_max : NATURAL; -- maximum travel latency of a remote block in number of block periods T_blk g_nof_aligners_max : POSITIVE := 1; -- 1 when only align at last node, > 1 when align at every intermediate node g_block_size : NATURAL := 32; -- > 1, g_block_size=1 is not supported g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_data_w : NATURAL; -- number of bits in sosi data - g_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks + g_data_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP - g_pipeline_input : NATURAL := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure - g_rd_latency : NATURAL := 1 -- 1 or 2, choose 2 to ease timing closure + g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr + g_pipeline_output : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr + g_rd_latency : NATURAL := 2 -- 1 or 2, choose 2 to ease timing closure ); PORT ( dp_rst : IN STD_LOGIC; dp_clk : IN STD_LOGIC; - node_index : IN NATURAL RANGE 0 TO g_nof_aligners_max := 0; -- only used when g_nof_aligners_max > 1 + node_index : IN NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0; -- only used when g_nof_aligners_max > 1 -- MM control stream_en_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1'); @@ -89,8 +94,8 @@ END dp_bsn_align_v2; ARCHITECTURE rtl OF dp_bsn_align_v2 IS - -- Circular buffer per stream - CONSTANT c_buffer_nof_blocks : NATURAL := ceil_pow2(1 + g_nof_aligners_max * g_bsn_latency_max); + -- Circular buffer per stream, size is next power of 2 that fits + CONSTANT c_buffer_nof_blocks : NATURAL := true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max); CONSTANT c_ram_size : NATURAL := c_buffer_nof_blocks * g_block_size; CONSTANT c_ram_buf : t_c_mem := (latency => 1, @@ -107,13 +112,18 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS -- avoid that synthesis may infer a too larger multiplier CONSTANT c_product_w : NATURAL := c_blk_pointer_w + c_block_size_w; + -- Output on lost data flag via out_sosi_arr().channel bit 0 + CONSTANT c_channel_w : NATURAL := 1; + TYPE t_bsn_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0); + TYPE t_channel_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_channel_w-1 DOWNTO 0); TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0); TYPE t_filled_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_buffer_nof_blocks-1 DOWNTO 0); + -- State TYPE t_reg IS RECORD -- p_write_arr - wr_pointer : NATURAL; + wr_blk_pointer : NATURAL; wr_copi_arr : t_mem_copi_arr(g_nof_streams-1 DOWNTO 0); -- all streams filled_arr : t_filled_arr(g_nof_streams-1 DOWNTO 0); @@ -124,19 +134,25 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS mm_sosi : t_dp_sosi; dp_sosi : t_dp_sosi; -- p_read - rd_pointer : INTEGER; -- use integer to detect need to wrap to natural + rd_blk_pointer : INTEGER; -- use integer to detect need to wrap to natural rd_offset : STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0); rd_copi : t_mem_copi; fill_cipo_arr : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data - out_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0); -- hold BSN for streaming output + out_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0); -- hold BSN until next sop, for easy view in Wave window + out_channel_arr : t_channel_arr(g_nof_streams-1 DOWNTO 0); -- hold channel until next sop per stream, for easy view in Wave window END RECORD; + -- Wires and auxiliary variables in p_comb + -- . For unique representation as signal wire, the p_comb should assign each + -- field in t_comb only once to a variable. It is allowed to reasign a + -- t_comb variable in p_comb, but then only the last assignment value will + -- be visible via the signal dbg_wires in the Wave window. TYPE t_comb IS RECORD - ref_sosi : t_dp_sosi; - pointer_slv : STD_LOGIC_VECTOR(c_blk_pointer_w-1 DOWNTO 0); - product_slv : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0); - lost_data_flag : STD_LOGIC; - out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + ref_sosi : t_dp_sosi; + blk_pointer_slv : STD_LOGIC_VECTOR(c_blk_pointer_w-1 DOWNTO 0); + product_slv : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0); + lost_data_flags_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); + out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); END RECORD; CONSTANT c_reg_rst : t_reg := (0, @@ -151,45 +167,48 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS (OTHERS=>'0'), c_mem_copi_rst, (OTHERS=>c_mem_cipo_rst), - (OTHERS=>'0')); + (OTHERS=>'0'), + (OTHERS=>(OTHERS=>'0'))); -- State registers for p_comb - SIGNAL r : t_reg; - SIGNAL nxt_r : t_reg; + SIGNAL r : t_reg; + SIGNAL nxt_r : t_reg; - -- Memoryless signals in p_comb (wires used as local auxiliary variables) - SIGNAL s : t_comb; + -- Memoryless signals in p_comb (wires used as local variables) + SIGNAL dbg_wires : t_comb; -- Structural signals (wires used to connect components and IO) - SIGNAL dp_done : STD_LOGIC; - SIGNAL dp_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); - SIGNAL dp_copi : t_mem_copi; - SIGNAL dp_copi_arr : t_mem_copi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL dp_done : STD_LOGIC; + SIGNAL dp_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); + SIGNAL dp_copi : t_mem_copi; + SIGNAL dp_copi_arr : t_mem_copi_arr(g_nof_streams-1 DOWNTO 0); - SIGNAL rd_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - SIGNAL rd_cipo_arr : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_mem_cipo_rst); + SIGNAL rd_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL rd_cipo_arr : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_mem_cipo_rst); -- Pipeline registers - SIGNAL in_sosi_arr_p : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - SIGNAL rd_copi : t_mem_copi; + SIGNAL in_sosi_arr_p : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL rd_copi : t_mem_copi; + SIGNAL comb_out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Debug signals - SIGNAL dbg_nof_streams : NATURAL := g_nof_streams; - SIGNAL dbg_bsn_latency_max : NATURAL := g_bsn_latency_max; - SIGNAL dbg_nof_aligners_max : NATURAL := g_nof_aligners_max; - SIGNAL dbg_block_size : NATURAL := g_block_size; - SIGNAL dbg_bsn_w : NATURAL := g_bsn_w; - SIGNAL dbg_data_w : NATURAL := g_data_w; - SIGNAL dbg_replacement_value : INTEGER := g_replacement_value; - SIGNAL dbg_use_mm_output : BOOLEAN := g_use_mm_output; - SIGNAL dbg_pipeline_input : NATURAL := g_pipeline_input; - SIGNAL dbg_rd_latency : NATURAL := g_rd_latency; - SIGNAL dbg_c_buffer_nof_blocks : NATURAL := c_buffer_nof_blocks; - SIGNAL dbg_c_product_w : NATURAL := c_product_w; + SIGNAL dbg_nof_streams : NATURAL := g_nof_streams; + SIGNAL dbg_bsn_latency_max : NATURAL := g_bsn_latency_max; + SIGNAL dbg_nof_aligners_max : NATURAL := g_nof_aligners_max; + SIGNAL dbg_block_size : NATURAL := g_block_size; + SIGNAL dbg_bsn_w : NATURAL := g_bsn_w; + SIGNAL dbg_data_w : NATURAL := g_data_w; + SIGNAL dbg_data_replacement_value : INTEGER := g_data_replacement_value; + SIGNAL dbg_use_mm_output : BOOLEAN := g_use_mm_output; + SIGNAL dbg_pipeline_input : NATURAL := g_pipeline_input; + SIGNAL dbg_rd_latency : NATURAL := g_rd_latency; + SIGNAL dbg_c_buffer_nof_blocks : NATURAL := c_buffer_nof_blocks; + SIGNAL dbg_c_product_w : NATURAL := c_product_w; BEGIN - mm_sosi <= r.mm_sosi WHEN g_use_mm_output = TRUE ELSE c_dp_sosi_rst; + -- Output mm_sosi, also when g_use_mm_output = FALSE. + mm_sosi <= r.mm_sosi; p_reg : PROCESS(dp_clk, dp_rst) BEGIN @@ -202,7 +221,7 @@ BEGIN p_comb : PROCESS(r, in_sosi_arr_p, mm_copi, dp_copi, rd_cipo_arr, rd_sosi_arr) VARIABLE v : t_reg; -- State variable - VARIABLE d : t_comb; -- Memoryless auxiliary variables, local wires + VARIABLE w : t_comb; -- Local wires = memoryless auxiliary variables BEGIN v := r; -- state signals v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi); @@ -222,56 +241,57 @@ BEGIN IF in_sosi_arr_p(I).sop = '1' THEN -- . set address at start of block - d.pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0); - d.product_slv := MULT_UVEC(d.pointer_slv, c_block_size_slv); - v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(d.product_slv); + w.blk_pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0); + w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv); + v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(w.product_slv); -- . set filled flag at sop, so assume rest of block will follow in time - v.filled_arr(I)(TO_UINT(d.pointer_slv)) := '1'; + v.filled_arr(I)(TO_UINT(w.blk_pointer_slv)) := '1'; END IF; END LOOP; ---------------------------------------------------------------------------- -- p_control, all at sop of local reference input 0 ---------------------------------------------------------------------------- - d.ref_sosi := in_sosi_arr_p(0); - IF d.ref_sosi.sop = '1' THEN + w.ref_sosi := in_sosi_arr_p(0); + IF w.ref_sosi.sop = '1' THEN -- . write sync & bsn buffer - v.wr_pointer := TO_UINT(d.ref_sosi.bsn(c_blk_pointer_w-1 DOWNTO 0)); - v.sync_arr(v.wr_pointer) := d.ref_sosi.sync; - v.bsn_arr(v.wr_pointer) := d.ref_sosi.bsn(g_bsn_w-1 DOWNTO 0); - - -- . update read block pointer at g_bsn_latency_max blocks behind the reference write pointer - IF g_nof_aligners_max = 1 THEN - v.rd_pointer := v.wr_pointer - g_bsn_latency_max; - ELSE - v.rd_pointer := v.wr_pointer - g_bsn_latency_max * node_index; - END IF; - IF v.rd_pointer < 0 THEN - v.rd_pointer := v.rd_pointer + c_buffer_nof_blocks; + v.wr_blk_pointer := TO_UINT(w.ref_sosi.bsn(c_blk_pointer_w-1 DOWNTO 0)); + v.sync_arr(v.wr_blk_pointer) := w.ref_sosi.sync; + v.bsn_arr(v.wr_blk_pointer) := w.ref_sosi.bsn(g_bsn_w-1 DOWNTO 0); + + -- . update read block pointer at g_bsn_latency_max blocks behind the + -- reference write pointer, dependent on the node_index. For + -- g_bsn_latency_max = 1 the node_index = 0 fixed. For + -- g_bsn_latency_max > 1, node_index is the first BSN aligner in a + -- chain. Each subsequent node in the chain then has to account for + -- g_bsn_latency_max additional block latency. + v.rd_blk_pointer := v.wr_blk_pointer - g_bsn_latency_max * (1 + node_index); + IF v.rd_blk_pointer < 0 THEN + v.rd_blk_pointer := v.rd_blk_pointer + c_buffer_nof_blocks; END IF; -- . update read address of read block pointer - d.pointer_slv := TO_UVEC(v.rd_pointer, c_blk_pointer_w); - d.product_slv := MULT_UVEC(d.pointer_slv, c_block_size_slv); - v.rd_offset := RESIZE_UVEC(d.product_slv, c_mem_ram.adr_w); + w.blk_pointer_slv := TO_UVEC(v.rd_blk_pointer, c_blk_pointer_w); + w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv); + v.rd_offset := RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w); -- . issue mm_sosi, if there is output ready to be read, indicated by filled reference block - IF r.filled_arr(0)(v.rd_pointer) = '1' THEN + IF r.filled_arr(0)(v.rd_blk_pointer) = '1' THEN v.mm_sosi.sop := '1'; v.mm_sosi.eop := '1'; v.mm_sosi.valid := '1'; -- . pass on timestamp information - v.mm_sosi.sync := v.sync_arr(v.rd_pointer); - v.mm_sosi.bsn := RESIZE_DP_BSN(v.bsn_arr(v.rd_pointer)); + v.mm_sosi.sync := v.sync_arr(v.rd_blk_pointer); + v.mm_sosi.bsn := RESIZE_DP_BSN(v.bsn_arr(v.rd_blk_pointer)); -- . pass on lost data flags for enabled streams via channel field, and -- determine whether the ouput has to insert replacement data v.mm_sosi.channel := (OTHERS=>'0'); FOR I IN 0 TO g_nof_streams-1 LOOP - d.lost_data_flag := NOT v.filled_arr(I)(v.rd_pointer); + w.lost_data_flags_arr(I) := NOT v.filled_arr(I)(v.rd_blk_pointer); IF stream_en_arr(I) = '1' THEN -- use MM bit at sop - v.use_replacement_data(I) := d.lost_data_flag; -- enabled stream, so replace the data if the data was lost - v.mm_sosi.channel(I) := d.lost_data_flag; -- enabled stream, so flag the data if the data was lost + v.use_replacement_data(I) := w.lost_data_flags_arr(I); -- enabled stream, so replace the data if the data was lost + v.mm_sosi.channel(I) := w.lost_data_flags_arr(I); -- enabled stream, so flag the data if the data was lost ELSE v.use_replacement_data(I) := '1'; -- disabled stream, so replace the data, but do not flag the data as lost END IF; @@ -280,7 +300,7 @@ BEGIN -- . clear filled flags, after mm_sosi was issued, or could have been issued FOR I IN 0 TO g_nof_streams-1 LOOP - v.filled_arr(I)(v.rd_pointer) := '0'; + v.filled_arr(I)(v.rd_blk_pointer) := '0'; END LOOP; END IF; @@ -294,7 +314,7 @@ BEGIN -- . if necessary, replace a stream by replacement data FOR I IN 0 TO g_nof_streams-1 LOOP IF r.use_replacement_data(I) = '1' THEN - v.fill_cipo_arr(I).rddata := TO_MEM_SDATA(g_replacement_value); + v.fill_cipo_arr(I).rddata := TO_MEM_SDATA(g_data_replacement_value); END IF; END LOOP; @@ -311,7 +331,7 @@ BEGIN mm_cipo_arr <= v.fill_cipo_arr; -- . no output via DP streaming interface - out_sosi_arr <= (OTHERS => c_dp_sosi_rst); + comb_out_sosi_arr <= (OTHERS => c_dp_sosi_rst); ELSE -------------------------------------------------------------------------- -- Do the output via the DP streaming interface @@ -327,26 +347,33 @@ BEGIN END IF; -- . pass on input data from the buffer - d.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the + w.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the -- input data from the buffer or replacement data IF rd_sosi_arr(0).sop = '1' THEN -- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr - d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.dp_sosi.sync, "SYNC"); - d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.dp_sosi.bsn, "BSN"); + w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.sync, "SYNC"); + w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.bsn, "BSN"); FOR I IN 0 TO g_nof_streams-1 LOOP -- . pass on the lost flag per stream - d.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(slv(r.dp_sosi.channel(I))); + w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(slv(r.dp_sosi.channel(I))); END LOOP; - -- . hold BSN until next sop, to ease view in wave window + -- . hold sop info fields until next sop, to ease view in wave window v.out_bsn := r.dp_sosi.bsn(g_bsn_w-1 DOWNTO 0); + FOR I IN 0 TO g_nof_streams-1 LOOP + v.out_channel_arr(I) := w.out_sosi_arr(I).channel(c_channel_w-1 DOWNTO 0); + END LOOP; ELSE - -- . until next sop pass on BSN, to ease view in wave window - d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.out_bsn, "BSN"); + -- . until next sop pass on BSN to all streams, to ease view in wave window + w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.out_bsn, "BSN"); + FOR I IN 0 TO g_nof_streams-1 LOOP + -- . until next sop pass on channel bit 0 per stream, to ease view in wave window + w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I)); + END LOOP; END IF; -- . output via DP streaming interface - out_sosi_arr <= d.out_sosi_arr; + comb_out_sosi_arr <= w.out_sosi_arr; -- . no output via MM interface mm_cipo_arr <= (OTHERS => c_mem_cipo_rst); @@ -357,8 +384,8 @@ BEGIN ---------------------------------------------------------------------------- nxt_r <= v; - -- memory less signals, only for view in wave window - s <= d; + -- local wires, only for view in wave window + dbg_wires <= w; END PROCESS; ------------------------------------------------------------------------------ @@ -421,7 +448,7 @@ BEGIN -- Pipelining ------------------------------------------------------------------------------ - -- . input + -- . input streams u_in_sosi_arr_p : ENTITY work.dp_pipeline_arr GENERIC MAP ( g_nof_streams => g_nof_streams, @@ -439,4 +466,19 @@ BEGIN -- . read RAM rd_copi <= nxt_r.rd_copi WHEN g_rd_latency = 1 ELSE r.rd_copi; + -- . output streams + u_out_sosi_arr_p : ENTITY work.dp_pipeline_arr + GENERIC MAP ( + g_nof_streams => g_nof_streams, + g_pipeline => g_pipeline_output + ) + PORT MAP ( + rst => dp_rst, + clk => dp_clk, + -- ST sink + snk_in_arr => comb_out_sosi_arr, + -- ST source + src_out_arr => out_sosi_arr + ); + END rtl; diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd index 5f55dc5a6675482176658ff3d29b308769cde600..e18047afe4322bab4ac2b2909e2ab21350987c4b 100644 --- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd @@ -43,13 +43,19 @@ USE work.dp_stream_pkg.ALL; ENTITY mmp_dp_bsn_align_v2 IS GENERIC ( + -- for dp_bsn_align_v2 g_nof_streams : NATURAL; -- number of input and output streams g_bsn_latency_max : NATURAL; -- Maximum travel latency of a remote block in number of block periods T_blk g_nof_aligners_max : NATURAL := 1; -- 1 when only align at last node, > 1 when align at every intermediate node g_block_size : NATURAL := 32; -- > 1, g_block_size=1 is not supported g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_data_w : NATURAL; -- number of bits in sosi data - g_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks + g_data_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks + g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP + g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr + g_pipeline_output : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr + g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure + -- for mms_dp_bsn_monitor_v2 g_nof_clk_per_sync : NATURAL := 200*10**6; g_nof_input_bsn_monitors : NATURAL := 0; g_use_bsn_output_monitor : BOOLEAN := FALSE @@ -59,8 +65,8 @@ ENTITY mmp_dp_bsn_align_v2 IS mm_rst : IN STD_LOGIC; mm_clk : IN STD_LOGIC; - reg_copi : IN t_mem_copi; - reg_cipo : OUT t_mem_cipo; + reg_bsn_align_copi : IN t_mem_copi; + reg_bsn_align_cipo : OUT t_mem_cipo; reg_input_monitor_copi : IN t_mem_copi; reg_input_monitor_cipo : OUT t_mem_cipo; @@ -69,18 +75,21 @@ ENTITY mmp_dp_bsn_align_v2 IS reg_output_monitor_cipo : OUT t_mem_cipo; -- Streaming clock domain - dp_rst : IN STD_LOGIC; - dp_clk : IN STD_LOGIC; + dp_rst : IN STD_LOGIC; + dp_clk : IN STD_LOGIC; - node_index : IN NATURAL := 0; -- only used when g_nof_aligners_max > 1 + node_index : IN NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0; -- only used when g_nof_aligners_max > 1 -- Streaming input - in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - -- Output via local MM in dp_clk domain - mm_copi : IN t_mem_copi; -- read access to output block, all output streams share same mm_copi - mm_cipo_arr : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); - mm_sosi : OUT t_dp_sosi -- streaming information that signals that an output block can be read + -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE. + mm_sosi : OUT t_dp_sosi; -- streaming information that signals that an output block can be read + mm_copi : IN t_mem_copi := c_mem_copi_rst; -- read access to output block, all output streams share same mm_copi + mm_cipo_arr : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); + + -- Output via streaming DP interface, when g_use_mm_output = TRUE. + out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) ); END mmp_dp_bsn_align_v2; @@ -95,15 +104,19 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS -- dat_w : NATURAL; -- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w -- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X' - CONSTANT c_mm_reg : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0'); + CONSTANT c_mm_reg : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0'); - SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0); - SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); + SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0); + SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); - SIGNAL mm_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0); + SIGNAL ref_sync : STD_LOGIC; + SIGNAL mon_out_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0); + SIGNAL i_out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL i_mm_sosi : t_dp_sosi; BEGIN + -- MM control of BSN aligner u_reg : ENTITY common_lib.common_reg_r_w_dc GENERIC MAP ( g_cross_clock_domain => TRUE, @@ -118,8 +131,8 @@ BEGIN st_clk => dp_clk, -- Memory Mapped Slave in mm_clk domain - sla_in => reg_copi, - sla_out => reg_cipo, + sla_in => reg_bsn_align_copi, + sla_out => reg_bsn_align_cipo, -- MM registers in st_clk domain reg_wr_arr => OPEN, @@ -130,6 +143,9 @@ BEGIN stream_en_arr <= reg_wr; + -- Use local sync as reference sync input for the BSN monitors + ref_sync <= in_sosi_arr(0).sync; + -- Use input BSN monitors for the first g_nof_input_bsn_monitors input -- streams, e.g. to support: -- . only one input stream (g_nof_input_bsn_monitors = 1), or @@ -156,9 +172,8 @@ BEGIN -- Streaming clock domain dp_rst => dp_rst, dp_clk => dp_clk, - ref_sync => in_sosi_arr(0).sync, -- local reference sync input + ref_sync => ref_sync, - in_siso_arr => (OTHERS=>c_dp_siso_rdy), in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors-1 DOWNTO 0) ); END GENERATE; @@ -185,13 +200,19 @@ BEGIN -- Streaming clock domain dp_rst => dp_rst, dp_clk => dp_clk, - ref_sync => in_sosi_arr(0).sync, -- local reference sync input + ref_sync => ref_sync, - in_siso_arr => (OTHERS=>c_dp_siso_rdy), - in_sosi_arr => mm_sosi_arr + in_sosi_arr => mon_out_sosi_arr ); END GENERATE; + -- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor + mon_out_sosi_arr(0) <= i_mm_sosi WHEN g_use_mm_output = TRUE ELSE i_out_sosi_arr(0); + + -- wire to output + mm_sosi <= i_mm_sosi; + out_sosi_arr <= i_out_sosi_arr; + u_bsn_align : ENTITY work.dp_bsn_align_v2 GENERIC MAP ( g_nof_streams => g_nof_streams, @@ -200,7 +221,11 @@ BEGIN g_block_size => g_block_size, g_bsn_w => g_bsn_w, g_data_w => g_data_w, - g_replacement_value => g_replacement_value + g_data_replacement_value => g_data_replacement_value, + g_use_mm_output => g_use_mm_output, + g_pipeline_input => g_pipeline_input, + g_pipeline_output => g_pipeline_output, + g_rd_latency => g_rd_latency ) PORT MAP ( dp_rst => dp_rst, @@ -211,12 +236,12 @@ BEGIN -- Streaming input in_sosi_arr => in_sosi_arr, -- Output via local MM in dp_clk domain + mm_sosi => i_mm_sosi, mm_copi => mm_copi, mm_cipo_arr => mm_cipo_arr, - mm_sosi => mm_sosi + -- Output via streaming DP interface, when g_use_mm_output = TRUE. + out_sosi_arr => i_out_sosi_arr ); - mm_sosi <= mm_sosi_arr(0); - END str; diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd index 4e62f1ceba00e9d1ddd859c1ef6ed081bfb85ec4..1c464c468c67424c91dadffc99860e32c941e4c4 100644 --- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd @@ -19,6 +19,54 @@ -- Author: Eric Kooistra, 3 Sept 2021 -- Purpose: Verify dp_bsn_align_v2 -- Description: +-- The tb verifies: +-- . DUT alignment of g_nof_streams >= 2 +-- . DUT restart via g_tb_nof_restart > 1 +-- . gaps or no gaps between blocks via g_block_period >= g_block_size +-- . g_bsn_latency_max in combination with g_tb_diff_delay +-- . g_use_mm_output using DUT MM to DP or external MM to DP in tb +-- . g_data_replacement_value for a remote g_disable_stream_id (it is +-- sufficient to verify one stream) +-- . g_data_replacement_value and lost flag channel(0) bit for a lost +-- remote g_lost_stream_id +-- . the local stream cannot be disabled or lost, because if it does, +-- then there is no output, which is verified by g_tb_nof_restart >= 2 +-- . g_lost_bsn_id to loose a single block in stream 1 and verify that +-- it gets replaced and flagged. +-- . array of one or more BSN aligners via g_nof_aligners_max >= 1, +-- using node_index_arr, only support tb for g_use_mm_output = FALSE +-- Remark: +-- For this BSN aligner component it was essential to have an almost +-- complete, reviewed, detailed design document, because it is a complex +-- component. Main difference after review was addding build in support +-- for streaming output via g_use_mm_output. The clear design made it +-- much easier to achieve a draft implementation that was almost correct. +-- For the DUT it implementation it was also essential to use the p_reg, +-- p_comb coding template. +-- The initial DUT implementation did not change much anymore after the +-- first tb tests, expect for some small (but important) corrections. +-- Each feature of the tb took several hours or up to a day to add. Much +-- time was also spent to regularly clean up and simply the code. The +-- last tb feature that verifies a chain of DUTs is realy nice to see, +-- e.g. by expanding dut_out_sosi_2_arr in the Wave window. The ascii +-- drawing at gen_bsn_align_chain was used to more easily connect and +-- clarify the wiring for the chain of DUTs. +-- Implementing the tb took more time than the DUT, but the design +-- document and the especially the design decisions took the most time. +-- The design decision to use a circular buffer instead of FIFOs and the +-- design decision to rely on a local reference and fixed latencies were +-- important. Initial prestudy end 2020 was done based on experience with +-- aligning streams in LOFAR1 and with the bsn_aligner.vhd in APERTIF. +-- About a in autumn 2021 the detailed design and implementation were done. +-- . prestudy ~ 1 week +-- . design decisions doc ~ 1 week (based on prestudy) +-- . detailed design doc ~ 1 week +-- . review and process review ~ 2 days +-- . implement DUT ~ 2 days (core in 1 day, features one more day) +-- . implement tb (and adding to tb_tb) ~ 1 week +-- . implement tb_mmp ~ 1 day +-- Total: ~ 6 weeks +-- -- Usage: -- > as 10 -- > run -all @@ -37,22 +85,27 @@ USE dp_lib.tb_dp_pkg.ALL; ENTITY tb_dp_bsn_align_v2 IS GENERIC ( -- DUT - g_nof_streams : NATURAL := 2; -- number of input and output streams - g_bsn_latency_max : NATURAL := 2; -- Maximum travel latency of a remote block in number of block periods T_blk - g_nof_aligners_max : POSITIVE := 1; -- 1 when only align at last node, > 1 when align at every intermediate node - g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported - g_block_period : NATURAL := 20; -- >= g_block_size, = g_block_size + c_gap_size - g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN - g_data_w : NATURAL := 16; -- number of bits in sosi data - g_replacement_value : INTEGER := 17; -- output sosi data replacement value for missing input blocks - g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP - g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure - g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure + g_nof_streams : NATURAL := 2; -- number of input and output streams + g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk + g_nof_aligners_max : POSITIVE := 1; -- 1 when only align at last node, > 1 when align at every intermediate node + g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported + g_block_period : NATURAL := 20; -- >= g_block_size, = g_block_size + c_gap_size + g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN + g_data_w : NATURAL := 16; -- number of bits in sosi data + g_data_replacement_value : INTEGER := 17; -- output sosi data replacement value for missing input blocks + g_disable_stream_id : NATURAL := 0; -- default 0 to enable all streams, > 0 selects stream that will be disabled + g_lost_stream_id : NATURAL := 0; -- default 0 to have all streams, > 0 selects stream that will be lost + g_lost_bsn_id : NATURAL := 0; -- for stream 1 the block with bsn = g_lost_bsn_id will be lost + g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP + g_pipeline_input : NATURAL := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr + g_pipeline_output : NATURAL := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sop_arr + g_rd_latency : NATURAL := 1; -- 1 or 2, choose 2 to ease timing closure -- TB - g_tb_diff_delay_max : NATURAL := 10; -- maximum nof clk delay between any inputs, <= c_align_latency_nof_clk - g_tb_nof_restart : NATURAL := 2; -- number of times to restart the input stimuli - g_tb_nof_blocks : NATURAL := 20 -- number of input blocks per restart + g_tb_diff_delay : INTEGER := 0; -- 0 = aligned inputs, -1 = max input delay for no loss, + -- >~ g_bsn_latency_max * g_block_period will give loss + g_tb_nof_restart : NATURAL := 2; -- number of times to restart the input stimuli + g_tb_nof_blocks : NATURAL := 20 -- number of input blocks per restart ); END tb_dp_bsn_align_v2; @@ -64,17 +117,42 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS CONSTANT c_data_w : NATURAL := 16; CONSTANT c_data_init : INTEGER := 0; CONSTANT c_bsn_w : NATURAL := 16; -- use <= 31 bit to fit NATURAL - CONSTANT c_bsn_init : NATURAL := 3; + CONSTANT c_bsn_init : NATURAL := 3; -- use > 0 to have no lost data for g_lost_bsn_id = 0 CONSTANT c_channel_init : INTEGER := 0; CONSTANT c_err_init : NATURAL := 247; CONSTANT c_sync_period : NATURAL := 7; CONSTANT c_sync_offset : NATURAL := 2; + -- maximum nof clk delay between any inputs, <= c_align_latency_nof_clk + -- . the -1 is due to some acceptable pipeline detail related to dp_block_from_mm + CONSTANT c_diff_delay_max : NATURAL := g_bsn_latency_max * g_block_period - sel_a_b(g_rd_latency > 1, 0, 1); + CONSTANT c_diff_delay : NATURAL := sel_a_b(g_tb_diff_delay < 0, c_diff_delay_max, g_tb_diff_delay); + + -- Return input delay as function of inputs stream index I + FUNCTION func_input_delay(I : NATURAL) RETURN NATURAL IS + BEGIN + RETURN c_diff_delay * I / (g_nof_streams - 1); + END; + CONSTANT c_gap_size : NATURAL := g_block_period - g_block_size; - CONSTANT c_dut_latency : NATURAL := g_pipeline_input + g_rd_latency + 2; - CONSTANT c_align_latency_nof_blocks : NATURAL := g_bsn_latency_max; -- DUT buffer latency in number blocks - CONSTANT c_align_latency_nof_valid : NATURAL := g_bsn_latency_max * g_block_size; -- DUT buffer latency in number of data samples - CONSTANT c_align_latency_nof_clk : NATURAL := g_bsn_latency_max * g_block_period; -- DUT buffer latency in number clk cycles + + CONSTANT c_lost_bsn_stream_id : NATURAL := 1; -- fixed use stream 1 to verify g_lost_bsn_id + + -- In the tb only support MM interface verification for c_nof_aligners_max = 1 + CONSTANT c_nof_aligners_max : POSITIVE := sel_a_b(g_use_mm_output, 1, g_nof_aligners_max); + + -- DUT latency of chain of DUTs is same as DUT latency of one DUT, so + -- independent c_nof_aligners_max. This is because the c_dut_latency of the + -- other DUTs is covered by the buffer latency. + CONSTANT c_mm_to_dp_latency : NATURAL := 1; + CONSTANT c_dut_latency : NATURAL := g_pipeline_input + g_rd_latency + c_mm_to_dp_latency + g_pipeline_output; + + -- DUT buffer latency for chain of DUTs + CONSTANT c_align_latency_nof_blocks : NATURAL := g_bsn_latency_max * c_nof_aligners_max; -- in number blocks + CONSTANT c_align_latency_nof_valid : NATURAL := g_bsn_latency_max * c_nof_aligners_max * g_block_size; -- in number of data samples + CONSTANT c_align_latency_nof_clk : NATURAL := g_bsn_latency_max * c_nof_aligners_max * g_block_period; -- in number clk cycles + + -- Total DUT chain latency CONSTANT c_total_latency : NATURAL := c_dut_latency + c_align_latency_nof_clk; CONSTANT c_verify_nof_blocks : NATURAL := g_tb_nof_blocks - c_align_latency_nof_blocks; -- skip last blocks that are still in the DUT buffer @@ -92,18 +170,26 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); END RECORD; + TYPE t_dut_sosi_2arr IS ARRAY (NATURAL RANGE <>) OF t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL tb_end_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL tb_end : STD_LOGIC; SIGNAL clk : STD_LOGIC := '1'; SIGNAL rst : STD_LOGIC := '1'; + SIGNAL sl1 : STD_LOGIC := '1'; - SIGNAL node_index : NATURAL := 0; + SIGNAL node_index_arr : t_nat_natural_arr(0 TO c_nof_aligners_max-1) := array_init(0, c_nof_aligners_max, 1); SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1'); -- default all streams are enabled + SIGNAL stream_lost_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- default no streams are lost + SIGNAL in_bsn_lost_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- default no blocks are lost + SIGNAL in_bsn_lost : STD_LOGIC; -- = in_bsn_lost_arr(c_lost_bsn_stream_id) + SIGNAL exp_bsn_lost_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- default no blocks are lost SIGNAL ref_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); - SIGNAL ref_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + SIGNAL ref_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- generated stimuli + SIGNAL rx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- received stimuli + SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- input stimuli SIGNAL in_sync_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); SIGNAL in_sop_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); @@ -120,12 +206,13 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS SIGNAL mm_sosi : t_dp_sosi; -- streaming information that signals that an output block can be read SIGNAL mm_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); SIGNAL mm_done : STD_LOGIC; - SIGNAL dut_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); - SIGNAL tb_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL mm_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + SIGNAL dut_in_sosi_2arr : t_dut_sosi_2arr(0 TO c_nof_aligners_max-1); + SIGNAL dut_out_sosi_2arr : t_dut_sosi_2arr(0 TO c_nof_aligners_max-1); + SIGNAL dut_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- last BSN aligner output SIGNAL r : t_reg; SIGNAL nxt_r : t_reg; - SIGNAL out_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); SIGNAL out_sosi : t_dp_sosi; @@ -136,11 +223,11 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS SIGNAL out_data_arr : t_data_arr; SIGNAL hold_data_arr : t_data_arr; SIGNAL out_bsn_arr : t_bsn_arr; + SIGNAL out_bsn : INTEGER; SIGNAL out_channel_arr : t_channel_arr; SIGNAL out_err_arr : t_err_arr; SIGNAL tb_state : t_tb_state; - SIGNAL tb_bsn : INTEGER; SIGNAL restart_cnt_arr : t_nat_integer_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => -1); SIGNAL restart_cnt : INTEGER := 0; SIGNAL ref_sosi_arr_dly : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); @@ -149,18 +236,27 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS SIGNAL verify_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL verify_sosi_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL expected_out_bsn_arr : t_bsn_arr; - SIGNAL expected_out_data_arr : t_data_arr; + SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL expected_out_bsn_arr : t_bsn_arr; + SIGNAL expected_out_data_arr : t_data_arr; + SIGNAL expected_out_channel_arr : t_channel_arr; - -- Return input delay as function of inputs stream index I - FUNCTION func_input_delay(I : NATURAL) RETURN NATURAL IS - BEGIN - RETURN g_tb_diff_delay_max * I / (g_nof_streams - 1); - END; + -- Debug signals to view in Wave window + SIGNAL dbg_func_delay_max : NATURAL := func_input_delay(g_nof_streams - 1); - SIGNAL dbg_tb_diff_delay_max : NATURAL := g_tb_diff_delay_max; - SIGNAL dbg_func_delay_max : NATURAL := func_input_delay(g_nof_streams - 1); + SIGNAL dbg_c_align_latency_nof_blocks : NATURAL := c_align_latency_nof_blocks; + SIGNAL dbg_c_align_latency_nof_valid : NATURAL := c_align_latency_nof_valid; + SIGNAL dbg_c_align_latency_nof_clk : NATURAL := c_align_latency_nof_clk; + SIGNAL dbg_c_total_latency : NATURAL := c_total_latency; + SIGNAL dbg_c_verify_nof_blocks : NATURAL := c_verify_nof_blocks; + + -- Debug signals to view that verification conditions actually occur + SIGNAL dbg_verify_sosi_control_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when sosi control is verified + SIGNAL dbg_verify_passed_on_data_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when passed on data is verified + SIGNAL dbg_verify_replaced_data_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when replaced data is verified + SIGNAL dbg_verify_bsn_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when bsn in all streams is verified + SIGNAL dbg_verify_no_lost_flag_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when lost data flag = 0 is verified + SIGNAL dbg_verify_lost_flag_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); -- '1' when lost data flag = 1 is verified BEGIN @@ -172,7 +268,7 @@ BEGIN ------------------------------------------------------------------------------ -- Generate data path input data - gen_input : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE + gen_stimuli : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE p_stimuli : PROCESS VARIABLE v_sync : STD_LOGIC := '0'; VARIABLE v_bsn : NATURAL; @@ -189,24 +285,39 @@ BEGIN -- Begin of stimuli FOR S IN 0 TO g_tb_nof_restart-1 LOOP v_bsn := c_bsn_init; - IF S = 2 THEN - stream_en_arr(1) <= '0'; - END IF; FOR R IN 0 TO g_tb_nof_blocks-1 LOOP v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0'); - proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), clk, stream_en_arr(I), ref_siso_arr(I), ref_sosi_arr(I)); + proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), clk, sl1, ref_siso_arr(I), ref_sosi_arr(I)); v_bsn := v_bsn + 1; v_data := v_data + g_block_size; proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames END LOOP; - -- no gap between restarts, to ease verification by maintaining fixed latency of out_sosi_arr_exp + -- no gap between restarts, to ease verification by maintaining fixed + -- latency of out_sosi_arr_exp restart_cnt_arr(I) <= restart_cnt_arr(I) + 1; END LOOP; - -- End of stimuli, g_bsn_latency_max blocks remain in DUT buffer + -- End of stimuli + -- . default g_bsn_latency_max blocks remain in DUT buffer expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w); expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w); - + -- . default no data is lost, so all channel(0) lost data flags are 0 + expected_out_channel_arr(I) <= TO_DP_CHANNEL(0); + + -- Account for disturbed remote input streams + IF I > 0 THEN + IF I = g_disable_stream_id THEN + -- Expected stream disable replacement data value + expected_out_data_arr(I) <= TO_UVEC(g_data_replacement_value, c_data_w); + END IF; + IF I = g_lost_stream_id THEN + -- Expected stream lost replacement data value and expected lost + -- flag channel(0) value + expected_out_data_arr(I) <= TO_UVEC(g_data_replacement_value, c_data_w); + expected_out_channel_arr(I) <= TO_DP_CHANNEL(1); + END IF; + END IF; + proc_common_wait_some_cycles(clk, 100); verify_done_arr(I) <= '1'; proc_common_wait_some_cycles(clk, 1); @@ -217,6 +328,39 @@ BEGIN END PROCESS; END GENERATE; + tb_end <= vector_and(tb_end_arr); + + -- Model misalignment latency between the input streams. + -- . it is sufficient to only model misalignment for the first DUT in case + -- c_nof_aligners_max > 1. + gen_rx_sosi_arr : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE + rx_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * clk_period; + END GENERATE; + + -- Model enable/disable remote input stream + stream_en_arr(g_disable_stream_id) <= '0' WHEN g_disable_stream_id > 0; + + -- Model lost remote input stream + stream_lost_arr(g_lost_stream_id) <= '1' WHEN g_lost_stream_id > 0; + + -- Model lost block on one remote input stream c_lost_bsn_stream_id + in_bsn_lost_arr(c_lost_bsn_stream_id) <= '1' WHEN TO_UINT(rx_sosi_arr(c_lost_bsn_stream_id).bsn) = g_lost_bsn_id ELSE '0'; + in_bsn_lost <= in_bsn_lost_arr(c_lost_bsn_stream_id); + + p_in_sosi_arr : PROCESS(rx_sosi_arr, stream_lost_arr, in_bsn_lost_arr) + BEGIN + in_sosi_arr <= rx_sosi_arr; + -- Model entirely lost remote input stream + IF stream_lost_arr(g_lost_stream_id) = '1' THEN + in_sosi_arr(g_lost_stream_id) <= RESET_DP_SOSI_CTRL(rx_sosi_arr(g_lost_stream_id)); + END IF; + -- Model single lost block in a stream (stream c_lost_bsn_stream_id = 1) + IF in_bsn_lost_arr(c_lost_bsn_stream_id) = '1' THEN + in_sosi_arr(c_lost_bsn_stream_id) <= RESET_DP_SOSI_CTRL(rx_sosi_arr(c_lost_bsn_stream_id)); + END IF; + END PROCESS; + + -- Use tb_state to view tb progress in Wave window restart_cnt <= restart_cnt_arr(0); @@ -228,14 +372,6 @@ BEGIN IF restart_cnt > 1 THEN tb_state <= s_restart; END IF; END PROCESS; - -- Create latency misalignment between the input streams - gen_in_sosi_arr : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE - in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * clk_period; - END GENERATE; - - - tb_end <= vector_and(tb_end_arr); - mon_sosi : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE -- Ease in_sosi_arr monitoring in_sync_arr(I) <= in_sosi_arr(I).sync; @@ -260,14 +396,14 @@ BEGIN out_sosi <= out_sosi_arr(0); -- take out_sosi control and info from out_sosi_arr(0) + out_bsn <= TO_UINT(out_sosi.bsn); -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn + ------------------------------------------------------------------------------ -- DATA VERIFICATION, use multiple ways to increase coverage - -- a) Use proc_dp_verify_*() to verify output compared to prev output - -- b) Use delayed in_sosi_arr as expected out_sosi_arr + -- a) Use proc_dp_verify_*() to verify output sosi format + -- b) Use delayed in_sosi_arr as expected out_sosi_arr to verify output sosi ------------------------------------------------------------------------------ - tb_bsn <= TO_UINT(out_sosi.bsn); - ref_sosi_arr_dly <= TRANSPORT ref_sosi_arr AFTER c_total_latency * clk_period; out_sosi_arr_exp <= ref_sosi_arr_dly WHEN rising_edge(clk); out_sosi_exp <= out_sosi_arr_exp(0); -- take out_sosi_exp control and info from out_sosi_arr_exp(0) @@ -280,16 +416,16 @@ BEGIN -- . Verify that the stimuli have been applied at all hold_data_arr(I) <= out_data_arr(I) WHEN out_val_arr(I) = '1'; -- hold last valid data - proc_dp_verify_value("out_data_arr", e_equal, clk, verify_done_arr(I), expected_out_data_arr(I), hold_data_arr(I)); proc_dp_verify_value("out_bsn_arr", e_equal, clk, verify_done_arr(I), expected_out_bsn_arr(I), out_bsn_arr(I)); + proc_dp_verify_value("out_channel_arr", e_equal, clk, verify_done_arr(I), expected_out_channel_arr(I), out_channel_arr(I)); END GENERATE; -- . Use delayed in_sosi_arr as expected out_sosi_arr, this is possible -- because the DUT has no flow control and has a fixed latency. p_verify_sosi_en_arr : PROCESS(out_sosi_exp) BEGIN - IF g_tb_diff_delay_max <= c_align_latency_nof_clk THEN + IF c_diff_delay <= c_align_latency_nof_clk THEN verify_sosi_en_arr <= (OTHERS => '1'); IF TO_UINT(out_sosi_exp.bsn) - c_bsn_init >= c_verify_nof_blocks THEN verify_sosi_en_arr <= (OTHERS => '0'); @@ -297,23 +433,57 @@ BEGIN END IF; END PROCESS; + exp_bsn_lost_arr(c_lost_bsn_stream_id) <= '1' WHEN TO_UINT(out_sosi_arr_exp(c_lost_bsn_stream_id).bsn) = g_lost_bsn_id ELSE '0'; + gen_verify_streams : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE - p_verify_sosi : PROCESS(clk) + p_verify_stream : PROCESS(clk) BEGIN IF rising_edge(clk) THEN + dbg_verify_sosi_control_arr(I) <= '0'; + dbg_verify_passed_on_data_arr(I) <= '0'; + dbg_verify_replaced_data_arr(I) <= '0'; + dbg_verify_bsn_arr(I) <= '0'; + dbg_verify_no_lost_flag_arr(I) <= '0'; + dbg_verify_lost_flag_arr(I) <= '0'; IF verify_sosi_en_arr(I) = '1' AND out_sosi_arr_exp(I).valid = '1' THEN + -- Verify sosi control fields + dbg_verify_sosi_control_arr(I) <= '1'; ASSERT out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync REPORT "Wrong sync for output " & int_to_str(I) SEVERITY ERROR; ASSERT out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop REPORT "Wrong sop for output " & int_to_str(I) SEVERITY ERROR; ASSERT out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop REPORT "Wrong eop for output " & int_to_str(I) SEVERITY ERROR; ASSERT out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid REPORT "Wrong valid for output " & int_to_str(I) SEVERITY ERROR; - IF stream_en_arr(I) = '1' THEN - ASSERT out_sosi_arr(I).data = out_sosi_arr_exp(I).data REPORT "Wrong data for output " & int_to_str(I) & " : " - & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= " - & int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) SEVERITY ERROR; + + -- Verify data field + IF stream_en_arr(I) = '1' AND stream_lost_arr(I) = '0' AND exp_bsn_lost_arr(I) = '0' THEN + -- verify passed on data + dbg_verify_passed_on_data_arr(I) <= '1'; + ASSERT out_sosi_arr(I).data = out_sosi_arr_exp(I).data REPORT "Wrong data for output stream " & int_to_str(I) & " : " + & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= " + & int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) SEVERITY ERROR; ELSE - ASSERT TO_UINT(out_sosi_arr(I).data) = g_replacement_value REPORT "Wrong data for output " & int_to_str(I) & " : " - & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= " - & int_to_str(g_replacement_value) SEVERITY ERROR; + -- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id + dbg_verify_replaced_data_arr(I) <= '1'; + ASSERT TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value REPORT "Wrong replacement data for output stream " & int_to_str(I) & " : " + & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= " + & int_to_str(g_data_replacement_value) SEVERITY ERROR; + END IF; + + -- Verify sop info fields + IF out_sosi_arr_exp(I).sop = '1' THEN + -- bsn field + dbg_verify_bsn_arr(I) <= '1'; + ASSERT out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn REPORT "Wrong bsn for output " & int_to_str(I) SEVERITY ERROR; + + -- channel field with lost flag bit 0 + IF stream_lost_arr(I) = '0' AND exp_bsn_lost_arr(I) = '0' THEN + -- verify no lost stream + dbg_verify_no_lost_flag_arr(I) <= '1'; + ASSERT out_sosi_arr(I).channel = TO_DP_CHANNEL(0) REPORT "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) SEVERITY ERROR; + ELSE + -- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id + dbg_verify_lost_flag_arr(I) <= '1'; + ASSERT out_sosi_arr(I).channel = TO_DP_CHANNEL(1) REPORT "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) SEVERITY ERROR; + END IF; END IF; END IF; END IF; @@ -323,37 +493,102 @@ BEGIN ------------------------------------------------------------------------------ -- DUT ------------------------------------------------------------------------------ - + + -- Connect all inputs to first DUT + dut_in_sosi_2arr(0) <= in_sosi_arr; + u_bsn_align : ENTITY work.dp_bsn_align_v2 GENERIC MAP ( g_nof_streams => g_nof_streams, g_bsn_latency_max => g_bsn_latency_max, - g_nof_aligners_max => g_nof_aligners_max, + g_nof_aligners_max => c_nof_aligners_max, g_block_size => g_block_size, g_bsn_w => g_bsn_w, g_data_w => g_data_w, - g_replacement_value => g_replacement_value, - g_use_mm_output => g_use_mm_output, -- output via MM or via streaming DP - g_pipeline_input => g_pipeline_input, -- >= 0, choose 0 for wires, choose 1 to ease timing closure - g_rd_latency => g_rd_latency -- 1 or 2, choose 2 to ease timing closure + g_data_replacement_value => g_data_replacement_value, + g_use_mm_output => g_use_mm_output, + g_pipeline_input => g_pipeline_input, + g_pipeline_output => g_pipeline_output, + g_rd_latency => g_rd_latency ) PORT MAP ( dp_rst => rst, dp_clk => clk, -- Control - node_index => node_index, + node_index => node_index_arr(0), stream_en_arr => stream_en_arr, -- Streaming input - in_sosi_arr => in_sosi_arr, + in_sosi_arr => dut_in_sosi_2arr(0), -- Output via local MM interface in dp_clk domain mm_copi => mm_copi, mm_cipo_arr => mm_cipo_arr, mm_sosi => mm_sosi, -- Output via streaming DP interface - out_sosi_arr => dut_sosi_arr + out_sosi_arr => dut_out_sosi_2arr(0) ); + -- Simulate series of DUT, when g_use_mm_output = FALSE and + -- g_nof_aligners_max > 1. Use same local in_sosi_arr(0) input for all BSN + -- aligners, because all DUT have same local reference. Connect the remote + -- in_sosi_arr(> 0) inputs via the BSN aligners: + -- + -- remote + -- in_sosi_arr(> 0) ------> DUT --------> DUT --------> DUT --> dut_sosi_arr()(> 0) + -- /-> 0 --X /-> 1 --X /-> 2 --> dut_sosi_arr()(= 0) + -- local / / / . . + -- in_sosi_arr(= 0) --/-------------/-------------/ . . + -- . . . . . . + -- . . . . . . + -- v . . . . . + -- dut_in_sosi_2arr(0) v . . . . + -- dut_out_sosi_2arr(0) v . . . + -- dut_in_sosi_2arr(1) v . . + -- dut_out_sosi_2arr(1) v . + -- dut_in_sosi_2arr(2) v + -- dut_out_sosi_2arr(2) + -- + gen_bsn_align_chain : FOR I IN 1 TO c_nof_aligners_max-1 GENERATE + u_bsn_align : ENTITY work.dp_bsn_align_v2 + GENERIC MAP ( + g_nof_streams => g_nof_streams, + g_bsn_latency_max => g_bsn_latency_max, + g_nof_aligners_max => c_nof_aligners_max, + g_block_size => g_block_size, + g_bsn_w => g_bsn_w, + g_data_w => g_data_w, + g_data_replacement_value => g_data_replacement_value, + g_use_mm_output => g_use_mm_output, + g_pipeline_input => g_pipeline_input, + g_pipeline_output => g_pipeline_output, + g_rd_latency => g_rd_latency + ) + PORT MAP ( + dp_rst => rst, + dp_clk => clk, + -- Control + node_index => node_index_arr(I), + stream_en_arr => stream_en_arr, + -- Streaming input + in_sosi_arr => dut_in_sosi_2arr(I), + -- Output via streaming DP interface + out_sosi_arr => dut_out_sosi_2arr(I) + ); + + -- Connect remote and local between DUTs in the chain of DUTs + p_connect : PROCESS(dut_out_sosi_2arr, in_sosi_arr) + BEGIN + -- connect the remote inputs, by connecting all inputs from previous DUT + dut_in_sosi_2arr(I) <= dut_out_sosi_2arr(I-1); + + -- connect the local input, same for all DUTs + dut_in_sosi_2arr(I)(0) <= in_sosi_arr(0); + END PROCESS; + END GENERATE; + + -- Connect output from last DUT, so only verify last output + dut_sosi_arr <= dut_out_sosi_2arr(c_nof_aligners_max-1); + ------------------------------------------------------------------------------ -- MM to streaming DP ------------------------------------------------------------------------------ @@ -383,12 +618,12 @@ BEGIN mm_done => mm_done_arr(I), mm_mosi => mm_copi_arr(I), mm_miso => mm_cipo_arr(I), - out_sosi => tb_sosi_arr(I), + out_sosi => mm_sosi_arr(I), out_siso => c_dp_siso_rdy ); END GENERATE; - p_comb : PROCESS(r, mm_sosi, tb_sosi_arr) + p_comb : PROCESS(r, mm_sosi, mm_sosi_arr) VARIABLE v : t_reg; BEGIN v := r; @@ -400,8 +635,8 @@ BEGIN END IF; -- apply mm_sosi.sync, bsn at sop to all streams in out_sosi_arr - v.out_sosi_arr := tb_sosi_arr; - IF tb_sosi_arr(0).sop = '1' THEN + v.out_sosi_arr := mm_sosi_arr; + IF mm_sosi_arr(0).sop = '1' THEN v.out_sosi_arr := func_dp_stream_arr_set(v.out_sosi_arr, r.sync, "SYNC"); v.out_sosi_arr := func_dp_stream_arr_set(v.out_sosi_arr, r.bsn, "BSN"); ELSE diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd index 2b624d5d125f2c1f117c8b18c2fd3e7a2b867f55..0b5a6f61f4899f666adf4930ca8728f089805daa 100644 --- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd @@ -20,6 +20,15 @@ -- Purpose: Verify MM part of mmp_dp_bsn_align_v2 -- Description: -- The functional part is already verified by tb_tb_dp_bsn_align_v2.vhd. +-- Tb features: +-- . verify expected end values for output data and bsn in gen_verify_ctrl +-- to ensure that test has ran +-- . verify MM access to input stream enable in p_mm_verify_bsn_align +-- . verify MM access to input BSN monitors by verifiying expected input +-- latencies for different input delays +-- . verify MM access to output BSN monitor by verifiying expected output +-- latencies. +-- -- Usage: -- > as 5 -- > run -all @@ -45,48 +54,138 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS CONSTANT c_dp_clk_period : TIME := 10 ns; CONSTANT c_cross_clock_domain_latency : NATURAL := 20; - CONSTANT c_report_note : BOOLEAN := FALSE; -- Use TRUE for tb debugging, else FALSE to keep Transcript window more empty - - CONSTANT c_nof_input_sync : NATURAL := 10; - CONSTANT c_nof_block_per_sync : NATURAL := 32; - CONSTANT c_block_size : NATURAL := 10; - CONSTANT c_input_gap_size : NATURAL := 3; - CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_sync * c_nof_input_sync; + CONSTANT c_rl : NATURAL := 1; + CONSTANT c_tb_nof_restart : NATURAL := 2; -- number of times to restart the input stimuli + CONSTANT c_tb_nof_blocks : NATURAL := 50; -- number of input blocks per restart - CONSTANT c_nof_streams : NATURAL := 2; - CONSTANT c_bsn_latency_max : POSITIVE := 2; - CONSTANT c_nof_aligners_max : NATURAL := 1; + -- Fixed dut generics + -- . for dp_bsn_align_v2 + CONSTANT c_nof_streams : NATURAL := 3; + CONSTANT c_bsn_latency_max : NATURAL := 1; + CONSTANT c_nof_aligners_max : POSITIVE := 1; -- fixed in this tb + CONSTANT c_block_size : NATURAL := 11; + CONSTANT c_block_period : NATURAL := 11; CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w; CONSTANT c_data_w : NATURAL := 16; - CONSTANT c_replacement_value : INTEGER := 0; + CONSTANT c_data_replacement_value : INTEGER := 17; + CONSTANT c_use_mm_output : BOOLEAN := FALSE; + CONSTANT c_pipeline_input : NATURAL := 1; + CONSTANT c_pipeline_output : NATURAL := 1; + CONSTANT c_rd_latency : NATURAL := 2; + -- . for mms_dp_bsn_monitor_v2 CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6; - CONSTANT c_nof_input_bsn_monitors : NATURAL := 0; - CONSTANT c_use_bsn_output_monitor : BOOLEAN := FALSE; + CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams; + CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE; + + CONSTANT c_reg_bsn_monitor_adr_w : NATURAL := ceil_log2(7); + CONSTANT c_reg_bsn_monitor_span : NATURAL := 2**c_reg_bsn_monitor_adr_w; + + -- maximum nof clk delay between any inputs, <= c_align_latency_nof_clk + -- . the -1 is due to some acceptable pipeline detail related to dp_block_from_mm + CONSTANT c_diff_delay_max : NATURAL := c_bsn_latency_max * c_block_period - sel_a_b(c_rd_latency > 1, 0, 1); + CONSTANT c_diff_delay : NATURAL := c_diff_delay_max; + + -- Return input delay as function of inputs stream index I + FUNCTION func_input_delay(I : NATURAL) RETURN NATURAL IS + BEGIN + RETURN c_diff_delay * I / (c_nof_streams - 1); + END; + + -- Input stream settings + CONSTANT c_data_init : INTEGER := 0; + CONSTANT c_bsn_init : NATURAL := 3; + CONSTANT c_channel_init : INTEGER := 0; + CONSTANT c_err_init : NATURAL := 247; + CONSTANT c_sync_period : NATURAL := 7; + CONSTANT c_sync_offset : NATURAL := 2; + CONSTANT c_gap_size : NATURAL := c_block_period - c_block_size; + -- DUT latency + CONSTANT c_mm_to_dp_latency : NATURAL := 1; + CONSTANT c_dut_latency : NATURAL := c_pipeline_input + c_rd_latency + c_mm_to_dp_latency + c_pipeline_output; + + CONSTANT c_align_latency_nof_blocks : NATURAL := c_bsn_latency_max * c_nof_aligners_max; -- in number blocks + CONSTANT c_align_latency_nof_valid : NATURAL := c_bsn_latency_max * c_nof_aligners_max * c_block_size; -- in number of data samples + CONSTANT c_align_latency_nof_clk : NATURAL := c_bsn_latency_max * c_nof_aligners_max * c_block_period; -- in number clk cycles + + -- Total DUT chain latency + CONSTANT c_total_latency : NATURAL := c_dut_latency + c_align_latency_nof_clk; + CONSTANT c_verify_nof_blocks : NATURAL := c_tb_nof_blocks - c_align_latency_nof_blocks; -- skip last blocks that are still in the DUT buffer + + -- Signal monitoring and verification + TYPE t_data_arr IS ARRAY (c_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); + TYPE t_bsn_arr IS ARRAY (c_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0); + TYPE t_err_arr IS ARRAY (c_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0); + TYPE t_channel_arr IS ARRAY (c_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0); + + SIGNAL sl1 : STD_LOGIC := '1'; + SIGNAL mm_end : STD_LOGIC := '0'; + SIGNAL dp_end_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL dp_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0'; - SIGNAL stimuli_end : STD_LOGIC := '0'; + SIGNAL streams_enabled : STD_LOGIC := '0'; + SIGNAL restart_cnt_arr : t_nat_integer_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => -1); + SIGNAL restart_cnt : INTEGER := 0; -- MM clock domain SIGNAL mm_clk : STD_LOGIC := '1'; SIGNAL mm_rst : STD_LOGIC := '1'; - SIGNAL reg_copi : t_mem_copi := c_mem_copi_rst; - SIGNAL reg_cipo : t_mem_cipo; + SIGNAL reg_bsn_align_copi : t_mem_copi := c_mem_copi_rst; + SIGNAL reg_bsn_align_cipo : t_mem_cipo; SIGNAL reg_input_monitor_copi : t_mem_copi := c_mem_copi_rst; SIGNAL reg_input_monitor_cipo : t_mem_cipo; SIGNAL reg_output_monitor_copi : t_mem_copi := c_mem_copi_rst; SIGNAL reg_output_monitor_cipo : t_mem_cipo; + SIGNAL mon_latency_input_arr : t_nat_natural_arr(c_nof_streams-1 DOWNTO 0); + SIGNAL mon_latency_output : NATURAL; + -- DP clock domain SIGNAL dp_clk : STD_LOGIC := '1'; SIGNAL dp_rst : STD_LOGIC := '1'; - SIGNAL node_index : NATURAL := 0; -- only used when g_bsn_latency_use_node_index is TRUE - SIGNAL stimuli_sosi : t_dp_sosi; - SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); - SIGNAL mm_copi : t_mem_copi; -- read access to output block, all output streams share same mm_copi - SIGNAL mm_cipo_arr : t_mem_cipo_arr(c_nof_streams-1 DOWNTO 0); - SIGNAL mm_sosi : t_dp_sosi; -- streaming information that signals that an output block can be read + SIGNAL node_index : NATURAL := 0; + SIGNAL ref_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL ref_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- generated stimuli + SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- input stimuli + + SIGNAL in_sync_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL in_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL in_eop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL in_val_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL in_data_arr : t_data_arr; + SIGNAL in_bsn_arr : t_bsn_arr; + SIGNAL in_channel_arr : t_channel_arr; + SIGNAL in_err_arr : t_err_arr; + + SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- output + SIGNAL out_sosi : t_dp_sosi; + SIGNAL out_sync_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL out_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL out_eop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL out_val_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0); + SIGNAL out_data_arr : t_data_arr; + SIGNAL hold_data_arr : t_data_arr; + SIGNAL out_bsn_arr : t_bsn_arr; + SIGNAL out_bsn : INTEGER; + SIGNAL out_channel_arr : t_channel_arr; + SIGNAL out_err_arr : t_err_arr; + + SIGNAL verify_done_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL verify_done : STD_LOGIC; + + SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL expected_out_bsn_arr : t_bsn_arr; + SIGNAL expected_out_data_arr : t_data_arr; + SIGNAL expected_out_channel_arr : t_channel_arr; + + -- Debug signals for view in Wave window + SIGNAL dbg_c_align_latency_nof_blocks : NATURAL := c_align_latency_nof_blocks; + SIGNAL dbg_c_align_latency_nof_valid : NATURAL := c_align_latency_nof_valid; + SIGNAL dbg_c_align_latency_nof_clk : NATURAL := c_align_latency_nof_clk; + SIGNAL dbg_c_total_latency : NATURAL := c_total_latency; + SIGNAL dbg_c_verify_nof_blocks : NATURAL := c_verify_nof_blocks; BEGIN @@ -95,23 +194,70 @@ BEGIN dp_rst <= '1', '0' AFTER c_dp_clk_period*7; mm_rst <= '1', '0' AFTER c_mm_clk_period*7; + tb_end <= mm_end AND dp_end; + + ------------------------------------------------------------------------------ + -- MM stimuli + ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- MM stimuli and verification ------------------------------------------------------------------------------ - p_stimuli_and_verify_mm : PROCESS - VARIABLE v_bsn : NATURAL; - BEGIN + p_mm_verify_bsn_align : PROCESS + BEGIN proc_common_wait_until_low(dp_clk, mm_rst); proc_common_wait_until_low(dp_clk, dp_rst); proc_common_wait_some_cycles(mm_clk, 5); + -- Read stream enable bits, default '0' after power up + FOR I IN 0 TO c_nof_streams-1 LOOP + proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_rd_latency(1, mm_clk); + ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR; + END LOOP; + + -- Write stream enable bits for stream_en_arr + FOR I IN 0 TO c_nof_streams-1 LOOP + proc_mem_mm_bus_wr(I, 1, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + END LOOP; + proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency); + proc_common_wait_some_cycles(dp_clk, c_cross_clock_domain_latency); + + -- Read stream enable bits, should now be '1' + FOR I IN 0 TO c_nof_streams-1 LOOP + proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); + proc_mem_mm_bus_rd_latency(1, mm_clk); + ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR; + END LOOP; - --------------------------------------------------------------------------- - -- End of test - --------------------------------------------------------------------------- - proc_common_wait_until_high(dp_clk, stimuli_end); - tb_end <= '1'; + -- End of MM test + streams_enabled <= '1'; + WAIT; + END PROCESS; + + p_mm_verify_bsn_monitors : PROCESS + BEGIN + proc_common_wait_until_high(mm_clk, verify_done); + + -- Read input BSN monitors + FOR I IN 0 TO c_nof_streams-1 LOOP + proc_mem_mm_bus_rd(6 + I*c_reg_bsn_monitor_span, mm_clk, reg_input_monitor_cipo, reg_input_monitor_copi); + proc_mem_mm_bus_rd_latency(1, mm_clk); + mon_latency_input_arr(I) <= TO_UINT(reg_input_monitor_cipo.rddata); + proc_common_wait_some_cycles(mm_clk, 1); + ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR; + END LOOP; + + -- Read output BSN monitor + proc_mem_mm_bus_rd(6, mm_clk, reg_output_monitor_cipo, reg_output_monitor_copi); + proc_mem_mm_bus_rd_latency(1, mm_clk); + mon_latency_output <= TO_UINT(reg_output_monitor_cipo.rddata); + + proc_common_wait_some_cycles(mm_clk, 1); + ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR; + + -- End of MM test + mm_end <= '1'; WAIT; END PROCESS; @@ -119,36 +265,113 @@ BEGIN -- Streaming stimuli ------------------------------------------------------------------------------ - -- Generate data blocks with input sync - u_stimuli : ENTITY work.dp_stream_stimuli - GENERIC MAP ( - g_sync_period => c_nof_block_per_sync, - g_err_init => 0, - g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window - g_channel_init => 0, - g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window - g_nof_repeat => c_sim_nof_blocks, - g_pkt_len => c_block_size, - g_pkt_gap => c_input_gap_size - ) - PORT MAP ( - rst => dp_rst, - clk => dp_clk, + -- Generate data path input data (similar as in tb_mmp_dp_bsn_align_v2.vhd) + gen_input : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE + p_stimuli : PROCESS + VARIABLE v_sync : STD_LOGIC := '0'; + VARIABLE v_bsn : NATURAL; + VARIABLE v_data : NATURAL := c_data_init; + VARIABLE v_channel : NATURAL := c_channel_init; + VARIABLE v_err : NATURAL := c_err_init; + BEGIN + v_data := v_data + I; + ref_sosi_arr(I) <= c_dp_sosi_rst; + proc_common_wait_until_low(dp_clk, dp_rst); + proc_common_wait_until_high(dp_clk, streams_enabled); + proc_common_wait_some_cycles(dp_clk, 10); + restart_cnt_arr(I) <= restart_cnt_arr(I) + 1; - -- Generate stimuli - src_out => stimuli_sosi, + -- Begin of stimuli + FOR S IN 0 TO c_tb_nof_restart-1 LOOP + v_bsn := c_bsn_init; + FOR R IN 0 TO c_tb_nof_blocks-1 LOOP + v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0'); + proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, c_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), dp_clk, sl1, ref_siso_arr(I), ref_sosi_arr(I)); + v_bsn := v_bsn + 1; + v_data := v_data + c_block_size; + proc_common_wait_some_cycles(dp_clk, c_gap_size); -- create gap between frames + END LOOP; + -- Create gap between restarts + proc_common_wait_some_cycles(dp_clk, 100); + restart_cnt_arr(I) <= restart_cnt_arr(I) + 1; + END LOOP; - -- End of stimuli - tb_end => stimuli_end - ); + -- End of stimuli + -- . default c_bsn_latency_max blocks remain in DUT buffer + expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w); + expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w); + -- . default no data is lost, so all channel(0) lost data flags are 0 + expected_out_channel_arr(I) <= TO_DP_CHANNEL(0); + + proc_common_wait_some_cycles(dp_clk, 100); + verify_done_arr(I) <= '1'; + proc_common_wait_some_cycles(dp_clk, 1); + verify_done_arr(I) <= '0'; + + -- Simulate some more to easy recognizing verify_done in Wave window + proc_common_wait_some_cycles(dp_clk, 100); + dp_end_arr(I) <= '1'; + WAIT; + END PROCESS; + END GENERATE; + + verify_done <= verify_done_arr(0); + restart_cnt <= restart_cnt_arr(0); + + dp_end <= vector_and(dp_end_arr); + + -- Model misalignment latency between the input streams to have different + -- input BSN monitor latencies + gen_rx_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE + in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period; + END GENERATE; + + ------------------------------------------------------------------------------ + -- Data verification + ------------------------------------------------------------------------------ + + mon_sosi : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE + -- Ease in_sosi_arr monitoring + in_sync_arr(I) <= in_sosi_arr(I).sync; + in_sop_arr(I) <= in_sosi_arr(I).sop; + in_eop_arr(I) <= in_sosi_arr(I).eop; + in_val_arr(I) <= in_sosi_arr(I).valid; + in_data_arr(I) <= in_sosi_arr(I).data(c_data_w-1 DOWNTO 0); + in_bsn_arr(I) <= in_sosi_arr(I).bsn(c_bsn_w-1 DOWNTO 0); + in_channel_arr(I) <= in_sosi_arr(I).channel; + in_err_arr(I) <= in_sosi_arr(I).err; + + -- Ease out_sosi_arr monitoring and verification + out_sync_arr(I) <= out_sosi_arr(I).sync; + out_sop_arr(I) <= out_sosi_arr(I).sop; + out_eop_arr(I) <= out_sosi_arr(I).eop; + out_val_arr(I) <= out_sosi_arr(I).valid; + out_data_arr(I) <= out_sosi_arr(I).data(c_data_w-1 DOWNTO 0); + out_bsn_arr(I) <= out_sosi_arr(I).bsn(c_bsn_w-1 DOWNTO 0); + out_channel_arr(I) <= out_sosi_arr(I).channel; + out_err_arr(I) <= out_sosi_arr(I).err; + END GENERATE; + + out_sosi <= out_sosi_arr(0); -- take out_sosi control and info from out_sosi_arr(0) + + out_bsn <= TO_UINT(out_sosi.bsn); -- = out_bsn_arr().bsn = out_sosi_arr(I).bsn + + gen_verify_ctrl : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE + -- . Verify that sop and eop come in pairs + proc_dp_verify_sop_and_eop(dp_clk, out_val_arr(I), out_sop_arr(I), out_eop_arr(I), hold_out_sop_arr(I)); - in_sosi_arr <= (OTHERS => stimuli_sosi); + -- . Verify that the stimuli have been applied at all + hold_data_arr(I) <= out_data_arr(I) WHEN out_val_arr(I) = '1'; -- hold last valid data + proc_dp_verify_value("out_data_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_data_arr(I), hold_data_arr(I)); + proc_dp_verify_value("out_bsn_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_bsn_arr(I), out_bsn_arr(I)); + proc_dp_verify_value("out_channel_arr", e_equal, dp_clk, verify_done_arr(I), expected_out_channel_arr(I), out_channel_arr(I)); + END GENERATE; ------------------------------------------------------------------------------ -- DUT ------------------------------------------------------------------------------ - u_bsn_align : ENTITY work.mmp_dp_bsn_align_v2 + u_mmp_dp_bsn_align : ENTITY work.mmp_dp_bsn_align_v2 GENERIC MAP ( g_nof_streams => c_nof_streams, g_bsn_latency_max => c_bsn_latency_max, @@ -156,7 +379,11 @@ BEGIN g_block_size => c_block_size, g_bsn_w => c_bsn_w, g_data_w => c_data_w, - g_replacement_value => c_replacement_value, + g_data_replacement_value => c_data_replacement_value, + g_use_mm_output => c_use_mm_output, + g_pipeline_input => c_pipeline_input, + g_pipeline_output => c_pipeline_output, + g_rd_latency => c_rd_latency, g_nof_clk_per_sync => c_nof_clk_per_sync, g_nof_input_bsn_monitors => c_nof_input_bsn_monitors, g_use_bsn_output_monitor => c_use_bsn_output_monitor @@ -165,8 +392,8 @@ BEGIN mm_rst => mm_rst, mm_clk => mm_clk, - reg_copi => reg_copi, - reg_cipo => reg_cipo, + reg_bsn_align_copi => reg_bsn_align_copi, + reg_bsn_align_cipo => reg_bsn_align_cipo, reg_input_monitor_copi => reg_input_monitor_copi, reg_input_monitor_cipo => reg_input_monitor_cipo, @@ -181,9 +408,11 @@ BEGIN -- Streaming input in_sosi_arr => in_sosi_arr, -- Output via local MM in dp_clk domain - mm_copi => mm_copi, - mm_cipo_arr => mm_cipo_arr, - mm_sosi => mm_sosi + --mm_sosi => mm_sosi, + --mm_copi => mm_copi, + --mm_cipo_arr => mm_cipo_arr, + -- Output via streaming DP interface, when g_use_mm_output = TRUE. + out_sosi_arr => out_sosi_arr ); END tb; diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd index f47d2acf82d36d526f01bd4df781fd3e733b094f..dfafc97e2fe1d57c9ac1f2b90e5816792ca92c9d 100644 --- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd +++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd @@ -34,11 +34,10 @@ END tb_tb_dp_bsn_align_v2; ARCHITECTURE tb OF tb_tb_dp_bsn_align_v2 IS - CONSTANT c_bsn_latency_max : POSITIVE := 1; CONSTANT c_block : NATURAL := 11; CONSTANT c_period : NATURAL := 20; - CONSTANT c_delay_max : NATURAL := c_bsn_latency_max * c_period; - + CONSTANT c_nof_blk : NATURAL := 30; + SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end' BEGIN @@ -51,20 +50,35 @@ BEGIN -- g_block_period : NATURAL := 20; -- >= g_block_size, = g_block_size + c_gap_size -- g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN -- g_data_w : NATURAL := 16; -- number of bits in sosi data - -- c_replacement_value : INTEGER := 0; -- output sosi data replacement value for missing input blocks + -- g_data_replacement_value : INTEGER := 0; -- output sosi data replacement value for missing input blocks + -- g_disable_stream_id : NATURAL := 0; -- default 0 to enable all streams, > 0 selects stream that will be disabled + -- g_lost_stream_id : NATURAL := 0; -- default 0 to have all streams, > 0 selects stream that will be lost + -- g_lost_bsn_id : NATURAL := 10; -- for stream 1 the block with bsn = g_lost_bsn_id will be lost -- g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP - -- g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure + -- g_pipeline_input : NATURAL := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr + -- g_pipeline_output : NATURAL := 0; -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sop_arr -- g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure -- -- -- TB - -- g_tb_diff_delay_max : NATURAL := 45; -- maximum nof clk delay between any inputs, <= c_align_latency + -- g_tb_diff_delay : INTEGER := 0; -- 0 = aligned inputs, -1 = max input delay for no loss, + -- -- >~ g_bsn_latency_max * g_block_period will give loss -- g_tb_nof_restart : NATURAL := 1; -- number of times to restart the input stimuli -- g_tb_nof_blocks : NATURAL := 10 -- number of input blocks per restart - u_mm_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, TRUE, 0, 1, 0, 1, 50); - u_dp_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1, 0, 1, 50); - - u_diff_delay_no_loss : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1, c_delay_max, 1, 50); - --u_loss_replacement : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1, 40 + c_delay_max, 1, 50); + u_mm_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, TRUE, 0, 0, 1, 0, 2, c_nof_blk); + u_dp_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_dp_output_p1 : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 1, 1, 1, 0, 2, c_nof_blk); + u_bsn_lat_max_2 : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 2, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_bsn_lat_max_3 : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 3, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_p1_rd2 : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 1, 0, 2, 0, 2, c_nof_blk); + u_zero_gap : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_block, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_zero_gap_p1_rd2 : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_block, 32, 16, 17, 0, 0, 0, FALSE, 1, 1, 2, 0, 2, c_nof_blk); + u_stream_disable : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 2, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_stream_lost : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 2, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_stream_disable_lost : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (4, 1, 1, c_block, c_period, 32, 16, 17, 1, 2, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_bsn_lost : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 10, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_diff_delay : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, -1, 2, c_nof_blk); + u_nof_aligners : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 8, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, 0, 2, c_nof_blk); + u_nof_aligners_diff_delay : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (4, 1, 3, c_block, c_period, 32, 16, 17, 0, 0, 0, FALSE, 0, 0, 1, -1, 2, c_nof_blk); END tb; diff --git a/libraries/base/ring/hdllib.cfg b/libraries/base/ring/hdllib.cfg index 71e708ef4e749402e72a83a5a6d30c2cf47ff99a..68def31c56c077a85b39f2e6709429e30696fb37 100644 --- a/libraries/base/ring/hdllib.cfg +++ b/libraries/base/ring/hdllib.cfg @@ -8,6 +8,7 @@ synth_files = src/vhdl/ring_pkg.vhd src/vhdl/ring_lane_info_reg.vhd src/vhdl/ring_lane_info.vhd + src/vhdl/ring_info.vhd src/vhdl/ring_tx.vhd src/vhdl/ring_rx.vhd src/vhdl/ring_lane.vhd diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7bf41c8d6e2edf745627030bef40bca86b9e3b20 --- /dev/null +++ b/libraries/base/ring/src/vhdl/ring_info.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- +-- Author: R. van der Walle + +-- Purpose: +-- . Ring info register +-- Description: +-- See ring_pkg.vhd +-- Remark: +-- . +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, mm_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_field_pkg.ALL; +USE work.ring_pkg.ALL; + +ENTITY ring_info IS + PORT ( + -- Clocks and reset + mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk + mm_clk : IN STD_LOGIC; -- memory-mapped bus clock + + dp_clk : IN STD_LOGIC; + dp_rst : IN STD_LOGIC; + + reg_copi : IN t_mem_copi; + reg_cipo : OUT t_mem_cipo; + + ring_info : OUT t_ring_info + ); +END ring_info; + + +ARCHITECTURE str OF ring_info IS + + SIGNAL mm_fields_out : STD_LOGIC_VECTOR(field_slv_out_len(c_ring_info_field_arr)-1 DOWNTO 0); + +BEGIN + + u_mm_fields: ENTITY mm_lib.mm_fields + GENERIC MAP( + g_use_slv_in_val => FALSE, -- use FALSE to save logic when always slv_in_val='1' + g_field_arr => c_ring_info_field_arr + ) + PORT MAP ( + mm_clk => mm_clk, + mm_rst => mm_rst, + + mm_mosi => reg_copi, + mm_miso => reg_cipo, + + slv_clk => dp_clk, + slv_rst => dp_rst, + + slv_in_val => '1', + + slv_out => mm_fields_out + ); + + -- get "RW" fields from mm_fields + ring_info.O_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "O_rn") DOWNTO field_lo(c_ring_info_field_arr, "O_rn")); + ring_info.N_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "N_rn") DOWNTO field_lo(c_ring_info_field_arr, "N_rn")); + ring_info.rx_select <= mm_fields_out(field_hi(c_ring_info_field_arr, "rx_select") DOWNTO field_lo(c_ring_info_field_arr, "rx_select"))(0); + ring_info.tx_select <= mm_fields_out(field_hi(c_ring_info_field_arr, "tx_select") DOWNTO field_lo(c_ring_info_field_arr, "tx_select"))(0); +END str; + + + + + diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd index b6d9a7bbef957ad6421edbf665d8f69f54d3773e..3295e70d67e60cd721360dd7402b8c8048cb602e 100644 --- a/libraries/base/ring/src/vhdl/ring_lane.vhd +++ b/libraries/base/ring/src/vhdl/ring_lane.vhd @@ -82,9 +82,10 @@ ENTITY ring_lane IS reg_dp_block_validate_bsn_at_sync_copi : IN t_mem_copi; reg_dp_block_validate_bsn_at_sync_cipo : OUT t_mem_cipo; - ref_sync : IN STD_LOGIC; - this_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); - N_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0) + this_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + N_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + rx_select : IN STD_LOGIC := '0'; + tx_select : IN STD_LOGIC := '0' ); END ring_lane; @@ -141,8 +142,8 @@ BEGIN reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo, - ref_sync => ref_sync, -- bs_sosi.sync? - rx_select => lane_info.rx_select, + ref_sync => bs_sosi.sync, + rx_select => rx_select, this_rn => this_rn, N_rn => N_rn ); @@ -169,7 +170,7 @@ BEGIN reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_tx_cipo, - tx_select => lane_info.tx_select, + tx_select => tx_select, remove_channel => lane_info.transport_nof_hops, this_rn => this_rn, N_rn => N_rn diff --git a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd index cc805353e543a1948f9d33736934bb15fc86d759..48c704142417e3ff572ea8ca378d5cf9b76ade86 100644 --- a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd +++ b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd @@ -104,7 +104,5 @@ BEGIN -- get "RW" fields from mm_fields lane_info_wr.transport_nof_hops <= mm_fields_out(field_hi(c_lane_info_field_arr, "transport_nof_hops") DOWNTO field_lo(c_lane_info_field_arr, "transport_nof_hops")); - lane_info_wr.tx_select <= sl(mm_fields_out(field_hi(c_lane_info_field_arr, "tx_select") DOWNTO field_lo(c_lane_info_field_arr, "tx_select"))); - lane_info_wr.rx_select <= sl(mm_fields_out(field_hi(c_lane_info_field_arr, "rx_select") DOWNTO field_lo(c_lane_info_field_arr, "rx_select"))); END str; diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd index 11a4e1e5c20b1aaf5c469d77a27f5ffdda3d67ea..5af05ebbbe88845840e3b9dfc33fc559ac8d338e 100644 --- a/libraries/base/ring/src/vhdl/ring_pkg.vhd +++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd @@ -51,6 +51,27 @@ PACKAGE ring_pkg is -- | | | Hence for N_lanes = 8, lanes 0, 2, 4, and 6 will transport in positive | | -- | | | direction, and lanes 1, 3, 5, 7 will transport in opposite (= negative) | | -- | | | direction. The lane direction is fixed per lane and therefore read only. | | +-- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+ + + TYPE t_lane_info IS RECORD + transport_nof_hops : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); + lane_direction : STD_LOGIC; + END RECORD; + + CONSTANT c_lane_info_rst : t_lane_info := + ( (OTHERS => '0'), '0' ); + + CONSTANT c_lane_info_field_arr : t_common_field_arr(1 DOWNTO 0) := + ( (field_name_pad("transport_nof_hops"), "RW", 32, field_default(0)), + (field_name_pad("lane_direction"), "RO", 1, field_default(0)) ); + +-- ring info, see https://support.astron.nl/confluence/x/jyu7Ag +-- +====================+========+==============================================================================+===========================+ +-- | Field | Access | Description | Remark | +-- +====================+========+==============================================================================+===========================+ +-- | O_rn | RW | Offset index of the first global node (GN) in the ring. | Same setting for all RN | +-- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+ +-- | N_rn | RW | The number of ring nodes (RN) in the closed ring. | Same setting for all RN | -- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+ -- | tx_select | RW | 0 = transmit via on board port, 1 = transmit via cable (QSFP) port. Default | Individual setting per RN | -- | | | in firmware assume cable between RN on different UniBoard2 and assume cable | | @@ -62,22 +83,21 @@ PACKAGE ring_pkg is -- | | | close the ring defined by ring_info. The programmable rx_select allows using | | -- | | | cables between other RN in the ring. | | -- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+ - - TYPE t_lane_info IS RECORD - transport_nof_hops : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); - lane_direction : STD_LOGIC; - tx_select : STD_LOGIC; - rx_select : STD_LOGIC; + TYPE t_ring_info IS RECORD + O_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + N_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + tx_select : STD_LOGIC; + rx_select : STD_LOGIC; END RECORD; - CONSTANT c_lane_info_rst : t_lane_info := - ( (OTHERS => '0'), '0', '0', '0' ); + CONSTANT c_ring_info_rst : t_ring_info := + ( (OTHERS => '0'), (OTHERS => '0'), '0', '0' ); - CONSTANT c_lane_info_field_arr : t_common_field_arr(3 DOWNTO 0) := - ( (field_name_pad("transport_nof_hops"), "RW", 32, field_default(0)), - (field_name_pad("lane_direction"), "RO", 1, field_default(0)), - (field_name_pad("tx_select"), "RW", 1, field_default(0)), - (field_name_pad("rx_select"), "RW", 1, field_default(0)) ); + CONSTANT c_ring_info_field_arr : t_common_field_arr(3 DOWNTO 0) := + ( (field_name_pad("O_rn"), "RW", 8, field_default( 0)), + (field_name_pad("N_rn"), "RW", 8, field_default(16)), + (field_name_pad("tx_select"), "RW", 1, field_default( 0)), + (field_name_pad("rx_select"), "RW", 1, field_default( 0)) ); CONSTANT c_ring_eth_dst_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"FFFFFFFFFFFF"; CONSTANT c_ring_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"002286080000"; diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd index 7744465c7ab13d171cc7d1fde94f8754c59bcbd5..7b152204a3d02b20209eb8084ca95ed8e6b99dbf 100644 --- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd +++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd @@ -49,10 +49,8 @@ ARCHITECTURE tb OF tb_ring_lane_info IS CONSTANT c_cross_clock_domain_latency : NATURAL := 20; -- used mm_adresses on mm bus - CONSTANT c_mm_addr_rx_select : NATURAL := 0; - CONSTANT c_mm_addr_tx_select : NATURAL := 1; - CONSTANT c_mm_addr_lane_direction : NATURAL := 2; - CONSTANT c_mm_addr_transport_nof_hops : NATURAL := 3; + CONSTANT c_mm_addr_lane_direction : NATURAL := 0; + CONSTANT c_mm_addr_transport_nof_hops : NATURAL := 1; SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_mm_reg_end : STD_LOGIC := '0'; @@ -91,8 +89,6 @@ BEGIN -- default all register hold value 0, try to write 1 in all registers proc_mem_mm_bus_wr(c_mm_addr_transport_nof_hops ,11 ,mm_clk, reg_miso, reg_mosi); proc_mem_mm_bus_wr(c_mm_addr_lane_direction ,1 ,mm_clk, reg_miso, reg_mosi); -- RO - proc_mem_mm_bus_wr(c_mm_addr_tx_select ,1 ,mm_clk, reg_miso, reg_mosi); - proc_mem_mm_bus_wr(c_mm_addr_rx_select ,1 ,mm_clk, reg_miso, reg_mosi); proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency); @@ -104,14 +100,6 @@ BEGIN mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1); ASSERT mm_natural_response /= 1 REPORT "wrong lane_direction (not read only)" SEVERITY ERROR; - proc_mem_mm_bus_rd(c_mm_addr_tx_select, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); - mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1); - ASSERT mm_natural_response = 1 REPORT "wrong tx_select" SEVERITY ERROR; - - proc_mem_mm_bus_rd(c_mm_addr_rx_select, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk); - mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1); - ASSERT mm_natural_response = 1 REPORT "wrong rx_select" SEVERITY ERROR; - proc_common_wait_some_cycles(mm_clk, 100); tb_mm_reg_end <= '1'; WAIT; @@ -125,8 +113,6 @@ BEGIN ASSERT TO_UINT(lane_info.transport_nof_hops) = 11 REPORT "wrong lane_info.transport_nof_hops value" SEVERITY ERROR; ASSERT lane_info.lane_direction = '0' REPORT "wrong lane_info.lane_direction value" SEVERITY ERROR; - ASSERT lane_info.tx_select = '1' REPORT "wrong lane_info.tx_select value" SEVERITY ERROR; - ASSERT lane_info.rx_select = '1' REPORT "wrong lane_info.rx_select value" SEVERITY ERROR; proc_common_wait_some_cycles(mm_clk, 100); tb_end <= '1'; diff --git a/libraries/base/util/util.peripheral.yaml b/libraries/base/util/util.peripheral.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2a4a75357795c7a3fcef7f98b31b720e96ad0776 --- /dev/null +++ b/libraries/base/util/util.peripheral.yaml @@ -0,0 +1,29 @@ +schema_name: args +schema_version: 1.0 +schema_type: peripheral + +hdl_library_name: util +hdl_library_description: "Util Heater." +peripherals: + - peripheral_name: heater # pi_heater.py + peripheral_description: "Heater component, see util_heater.vhd" + parameters: + - { name: c_nof_mac4_max, value: 800 } + - { name: c_reg_nof_words, value: c_nof_mac4_max // 32 } # = 25 + mm_ports: + # MM port for util_heater.vhd + - mm_port_name: REG_HEATER + mm_port_type: REG + mm_port_span: ceil_pow2(25) * MM_BUS_SIZE #ceil_pow2(c_reg_nof_words) * MM_BUS_SIZE + mm_port_description: "Heater control." + fields: + - - field_name: enable + field_description: | + "The heater elements can be enabled or disabled via this MM register. + Each heater element consists of a MAC4. A MAC4 uses 4 18x18 multipliers. + The MM register allows enabling 0, 1, more or all MAC4 under SW control. + In this way it is possible to vary the power consumption during run time." + number_of_fields: 25 #c_reg_nof_words + address_offset: 0x0 + + diff --git a/libraries/io/ddr/ddr.peripheral.yaml b/libraries/io/ddr/ddr.peripheral.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b2cbd21a659e3682d4ca23512caee423de5bbb86 --- /dev/null +++ b/libraries/io/ddr/ddr.peripheral.yaml @@ -0,0 +1,65 @@ +schema_name: args +schema_version: 1.0 +schema_type: peripheral + +hdl_library_name: ddr +hdl_library_description: "Double data rate memory" + +peripherals: + - peripheral_name: io_ddr # pi_io_ddr.py + peripheral_description: "DDR controller" + mm_ports: + # MM port for io_ddr_reg.vhd + - mm_port_name: REG_IO_DDR + mm_port_type: REG + mm_port_span: 8 * MM_BUS_SIZE + mm_port_description: "DDR controller registers." + number_of_mm_ports: 1 + fields: + - - field_name: reg_io_ddr + field_description: | + "IO DDR status bits concatenated: + ctlr_tech_mosi.wr & ctlr_tech_miso.rdval & ctlr_tech_miso.cal_fail & ctlr_tech_miso.cal_ok + ctlr_rst_out_i & ctlr_wr_flush_en & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done" + address_offset: 0 * MM_BUS_SIZE + access_mode: RO + - - field_name: reg_rd_fifo_used + field_description: "Read FIFO fill level." + address_offset: 1 * MM_BUS_SIZE + access_mode: RO + - - field_name: reg_wr_fifo_used + field_description: "Write FIFO fill level." + address_offset: 2 * MM_BUS_SIZE + access_mode: RO + - - field_name: reg_fifo_full + field_description: "Read FIFO full bit & Write FIFO full bit" + address_offset: 3 * MM_BUS_SIZE + access_mode: RO + - - field_name: reg_burstbegin + field_description: "Start write or read access to DDR when reg_burstbegin = 1." + address_offset: 8 * MM_BUS_SIZE + access_mode: WO + - - field_name: reg_wr_not_rd + field_description: "Set read / write mode. reg_wr_not_rd = 1 = write mode, reg_wr_not_rd = 0 = read mode." + address_offset: 9 * MM_BUS_SIZE + access_mode: WO + - - field_name: reg_done + field_description: "reg_done = 1 when memory access is finished." + address_offset: 10 * MM_BUS_SIZE + access_mode: RO + - - field_name: reg_address + field_description: "Start address for memory access." + address_offset: 13 * MM_BUS_SIZE + access_mode: WO + - - field_name: reg_burstsize + field_description: "Access size for memory access" + address_offset: 14 * MM_BUS_SIZE + access_mode: WO + - - field_name: reg_flush + field_description: | + "Flush the write FIFO + The user input to the write FIFO sohuld be off. Internally the method waits sufficient us to + ensure that the write FIFO is read empty." + address_offset: 15 * MM_BUS_SIZE + + diff --git a/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml new file mode 100644 index 0000000000000000000000000000000000000000..215c802fa4674c5f8f301d6f47eef4373ddbb760 --- /dev/null +++ b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml @@ -0,0 +1,179 @@ +schema_name: args +schema_version: 1.0 +schema_type: peripheral + +hdl_library_name: tr_10GbE # copy of nw_10GbE. +hdl_library_description: "Network peripherals for 10GbE." + +peripherals: + - peripheral_name: tr_10GbE_unb2legacy # pi_nw_10GbE_unb2legacy.py / pi_tr_10GbE.py / pi_tr_10GbE_unb2.py + peripheral_description: | + "M&C of Intel Low Latency (LL) 10GbE MAC control status register (CSR) see [1] + + The LL 10GbE MAC is used with the legacy address map option of the old 10GbE MAC, see [2], this implies: + . Some registers have a different address offset in [1] and [2] + . The 36 bit registers are stored at word 0 = [31:0] and word 1 = [3:0] = [35:32] in [1], but in [2] + they are stored with their 4 most significant bits first and their 32 least significant bits last, so + with word 0 = [3:0] = [35:32] and word 1 = [31:0]. + Here the address map and 36 bit word order from [2] are used. + + [1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf + [2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf + " + parameters: + # Parameters of nw_10GbE.vhd / tr_10GbE.vhd + - { name: g_nof_macs, value: 1 } + mm_ports: + # MM port for reg_mac_mosi = mac_mosi in ip_arria10_e1sg_eth_10g.vhd + # Use tr_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses + - mm_port_name: REG_TR_10GBE_MAC + mm_port_type: REG + mm_port_description: "MAC registers" + number_of_mm_ports: g_nof_macs + fields: + - - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000 + - - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001 + - - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040 + - - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080 + - - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0300 } # = 0x00C0 + - - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0308 } # = 0x00C2 + - - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100 + - - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140 + - - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800 + - - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801 + - - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802 + - - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803 + - - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804 + - - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805 + - - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806 + - - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807 + - - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808 + - - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809 + - - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A + - - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B + - - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818 + - - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000 + - - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001 + - - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040 + - - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080 + - - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x4300 } # = 0x10C0 + - - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100 + - - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140 + - - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141 + - - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142 + # Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved: + - - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180 + - - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181 + - - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182 + - - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183 + - - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184 + - - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185 + - - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186 + - - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187 + - - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190 + - - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191 + - - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192 + - - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193 + - - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194 + - - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195 + - - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196 + - - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197 + - - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0 + - - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200 + - - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201 + - - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202 + - - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801 + - - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00 + - - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00 + - - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3008 } # = 0x0C02 + - - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7008 } # = 0x1C02 + - - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3010 } # = 0x0C04 + - - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7010 } # = 0x1C04 + - - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3018 } # = 0x0C06 + - - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7018 } # = 0x1C06 + - - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3020 } # = 0x0C08 + - - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7020 } # = 0x1C08 + - - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A + - - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A + - - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C + - - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C + - - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E + - - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E + - - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3040 } # = 0x0C10 + - - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7040 } # = 0x1C10 + - - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3048 } # = 0x0C12 + - - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7048 } # = 0x1C12 + - - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3050 } # = 0x0C14 + - - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7050 } # = 0x1C14 + - - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3058 } # = 0x0C16 + - - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7058 } # = 0x1C16 + - - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3060 } # = 0x0C18 + - - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7060 } # = 0x1C18 + - - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A + - - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A + - - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C + - - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C + - - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E + - - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E + - - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3080 } # = 0x0C20 + - - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7080 } # = 0x1C20 + - - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3088 } # = 0x0C22 + - - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7088 } # = 0x1C22 + - - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3090 } # = 0x0C24 + - - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7090 } # = 0x1C24 + - - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3098 } # = 0x0C26 + - - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7098 } # = 0x1C26 + - - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28 + - - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28 + - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A + - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A + - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C + - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C + - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E + - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E + - - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30 + - - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30 + - - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32 + - - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32 + - - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34 + - - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34 + - - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36 + - - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36 + - - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38 + - - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38 + - - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A + - - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A + - - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C + - - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C + + + - peripheral_name: tr_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py + peripheral_description: "10GbE link status register" + parameters: + # Parameters of nw_10GbE.vhd / tr_10GbE.vhd + - { name: g_nof_macs, value: 1 } + mm_ports: + # MM port for reg_eth10g_mosi in ip_arria10_e1sg_eth_10g.vhd / common_reg_r_w_dc.vhd + - mm_port_name: REG_TR_10GBE_ETH10G + mm_port_type: REG + mm_port_description: "" + number_of_mm_ports: g_nof_macs + fields: + - - field_name: tx_snk_out_xon + field_description: "" + address_offset: 0x0 + mm_width: 1 + bit_offset: 0 + access_mode: RO + - - field_name: xgmii_tx_ready + field_description: "" + address_offset: 0x0 + mm_width: 1 + bit_offset: 1 + access_mode: RO + - - field_name: xgmii_link_status + field_description: "" + address_offset: 0x0 + mm_width: 2 + bit_offset: 2 + access_mode: RO