From 072ebde0a7345c5ec64d5a82f43b013e8ba1b0b6 Mon Sep 17 00:00:00 2001 From: Eric Kooistra <kooistra@astron.nl> Date: Wed, 4 Aug 2021 11:24:50 +0200 Subject: [PATCH] Corrected col7 = number_of_fields for statistics (SST, BST and XST). --- .../lofar2_unb2b_sdp_station.mmap.gold | 6 +++--- .../lofar2_unb2b_sdp_station.mmap.qsys.gold | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold index 43436c8793..fc08722737 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold @@ -146,7 +146,7 @@ number_of_columns = 13 RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024 REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - - - RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] - 2048 + RAM_ST_SST 1 6 RAM data 0x00044000 1024 RW uint64 b[31:0] b[31:0] - 2048 - - - - - 0x00042001 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - - @@ -198,7 +198,7 @@ number_of_columns = 13 REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0004c000 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x0004c001 - - - b[31:0] b[63:32] - - REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0004e000 1 RW uint32 b[31:0] - - - - RAM_ST_XSQ 1 1 RAM data 0x00050000 576 RW cint64_ir b[31:0] b[31:0] - - + RAM_ST_XSQ 1 1 RAM data 0x00050000 144 RW cint64_ir b[31:0] b[31:0] - - - - - - - 0x0004e001 - - - b[31:0] b[63:32] - - REG_CROSSLETS_INFO 1 1 REG offset 0x00052000 15 RW uint32 b[31:0] - - - - - - - step 0x0005200f 1 RW uint32 b[31:0] - - - @@ -298,7 +298,7 @@ number_of_columns = 13 - - - - eth_destination_mac 0x00066028 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x00066029 - - - b[15:0] b[47:32] - - REG_DP_XONOFF 2 1 REG enable_stream 0x00068000 1 RW uint32 b[0:0] - 2 2 - RAM_ST_BST 2 1 RAM data 0x0006a000 1952 RW uint64 b[31:0] b[31:0] 2048 2048 + RAM_ST_BST 2 1 RAM data 0x0006a000 976 RW uint64 b[31:0] b[31:0] 2048 2048 - - - - - 0x00068001 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_BST 2 1 REG enable 0x0006c000 1 RW uint32 b[0:0] - 2 2 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0006e000 1 RW uint64 b[31:0] b[31:0] 64 64 diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold index 6bc74963e3..96b6cb35c1 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold @@ -146,7 +146,7 @@ number_of_columns = 13 RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024 REG_DP_SELECTOR 1 1 REG input_select 0x0002d066 1 RW uint32 b[0:0] - - - - RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] - 2048 + RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048 - - - - - 0x0002d067 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d060 1 RW uint32 b[0:0] - - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - - @@ -198,7 +198,7 @@ number_of_columns = 13 REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0002d05c 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x0002d05d - - - b[31:0] b[63:32] - - REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0002d05e 1 RW uint32 b[31:0] - - - - RAM_ST_XSQ 1 1 RAM data 0x00018000 576 RW cint64_ir b[31:0] b[31:0] - - + RAM_ST_XSQ 1 1 RAM data 0x00018000 144 RW cint64_ir b[31:0] b[31:0] - - - - - - - 0x0002d05f - - - b[31:0] b[63:32] - - REG_CROSSLETS_INFO 1 1 REG offset 0x0002d000 15 RW uint32 b[31:0] - - - - - - - step 0x0002d00f 1 RW uint32 b[31:0] - - - @@ -298,7 +298,7 @@ number_of_columns = 13 - - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x00000ca9 - - - b[15:0] b[47:32] - - REG_DP_XONOFF 2 1 REG enable_stream 0x0002d054 1 RW uint32 b[0:0] - 2 2 - RAM_ST_BST 2 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] 2048 2048 + RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048 - - - - - 0x0002d055 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_BST 2 1 REG enable 0x0002d050 1 RW uint32 b[0:0] - 2 2 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64 -- GitLab