diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 06ecd9274302f8b4446b781391f51c979ea40571..980a6cd138764707de53499177419dd371581b31 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -37,7 +37,6 @@ PACKAGE lofar2_unb2b_filterbank_pkg IS
END RECORD;
-- nofjesd, nofdb, nofinput
- CONSTANT c_one_node : t_lofar2_unb2b_filterbank_config := ( 12, 2, 1 );
CONSTANT c_full : t_lofar2_unb2b_filterbank_config := ( 12, 2, 12 );
-- Function to select the revision configuration.
@@ -51,9 +50,8 @@ PACKAGE BODY lofar2_unb2b_filterbank_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_filterbank_config IS
BEGIN
- IF g_design_name = "lofar2_unb2b_filterbank_one_node" THEN RETURN c_one_node;
- ELSIF g_design_name = "lofar2_unb2b_filterbank_full" THEN RETURN c_full;
- ELSE RETURN c_one_node;
+ IF g_design_name = "lofar2_unb2b_filterbank_full" THEN RETURN c_full;
+ ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_multichannel.vhd
deleted file mode 100644
index a95b3ba69a2219e2a0011a523c668c2bee05feab..0000000000000000000000000000000000000000
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_multichannel.vhd
+++ /dev/null
@@ -1,502 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2018
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author: Jonathan Hargreaves
--- Purpose: Tb to show that lofar2_unb2b_filterbank can simulate
--- Description:
--- Must use c_sim = TRUE to speed up simulation
--- This is a compile-only test bench
--- Usage:
--- Load sim # check that design can load in vsim
--- > as 10 # check that the hierarchy for g_design_name is complete
--- > run -a # check that design can simulate some us without error
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL;
-USE common_lib.tb_common_pkg.ALL;
-USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
-
-ENTITY tb_lofar2_unb2b_filterbank_multichannel IS
-END tb_lofar2_unb2b_filterbank_multichannel;
-
-ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_multichannel IS
-
- CONSTANT c_sim : BOOLEAN := TRUE;
- CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
- CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
- CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
-
- CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
- CONSTANT c_ext_clk_period : TIME := 5 ns;
- CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
- CONSTANT c_bondingclk_period : TIME := 10 ns;
- CONSTANT c_sysref_period : NATURAL := 10000; -- number of sample clocks between sysref pulses
-
- -- Transport delays
- TYPE t_time_arr IS ARRAY (0 TO 11) OF TIME;
- CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
- CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps) ; -- transport delays tx to rx data
- CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps) ; -- transport delays clock source to adc(tx)
- CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
-
-
-
- -- clocks and resets for the jesd204b tx
- SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
- SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
- SIGNAL txphy_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
- SIGNAL mm_rst : STD_LOGIC;
- SIGNAL avs_rst_n : STD_LOGIC;
- SIGNAL txlink_rst_n : STD_LOGIC;
- SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 downto 0);
- SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 downto 0);
- SIGNAL tx_bonding_clocks : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
- SIGNAL bonding_clock_0 : STD_LOGIC := '0';
- SIGNAL bonding_clock_1 : STD_LOGIC := '0';
- SIGNAL bonding_clock_2 : STD_LOGIC := '0';
- SIGNAL bonding_clock_3 : STD_LOGIC := '0';
- SIGNAL bonding_clock_4 : STD_LOGIC := '0';
- SIGNAL bonding_clock_5 : STD_LOGIC := '0';
- SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
-
- CONSTANT c_mm_clk_period : TIME := 20 ns;
- SIGNAL mm_clk : STD_LOGIC := '0';
-
- -- Tb
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL sim_done : STD_LOGIC := '0';
-
- -- DUT
- SIGNAL ext_clk : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
-
- SIGNAL WDI : STD_LOGIC;
- SIGNAL INTA : STD_LOGIC;
- SIGNAL INTB : STD_LOGIC;
-
- SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
-
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
- -- serial transceivers
- SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
- SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0) := (others => '0');
-
- -- jesd204b syncronization signals and delayed copies
- SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sampclk : STD_LOGIC := '0';
-
- SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
- SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
- SIGNAL jesd204b_sysref_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sysref_adc_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sysref_adc_2 : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sync_n_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_sync_n_fpga : STD_LOGIC_VECTOR(11 DOWNTO 0);
-
- -- Test bench data
- SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(11 DOWNTO 0);
- SIGNAL jesd204b_tx_link_valid : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
-
- -- Diagnostic signals
- SIGNAL avs_chipselect : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL avs_read : STD_LOGIC_VECTOR(11 DOWNTO 0);
- SIGNAL avs_readdata : t_slv_32_arr(11 DOWNTO 0);
- SIGNAL avs_address : t_slv_8_arr(11 DOWNTO 0);
-
-BEGIN
-
-
- ----------------------------------------------------------------------------
- -- System setup
- ----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
- ------------------------------------------------------------------------------
- -- External PPS
- ------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
- --jesd204b_sysref <= pps;
-
- ------------------------------------------------------------------------------
- -- DUT
- ------------------------------------------------------------------------------
- u_lofar_unb2b_filterbank : ENTITY work.lofar2_unb2b_filterbank
- GENERIC MAP (
- g_design_name => "lofar2_unb2b_filterbank_full",
- g_design_note => "Lofar2 filterbank",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- PORT MAP (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => bck_rx,
- JESD204B_REFCLK => jesd204b_sampclk_fpga,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref_fpga,
- JESD204B_SYNC_N => jesd204b_sync_n_fpga
- );
-
-
- -----------------------------------------------------------------------------
- -- Transport
- -----------------------------------------------------------------------------
-
- gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
- jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
- jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
--- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
- bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
- jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
- END GENERATE;
-
- jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
- jesd204b_sysref_fpga <= transport jesd204b_sysref after c_delay_sysreftofpga;
-
- -----------------------------------------------------------------------------
- -- Use a jesd204b instance in TX-ONLY modeTransmit Only.
- -----------------------------------------------------------------------------
-
- gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
- u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- PORT MAP
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, --out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), --out
- jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
- mdev_sync_n => dev_sync_n(i), --in
- pll_locked => pll_locked, --in
- sync_n => jesd204b_sync_n_adc(i), --in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
-
- -- Generate test pattern at each ADC
-
- proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
- VARIABLE data : INTEGER := 0;
- VARIABLE even_sample : BOOLEAN := TRUE;
- BEGIN
- IF mm_rst = '1' THEN
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- data := 0;
- even_sample := TRUE;
- ELSE
- IF rising_edge(jesd204b_sampclk_adc(i)) THEN
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
- IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
- data := 1000;
- ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
- data := -1000;
- ELSE
- data := 0;
- END IF;
-
- -- Frame the data to 32 bits at half the rate
- IF(jesd204b_tx_link_ready(i) = '0') THEN
- even_sample := TRUE;
- ELSE
- even_sample := not even_sample;
- END IF;
- IF (even_sample = TRUE) THEN
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- ELSE
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- END IF;
-
- END IF;
- END IF;
- END PROCESS;
-
-
-
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- Stimulii
- -----------------------------------------------------------------------------
-
- -- Clocks and resets
- mm_clk <= not mm_clk after c_mm_clk_period/2;
- mm_rst <= '1', '0' after 800 ns;
- avs_rst_n <= '0', '1' after 23500 ns;
- tx_analogreset(0) <= '1', '0' after 18500 ns;
- tx_digitalreset(0) <= '1', '0' after 23000 ns;
- txlink_rst_n <= '0', '1' after 25500 ns;
- pll_locked(0) <= '0', '1' after 1000 ns;
-
- bonding_clock_5 <= not bonding_clock_5 after 250 ps;
- bonding_clock_4 <= not bonding_clock_4 after 250 ps;
- bonding_clock_3 <= not bonding_clock_3 after 500 ps;
- bonding_clock_2 <= not bonding_clock_2 after 500 ps;
- bonding_clock_0 <= not bonding_clock_0 after 2500 ps;
-
- bonding_clock_1_process : process
- begin
- bonding_clock_1 <= '0';
- wait for 4000 ps;
- bonding_clock_1 <= '1';
- wait for 1000 ps;
- end process;
-
- tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps;
- tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps;
- tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps;
- tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps;
- tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps;
- tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
-
- -- Sample Clock
- jesd204b_sampclk <= NOT jesd204b_sampclk AFTER c_jesd204b_sampclk_period/2; -- JESD sample clock (200MHz)
-
- -- clock source process
-
- proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
- VARIABLE count : NATURAL := 0;
- BEGIN
- IF mm_rst = '1' THEN
- jesd204b_sysref <= '0';
- count := 0;
- ELSE
- IF rising_edge(jesd204b_sampclk) THEN
- IF (count = c_sysref_period-1) THEN
- count := 0;
- ELSE
- count := count + 1;
- END IF;
-
- IF count > c_sysref_period-8 THEN
- jesd204b_sysref <= '1';
- ELSE
- jesd204b_sysref <= '0';
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- ------------------------------------------------------------------------------
- -- Diagnostics
- ------------------------------------------------------------------------------
- proc_read_avs_regs : PROCESS
- BEGIN
- wait for 100ns;
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait until avs_rst_n = '1';
- while true loop
- wait until rising_edge(mm_clk);
- avs_address(0) <= X"14"; -- dll control
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- wait until rising_edge(mm_clk);
- avs_address(0) <= X"15"; -- syncn_sysref control
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- wait until rising_edge(mm_clk);
-
- avs_address(0) <= X"18"; -- syncn_sysref control
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- wait until rising_edge(mm_clk);
- avs_address(0) <= X"19"; -- syncn_sysref control
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- wait until rising_edge(mm_clk);
-
- avs_address(0) <= X"20"; -- tx control0
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- wait until rising_edge(mm_clk);
- avs_address(0) <= X"26"; -- tx control0
- avs_chipselect(0) <= '1';
- avs_read(0) <= '1';
- wait for c_mm_clk_period * 1;
- wait until rising_edge(mm_clk);
- avs_address(0) <= (others => '0');
- avs_chipselect(0) <= '0';
- avs_read(0) <= '0';
- wait for c_mm_clk_period * 32;
- END LOOP;
- END PROCESS;
-
- ------------------------------------------------------------------------------
- -- Simulation end
- ------------------------------------------------------------------------------
- --sim_done <= '0', '1' AFTER 1 us;
- sim_done <= '0';
-
- proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
-
-END tb;