diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index d3198bf0d2b4db7888cd4efed534c3cdc08ca31d..3c63f38cd1b46e389ec71d96f70af019f539ee1f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -21,8 +21,14 @@
-- Usage:
-- > as 7 # default
-- > as 12 # for detailed debugging
--- > run -a
+-- > run -a # takes about 250 us --> c_eth_runtime_timeout
--
+-- Remark:
+-- - Only verify that there is statistics offload.
+-- - The statistics data gets undefined, due to that the c_nof_block_per_sync
+-- is too short to offload 12 SST packets via 1GbE. This causes that new
+-- data is available before the old data has been offloaded. Therefore use
+-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
USE IEEE.std_logic_1164.ALL;
@@ -72,13 +78,15 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
-- . 1GbE output
- CONSTANT c_eth_check_nof_packets : NATURAL := 4512; -- received packets in 2 sync periods
- CONSTANT c_eth_runtime_timeout : TIME := 100 ms; -- factor 2 margin
+ CONSTANT c_eth_check_nof_packets : NATURAL := 1;
+ CONSTANT c_eth_runtime_timeout : TIME := 300 us;
-- MM
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_reg_stat_enable_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_SST";
+ CONSTANT c_mm_file_reg_stat_hdr_dat_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_DAT_SST";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -110,12 +118,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0);
BEGIN
@@ -192,9 +200,7 @@ BEGIN
tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock
p_mm_stimuli : PROCESS
- CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
- CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
- VARIABLE v_bsn : NATURAL;
+ VARIABLE v_bsn : NATURAL;
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
@@ -235,7 +241,7 @@ BEGIN
WAIT FOR c_sdp_T_sub * 2;
-- Offload enable
- mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_sst, 0, 1, tb_clk);
-- End Simulation
proc_common_wait_until_high(ext_clk, eth_done);
@@ -246,12 +252,10 @@ BEGIN
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : ENTITY eth_lib.eth_statistics
- GENERIC MAP (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout,
- g_check_nof_valid => TRUE,
- g_check_nof_valid_ref => c_eth_check_nof_packets
- )
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
PORT MAP (
eth_serial_in => eth_txp(0),
tb_end => eth_done
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 5e4731f8efc4c1ec2c19ca601199af0f98a27a60..2129d701d1eddfa82e247b8c4ae31ef9a225cbf3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -20,9 +20,15 @@
-- Test statistics offload with "ethernet packet statistics" in wave window only
-- Usage:
-- > as 7 # default
--- > as 12 # for detailed debugging
--- > run -a
+-- > as 14 # for detailed debugging of Eth sim tx link
+-- > run -a # takes about 250 us --> c_eth_runtime_timeout
--
+-- Remark:
+-- - Only verify that there is statistics offload.
+-- - The statistics data gets undefined, due to that the c_nof_block_per_sync
+-- is too short to offload 12 SST packets via 1GbE. This causes that new
+-- data is available before the old data has been offloaded. Therefore use
+-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
USE IEEE.std_logic_1164.ALL;
@@ -72,13 +78,15 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station IS
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
-- . 1GbE output
- CONSTANT c_eth_check_nof_packets : NATURAL := 4512; -- received packets in 2 sync periods
- CONSTANT c_eth_runtime_timeout : TIME := 100 ms; -- factor 2 margin
+ CONSTANT c_eth_check_nof_packets : NATURAL := 1;
+ CONSTANT c_eth_runtime_timeout : TIME := 300 us;
-- MM
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_reg_stat_enable_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_SST";
+ CONSTANT c_mm_file_reg_stat_hdr_dat_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_DAT_SST";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -100,27 +108,29 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_clk_slv : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
- SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+ SIGNAL eth_clk_slv : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_txp_slv : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp_slv : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
-- back transceivers
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0);
BEGIN
-- System setup
ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
- eth_clk_slv <= (OTHERS => eth_clk);
+ -- Ethernet ref clock (125 MHz)
+ eth_clk_slv(0) <= (NOT eth_clk_slv(0)) OR tb_end AFTER c_eth_clk_period/2;
+ eth_clk_slv(1) <= '0'; -- not used
+
+ -- JESD sample clock (200MHz)
+ JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -156,8 +166,8 @@ BEGIN
-- 1GbE Control Interface
ETH_CLK => eth_clk_slv,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
+ ETH_SGIN => eth_rxp_slv,
+ ETH_SGOUT => eth_txp_slv,
-- LEDs
QSFP_LED => open,
@@ -177,8 +187,6 @@ BEGIN
tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock
p_mm_stimuli : PROCESS
- CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
- CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
VARIABLE v_bsn : NATURAL;
BEGIN
-- Wait for DUT power up after reset
@@ -220,7 +228,7 @@ BEGIN
WAIT FOR c_sdp_T_sub * 2;
-- Offload enable
- mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_sst, 0, 1, tb_clk);
-- End Simulation
proc_common_wait_until_high(ext_clk, eth_done);
@@ -231,14 +239,12 @@ BEGIN
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : ENTITY eth_lib.eth_statistics
- GENERIC MAP (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout,
- g_check_nof_valid => TRUE,
- g_check_nof_valid_ref => c_eth_check_nof_packets
- )
- PORT MAP (
- eth_serial_in => eth_txp(0),
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp_slv(0),
tb_end => eth_done
);