diff --git a/applications/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
index 0ddc40de8e1bb8def086693c583645319bdf6543..f8141ef5d1090acff88ab257cce05e8156fd9cd8 100644
--- a/applications/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+++ b/applications/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
@@ -139,7 +139,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
true, c_wpfb_use_separate, 16, c_wpfb_out_dat_w, 18, 2, true, 56, 2,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
- CONSTANT c_wpfb_coefs_file_prefix : STRING := "../../../../../UniBoard/trunk/Firmware/dsp/filter/build/data/coefs_wide";
+ CONSTANT c_wpfb_coefs_file_prefix : STRING := "../../../../../UniBoard/trunk/Firmware/dsp/filter/build/data/coefs_wide1_p64_t8";
-- Correlator
CONSTANT c_nof_inputs : NATURAL := 24;
@@ -396,7 +396,8 @@ BEGIN
clk_clk => CLK, -- altpll_1 ref clk (200MHz)
clk_clk_in_reset_reset_n => xo_rst_n,
- altpll_1_c0_clk => dp_clk, -- altpll_1 output clock
+
+ dp_clk => dp_clk, -- altpll_1 output clock
-- PIOs
pout_wdi => pout_wdi,
diff --git a/applications/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd b/applications/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
index 8fbfa867085a8dca1315fcb440d27599821cb0f5..0bcc292e851e76e096ee072725bcc8b79d3f1a3b 100644
--- a/applications/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
+++ b/applications/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
@@ -90,7 +90,7 @@ ENTITY mmm_apertif_unb1_correlator IS
-- Speed test using internal PLL:
clk_clk : IN STD_LOGIC;
clk_clk_in_reset_reset_n : IN STD_LOGIC;
- altpll_1_c0_clk : OUT STD_LOGIC
+ dp_clk : OUT STD_LOGIC
);
@@ -101,12 +101,14 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
-- ( 64 * 8 / 1 )
CONSTANT c_ram_fil_coefs_addr_w : natural := ceil_log2(g_wpfb.nof_points * g_wpfb.nof_taps / g_wpfb.wb_factor);
- CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
SIGNAL i_mm_clk : STD_LOGIC := '1';
+ SIGNAL i_dp_clk : STD_LOGIC := '1';
----------------------------------------------------------------------------
-- mm_file component
@@ -220,18 +222,19 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_reset_export : out std_logic; -- export
- clk_clk : in std_logic;
- reset_reset_n : in std_logic;
- altpll_1_c0_clk : out std_logic;
- altpll_1_areset_conduit_export : in std_logic;
- altpll_1_phasedone_conduit_export : out std_logic;
- altpll_1_locked_conduit_export : out std_logic
+ clk_clk : in std_logic;
+ reset_reset_n : in std_logic;
+ altpll_1_c0_clk : out std_logic;
+ altpll_1_areset_conduit_export : in std_logic;
+ altpll_1_phasedone_conduit_export : out std_logic;
+ altpll_1_locked_conduit_export : out std_logic
);
end component qsys_apertif_unb1_correlator;
BEGIN
mm_clk <= i_mm_clk;
+ dp_clk <= i_dp_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
@@ -239,6 +242,8 @@ BEGIN
gen_mm_file_io : IF g_sim = TRUE GENERATE
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+ i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;
+
mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
@@ -380,13 +385,13 @@ BEGIN
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
- clk_clk => clk_clk,
- reset_reset_n => clk_clk_in_reset_reset_n,
- altpll_1_c0_clk => altpll_1_c0_clk,
+ clk_clk => clk_clk,
+ reset_reset_n => clk_clk_in_reset_reset_n,
+ altpll_1_c0_clk => i_dp_clk,
- altpll_1_areset_conduit_export => xo_rst,
- altpll_1_phasedone_conduit_export => OPEN,
- altpll_1_locked_conduit_export => OPEN
+ altpll_1_areset_conduit_export => xo_rst,
+ altpll_1_phasedone_conduit_export => OPEN,
+ altpll_1_locked_conduit_export => OPEN
);
END GENERATE;
diff --git a/applications/apertif_unb1_correlator/werkplan.txt b/applications/apertif_unb1_correlator/werkplan.txt
new file mode 100644
index 0000000000000000000000000000000000000000..dd984c10249bd729c765f45234b081f815fed782
--- /dev/null
+++ b/applications/apertif_unb1_correlator/werkplan.txt
@@ -0,0 +1,62 @@
+================
+WPFB+ CORRELATOR (2 weken)
+================
+1) mm_file instances in tb_apertif_unb1_correlator
+2) copy tc_correlator.py naar tc_apertif_unb1_correlator.py
+4) maak src/python/gen_block_gen_hex_files.py
+ . maak eerst 1 (deze komt bv. in channel 0) phase-shifted sinus per stream,
+ . verifieer correcte correlator output met de TC
+ . Voeg signalen toe voor zover deze in aparte bins terechtkomen
+ . 64 ge-adde sinussen zijn wss te veel.
+5) Correlatoroutput verifieren met bovenstaande sinussen
+
+=======================
+1GbE visibility offload (2 weken)
+=======================
+6) 1GbE offload toevoegen aan apertif_unb1_correlator.vhd
+7) 1GbE capture toevoegen aan TC, validatie zelfde als verificatie met correlator_src_out0.rec
+8) Draai dit image op 8 FPGAs en zorg dat de 1GbE capture TC dit ook aankan.
+
+==============================
+BGs aanpassen + reinterleavers (3 weken)
+==============================
+9) Block gens aanpassen, reinterleavers (aka 'combine' in doc) erachter:
+ . Van 24 BG's @(100MHz x 2x6b=) 1.2Gbps (totaal = 24x1.2= 28.8Gbps) naar:
+ => 8 ('telescopes) * 3 BG's @(200MHz x 4 x 2x6b=) 9.6Gbps = 8*28.8Gbps
+ . Reinterleaver stage:
+ . 1/8 vd data rate naar eigen correlator (dus 28.8Gbps).
+ . 7/8 vd data rate: eerst discarden (later naar mesh TX)
+ . Correlatoroutput: moet nog steeds kloppen.
+ . Dit design werkt nog op 1 node.
+
+NOTE: Als 24 diepere+bredere BGs niet passen hebben we fn_beamformer (evt. met block gens)
+ en 10GbE inputs nodig.
+ Andere optie is om block gen outputs te kopieren maar dan kloppen de fases niet meer.
+
+==================================
+3BGs/FPGA (ipv 24) + Mesh terminals (4 weken)
+==================================
+10) Verwijder BG 3..23.
+11) Instantieer mesh terminals + BSN aligner
+ . Reinterleaver inputs 3..23 komen nu van mesh terminal RX ipv BGs 3..23
+ . 7/8 vd reinterleaver output data gaat nu naar mesh terminal TX
+ . Correlatoroutput moet ongewijzigd blijven.
+ . Dit design werkt op 8 nodes.
+ . Dit design kan op 1 node werken als we hier al rekening houden met uitgevallen telescopes.
+
+============
+10GbE inputs (1 week) (hier moet de DDR3 transpose werken of we moeten een fn_beamformer met block gens oid hebben).
+============
+12) 10GbE toevoegen aan apertif_unb1_correlator.vhd
+ . Sluit ipv de 3 block gens de 3 10GbE input streams aan.
+ . Als we nog geen 10GbE backplane hebben moeten we wel uitgevallen telescopes supporten
+ aangezien T12..23 niet binnenkomen
+
+
+Niet meegenomen:
+-Correlatormodule cleanen,afmaken, documenteren, sluitende test bench....etc.
+ . Dit kan in de slacktijd als mijlpalen al gehaald zijn
+-Flagging
+-wat moeten we met de BSN
+
+