diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index 76c4300dd44c4889ef4d23151136242494ec00c1..445e0306eba3dccd915526c65ccfb1206280b477 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -25,7 +25,7 @@
 --   Use port a only for write in write clock domain
 --   Use port b only for read in read clock domain
 -- Remark:
---   Because the the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP,
+--   Because the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP,
 --   and unfortunately, the rwk_rw IP isn't supported either, the crk_cw IP
 --   has been created, resulting in modifications to this file.[1]
 -- Reference: