From 058bde9cffebd5da85e3e11e18ba6e940d85b22c Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 7 Aug 2017 08:49:32 +0000
Subject: [PATCH] enabled and configured analog settings
---
.../ip_arria10_e3sge3_phy_10gbase_r_24.qsys | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/ip_arria10_e3sge3_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/ip_arria10_e3sge3_phy_10gbase_r_24.qsys
index 55c41582ba..78a02af4be 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/ip_arria10_e3sge3_phy_10gbase_r_24.qsys
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/ip_arria10_e3sge3_phy_10gbase_r_24.qsys
@@ -361,11 +361,11 @@
version="16.0"
enabled="1"
autoexport="1">
- <parameter name="anlg_enable_rx_default_ovr" value="0" />
- <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_enable_rx_default_ovr" value="1" />
+ <parameter name="anlg_enable_tx_default_ovr" value="1" />
<parameter name="anlg_link" value="sr" />
- <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
- <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_8</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_8</parameter>
<parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
<parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
<parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
@@ -377,9 +377,9 @@
<parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
<parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
<parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
- <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
- <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
- <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_5" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="no_dc_gain" />
+ <parameter name="anlg_rx_one_stage_enable" value="non_s1_mode" />
<parameter name="anlg_rx_term_sel" value="r_r1" />
<parameter name="anlg_tx_analog_mode" value="user_custom" />
<parameter name="anlg_tx_compensation_en" value="enable" />
@@ -391,9 +391,9 @@
<parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
<parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
<parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
- <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r5" />
<parameter name="anlg_tx_term_sel" value="r_r1" />
- <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="30" />
<parameter name="anlg_voltage" value="1_1V" />
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
@@ -404,7 +404,7 @@
<parameter name="device" value="10AX115U4F45E3SGE3" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
- <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_analog_settings" value="1" />
<parameter name="enable_hard_reset" value="0" />
<parameter name="enable_hip" value="0" />
<parameter name="enable_parallel_loopback" value="0" />
--
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