diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt
index 796b41532404bc646db5c31d21e1991b846dea56..04b8c6aebc44e2dccad25e7241a1c08dc73f283f 100644
--- a/tools/hdltool_readme.txt
+++ b/tools/hdltool_readme.txt
@@ -709,6 +709,10 @@ o) How to avoid Quartus exit due to IP that is included at configuration, but no
    then the design that uses the io_ddr has hdl_lib_uses = io_ddr in its hdllib.cfg whereas the design that does not
    use io_ddr should in have hdl_lib_uses = io_ddr_empty, where io_ddr_empty is a revision of io_ddr with only the
    entity and an emtpy architecture.
+   If only the testbench uses some IO IP and the DUT does not (eg like for the reorder library where the tb can use
+   io_ddr + DDR3 memoery model) then it could be usefull to define an extra hdl_lib_tb_uses key next to the
+   hdl_lib_uses key. The hdl_lib_tb_uses = io_ddr is then used by Modelsim for simulation but ignored by Quartus for
+   synthesis.
    
 
 101) More ideas