diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 3bc753eb49c966c41c611588d89887d90facba1e..ccd5f167bb3fae1d1a0222002b4ea0994203d2c3 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -112,23 +112,6 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
 
   SIGNAL i_reset_n         : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 5c2f947727694406247c5cd973408505915cc092..f2e4fd38dda6cd79a13fb69f740dec777202403e 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -108,23 +108,6 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
 
   SIGNAL i_reset_n         : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index d6a07a7f6ff9e933ca4eeff5b44eaaf579dd2942..d558269b2d32b4feff3f6080740a111bfdc6c12e 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -284,23 +284,6 @@ ARCHITECTURE str OF mmm_unb2a_test IS
   SIGNAL sim_eth1g_eth1_reg_mosi                   : t_mem_mosi;
   SIGNAL i_reset_n                                 : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------