From 0332415e2b9f8e507c378e9071ccbe65d9506855 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 30 Mar 2021 19:02:47 +0200
Subject: [PATCH] unb2c fw update

---
 .../unb2c_test_10GbE/unb2c_test_10GbE.vhd     |  8 +--
 .../unb2c_test/src/vhdl/mmm_unb2c_test.vhd    | 18 ++++-
 .../unb2c_test/src/vhdl/unb2c_test.vhd        | 14 +++-
 .../unb2c_test/tb/vhdl/tb_unb2c_test.vhd      |  4 +-
 .../technology/ddr/tech_ddr_arria10_e2sg.vhd  |  2 +-
 .../alt_mem_if_jtag_master_191/hdllib.cfg     |  3 +-
 .../compile_ip.tcl                            |  3 +-
 .../hdllib.cfg                                |  6 +-
 .../compile_ip.tcl                            | 68 ++++---------------
 .../altera_emif_1910/hdllib.cfg               | 16 +++++
 .../altera_emif_arch_nf_191/compile_ip.tcl    | 22 +-----
 .../compile_ip.tcl                            |  9 +--
 .../altera_emif_cal_slave_nf_191/hdllib.cfg   |  2 +-
 .../altera_ip_col_if_191/compile_ip.tcl       |  2 +-
 .../altera_ip_col_if_191/hdllib.cfg           |  2 +-
 .../altera_jesd204_1920/compile_ip.tcl        | 41 +++++++++++
 .../altera_jesd204_1920/hdllib.cfg            | 17 +++++
 .../altera_jesd204_phy_191/compile_ip.tcl     | 40 +++++++++++
 .../altera_jesd204_phy_191/hdllib.cfg         | 17 +++++
 .../compile_ip.tcl                            | 36 ++++++++++
 .../hdllib.cfg                                |  8 +--
 .../altera_jesd204_rx_191/compile_ip.tcl      | 50 ++++++++++++++
 .../altera_jesd204_rx_191/hdllib.cfg          | 17 +++++
 .../compile_ip.tcl                            | 43 ++++++++++++
 .../altera_jesd204_rx_mlpcs_191/hdllib.cfg    | 17 +++++
 .../altera_jesd204_tx_191/compile_ip.tcl      | 45 ++++++++++++
 .../altera_jesd204_tx_191/hdllib.cfg          | 17 +++++
 .../compile_ip.tcl                            | 42 ++++++++++++
 .../altera_jesd204_tx_mlpcs_191/hdllib.cfg    | 17 +++++
 .../compile_ip.tcl                            | 35 ++++++++++
 .../hdllib.cfg                                | 16 +++++
 .../compile_ip.tcl                            |  2 +-
 .../altera_mm_interconnect_191/compile_ip.tcl |  7 --
 .../altera_mm_interconnect_191/hdllib.cfg     |  3 +-
 .../altera_reset_sequencer_191/compile_ip.tcl | 44 ++++++++++++
 .../altera_reset_sequencer_191/hdllib.cfg     | 16 +++++
 .../compile_ip.tcl                            |  2 +-
 .../ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg   |  5 +-
 .../ip_arria10_e2sg/jesd204b/hdllib.cfg       |  4 +-
 .../jesd204b/ip_arria10_e2sg_jesd204b.vhd     |  2 +-
 libraries/technology/jesd204b/hdllib.cfg      |  2 +-
 41 files changed, 597 insertions(+), 127 deletions(-)
 rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_191 => altera_emif_1910}/compile_ip.tcl (69%)
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
 rename libraries/technology/ip_arria10_e2sg/altera_libraries/{altera_emif_191 => altera_jesd204_phy_adapter_xs_191}/hdllib.cfg (50%)
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
 create mode 100644 libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg

diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index 438aaea567..e15b0e544a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -64,8 +64,8 @@ ENTITY unb2c_test_10GbE IS
     BCK_REF_CLK  : IN    STD_LOGIC; -- Clock 10GbE back lower 24 lines
 
     -- back transceivers
-    BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
-    BCK_TX       : OUT   STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
+    --BCK_RX       : IN    STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
+    --BCK_TX       : OUT   STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
 
     -- ring transceivers
     RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
@@ -131,8 +131,8 @@ BEGIN
     BCK_REF_CLK  => BCK_REF_CLK,
 
     -- back transceivers
-    BCK_RX       => BCK_RX,
-    BCK_TX       => BCK_TX,
+    --BCK_RX       => BCK_RX,
+    --BCK_TX       => BCK_TX,
 
     -- ring transceivers
     RING_0_RX    => RING_0_RX,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 2d2b17ed86..ef424554b4 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -214,7 +214,11 @@ ENTITY mmm_unb2c_test IS
     ram_diag_data_buf_bsn_mosi  : OUT t_mem_mosi;
     ram_diag_data_buf_bsn_miso  : IN  t_mem_miso;
     reg_diag_data_buf_bsn_mosi  : OUT t_mem_mosi;
-    reg_diag_data_buf_bsn_miso  : IN  t_mem_miso
+    reg_diag_data_buf_bsn_miso  : IN  t_mem_miso;
+
+    -- Scrap RAM
+    ram_scrap_mosi           : OUT t_mem_mosi;
+    ram_scrap_miso           : IN  t_mem_miso
   );
 END mmm_unb2c_test;
 
@@ -366,6 +370,8 @@ BEGIN
 
     u_mm_file_reg_heater          : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
                                                PORT MAP(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+    u_mm_file_ram_scrap           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+                                               PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
 
 
     ----------------------------------------------------------------------------
@@ -807,7 +813,15 @@ BEGIN
       reg_diag_data_buffer_bsn_write_export        => reg_diag_data_buf_bsn_mosi.wr,
       reg_diag_data_buffer_bsn_writedata_export    => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
       reg_diag_data_buffer_bsn_read_export         => reg_diag_data_buf_bsn_mosi.rd,
-      reg_diag_data_buffer_bsn_readdata_export     => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0)
+      reg_diag_data_buffer_bsn_readdata_export     => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      ram_scrap_reset_export                    => OPEN,
+      ram_scrap_clk_export                      => OPEN,
+      ram_scrap_address_export                  => ram_scrap_mosi.address(8 DOWNTO 0),
+      ram_scrap_write_export                    => ram_scrap_mosi.wr,
+      ram_scrap_writedata_export                => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_scrap_read_export                     => ram_scrap_mosi.rd,
+      ram_scrap_readdata_export                 => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
     );
   END GENERATE;
 
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 865d1ec90d..f57f7b56ef 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -236,6 +236,10 @@ ARCHITECTURE str OF unb2c_test IS
   SIGNAL reg_wdi_mosi               : t_mem_mosi;
   SIGNAL reg_wdi_miso               : t_mem_miso;
 
+  -- Scrap RAM
+  SIGNAL ram_scrap_mosi             : t_mem_mosi;
+  SIGNAL ram_scrap_miso             : t_mem_miso;
+
   -- PPSH
   SIGNAL reg_ppsh_mosi              : t_mem_mosi;
   SIGNAL reg_ppsh_miso              : t_mem_miso;
@@ -546,6 +550,10 @@ BEGIN
     udp_rx_sosi_arr          =>  eth1g_udp_rx_sosi_arr,
     udp_rx_siso_arr          =>  eth1g_udp_rx_siso_arr,
 
+    -- scrap ram
+    ram_scrap_mosi           => ram_scrap_mosi,
+    ram_scrap_miso           => ram_scrap_miso,
+
     -- FPGA pins
     -- . General
     CLK                      => CLK,
@@ -746,7 +754,11 @@ BEGIN
     ram_diag_data_buf_bsn_mosi  => ram_diag_data_buf_bsn_mosi,
     ram_diag_data_buf_bsn_miso  => ram_diag_data_buf_bsn_miso,
     reg_diag_data_buf_bsn_mosi  => reg_diag_data_buf_bsn_mosi,
-    reg_diag_data_buf_bsn_miso  => reg_diag_data_buf_bsn_miso
+    reg_diag_data_buf_bsn_miso  => reg_diag_data_buf_bsn_miso,
+
+    -- Scrap RAM
+    ram_scrap_mosi           => ram_scrap_mosi,
+    ram_scrap_miso           => ram_scrap_miso
   );
 
   -- TODO: Add support for second 1GbE port
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index c3446adbab..79b64ba28e 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -174,9 +174,7 @@ BEGIN
     g_sim           => c_sim,
     g_sim_unb_nr    => c_unb_nr,
     g_sim_node_nr   => c_node_nr,
-    g_sim_model_ddr => g_sim_model_ddr,
-    g_ddr_MB_I      => c_ddr_MB_I,
-    g_ddr_MB_II     => c_ddr_MB_II
+    g_sim_model_ddr => g_sim_model_ddr
   )
   PORT MAP (
     -- GENERAL
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
index 7f91e1c9d8..790e2e9b56 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -34,7 +34,7 @@
 --   DDR interface monitoring purposes.
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_ddr4_8g_1600_altera_emif_191;
+LIBRARY ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910;
 --LIBRARY ip_arria10_e2sg_ddr4_8g_2400_altera_emif_191;
 
 LIBRARY IEEE, technology_lib, common_lib;
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
index d9efdea2c2..6bd31de18b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
@@ -1,8 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_alt_mem_if_jtag_master_191
 hdl_library_clause_name = alt_mem_if_jtag_master_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_altera_reset_controller_191
-#ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 
 
 hdl_lib_technology = ip_arria10_e2sg
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
index e1408439bc..a6876f47ee 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
@@ -28,9 +28,8 @@
 
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
 vmap  altera_avalon_mm_bridge_191         ./work/                       
 
-#  vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/altera_avalon_mm_bridge.v"  -work altera_avalon_mm_bridge_191                                                        
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191                                                        
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
index 8a5524e48b..dd502e7d10 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194
-hdl_library_clause_name = altera_avalon_st_packets_to_bytes_194
+hdl_lib_name = ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910
+hdl_library_clause_name = altera_avalon_st_packets_to_bytes_1910
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg
@@ -10,7 +10,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_194/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
similarity index 69%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
index 297065a0ab..490f20d9a9 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
@@ -28,47 +28,16 @@
 
 #vlib ./work/         ;# Assume library work already exist
 #
-vmap  altera_emif_1910                     ./work/
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_194_dzobyri.v"                                     -work altera_emif_194
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000sim"
-#  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_194_lwknerq.v"                                     -work altera_emif_194
-
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-  vlog      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd"                                  -work altera_emif_1910
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vlog      "$IP_DIR/../altera_emif_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194_nz3mdxa.v"                                     -work altera_emif_194
 
 vmap altera_emif_arch_nf_191 ./work/
-# ddr4_4g_1600
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv"                    -work altera_emif_arch_nf_194
-
-# ddr4_4g_2000
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv"                    -work altera_emif_arch_nf_194
 
 # ddr4_8g_1600
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv"                -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv"             -work altera_emif_arch_nf_191
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd"                   -work altera_emif_arch_nf_191
+  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd"                   -work altera_emif_arch_nf_191
 
-# ddr4_8g_2400
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv"                    -work altera_emif_arch_nf_194
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv"                                                        -work altera_emif_arch_nf_191
@@ -109,21 +78,10 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane_bcm__nf5es_abphy.sv"                                                     -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/io_12_lane__nf5es_abphy.sv"                                                         -work altera_emif_arch_nf_191
 
-vmap  altera_emif_cal_slave_nf_191        ./work/
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
 
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
-
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
 
 vmap  altera_reset_controller_191         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_controller.v"                                               -work altera_reset_controller_191
   vlog      "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v"                                             -work altera_reset_controller_191
 
@@ -133,20 +91,24 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"          -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"          -work altera_mm_interconnect_191
 
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
 
 vmap  altera_avalon_onchip_memory2_1920    ./work/
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
 
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vcom         "$IP_DIR/../altera_avalon_onchip_memory2_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_avalon_onchip_memory2_194_xymx6za.vhd" -work altera_avalon_onchip_memory2_194
-
 
 vmap  altera_avalon_mm_bridge_191         ./work/
-set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vlog      "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v"  -work altera_avalon_mm_bridge_191
+
+vmap  altera_emif_cal_slave_nf_191        ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"         -work altera_emif_cal_slave_nf_191
+
+
+vmap  altera_emif_1910                     ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+  vcom      "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd"                                  -work altera_emif_1910
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
new file mode 100644
index 0000000000..96efe3d56e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_emif_1910
+hdl_library_clause_name = altera_emif_1910
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_ip_col_if_191
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
index e3828ad679..2dadb95b50 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
@@ -29,33 +29,13 @@
 #vlib ./work/         ;# Assume library work already exist                                                                                        
 
 vmap altera_emif_arch_nf_191 ./work/
-# ddr4_4g_1600
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_arch_nf_194_ud6bb7y.sv"                    -work altera_emif_arch_nf_194
-
-# ddr4_4g_2000
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_arch_nf_194_n4j75iy.sv"                    -work altera_emif_arch_nf_194
 
 # ddr4_8g_1600
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
 
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv"                -work altera_emif_arch_nf_191
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv"             -work altera_emif_arch_nf_191
-  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd"                   -work altera_emif_arch_nf_191
-
-# ddr4_8g_2400
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_top.sv"                -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i_io_aux.sv"             -work altera_emif_arch_nf_194
-#  vlog -sv  "$IP_DIR/../altera_emif_arch_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_194_e37lt4i.sv"                    -work altera_emif_arch_nf_194
+  vcom      "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq.vhd"                   -work altera_emif_arch_nf_191
 
 # common dependencies
   vlog -sv  "$IP_DIR/../altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv"                                                        -work altera_emif_arch_nf_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
index 6d30c9b1f8..e700baca19 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
@@ -30,16 +30,9 @@
 #
 
 vmap  altera_emif_cal_slave_nf_191        ./work/
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
-  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"          -work altera_emif_cal_slave_nf_191
+  vcom      "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd"          -work altera_emif_cal_slave_nf_191
 
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vlog      "$IP_DIR/../altera_emif_cal_slave_nf_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_cal_slave_nf_194_efslyyq.v"           -work altera_emif_cal_slave_nf_194
 
                                                       
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
index a26e9d4fef..f8b87b4e79 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_altera_emif_cal_slave_nf_191
 hdl_library_clause_name = altera_emif_cal_slave_nf_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
index ae1a4365be..39a9046c4b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
@@ -34,4 +34,4 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
 
 vmap  altera_ip_col_if_191 ./work/
                                               
-  vlog  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.v"  -work altera_ip_col_if_191                 
+  vcom  "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.vhd"  -work altera_ip_col_if_191                 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
index 2a1b8d1562..6b3ebc9cb7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_altera_ip_col_if_191
 hdl_library_clause_name = altera_ip_col_if_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_mm_interconnect_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
new file mode 100644
index 0000000000..7ca664bc19
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
@@ -0,0 +1,41 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_1920           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+  vcom "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_1920_humwsma.vhd"   -work altera_jesd204_1920
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_1920_xrjkkdy.vhd"   -work altera_jesd204_1920 
+
+
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
new file mode 100644
index 0000000000..7e2c7b6c99
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_1920
+hdl_library_clause_name = altera_jesd204_1920
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jesd204_phy_191
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
new file mode 100644
index 0000000000..9fd2ce4a80
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_phy_191           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+  vcom         "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_phy_191_qtzjdri.vhd"   -work altera_jesd204_phy_191
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+  vcom         "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_phy_191_iu47x7q.vhd"   -work altera_jesd204_phy_191
+
+
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
new file mode 100644
index 0000000000..7a3f243be3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_phy_191
+hdl_library_clause_name = altera_jesd204_phy_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_jesd204_rx_191 ip_arria10_e2sg_altera_jesd204_tx_191 ip_arria10_e2sg_altera_jesd204_phy_adapter_xs_191
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
new file mode 100644
index 0000000000..24d021d788
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_phy_adapter_xs_191           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+
+  vlog         "$IP_DIR/../altera_jesd204_phy_adapter_xs_191/sim/mentor/altera_jesd204_phy_adapter_xs.v"          -work altera_jesd204_phy_adapter_xs_191  
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
similarity index 50%
rename from libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg
rename to libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
index d45106b1c9..019f8fa154 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
@@ -1,17 +1,17 @@
-hdl_lib_name = ip_arria10_e2sg_altera_emif_191
-hdl_library_clause_name = altera_emif_191
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_phy_adapter_xs_191
+hdl_library_clause_name = altera_jesd204_phy_adapter_xs_191
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = 
-#ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
     
 test_bench_files = 
 
+
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_191/compile_ip.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
 
 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
new file mode 100644
index 0000000000..fda853dc06
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_rx_191           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v"                -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_csr.v"                 -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_ctl.v"                 -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_descrambler.v"         -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_char_val.v"        -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_cs.v"              -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_data_store.v"      -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_ecc_dec.v"         -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_ecc_enc.v"         -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_ecc_fifo.v"        -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_frame_align.v"     -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_fs_char_replace.v" -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_lane_align.v"      -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll.v"                 -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_dll_wo_ecc_fifo.v"     -work altera_jesd204_rx_191   
+  vlog         "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_regmap.v"              -work altera_jesd204_rx_191   
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
new file mode 100644
index 0000000000..f1cbfa6e1b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_rx_191
+hdl_library_clause_name = altera_jesd204_rx_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191 ip_arria10_e2sg_altera_jesd204_rx_mlpcs_191 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
new file mode 100644
index 0000000000..7c98851c07
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_rx_mlpcs_191           ./work/
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_dec.v"          -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_mlpcs.v"           -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_pcs.v"             -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_wa.v"                 -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_wys_lut.v"            -work altera_jesd204_rx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_xn_8b10b_dec.v"       -work altera_jesd204_rx_mlpcs_191  
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
new file mode 100644
index 0000000000..1a66738823
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_rx_mlpcs_191
+hdl_library_clause_name = altera_jesd204_rx_mlpcs_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
new file mode 100644
index 0000000000..2dedec0639
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_tx_191           ./work/
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+
+
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_base.v"          -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_csr.v"           -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_ctl.v"           -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_dll.v"           -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_regmap_opt.v"    -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_regmap.v"        -work altera_jesd204_tx_191 
+  vlog         "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_scrambler.v"     -work altera_jesd204_tx_191 
+
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
new file mode 100644
index 0000000000..175fe361da
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_tx_191
+hdl_library_clause_name = altera_jesd204_tx_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_191 ip_arria10_e2sg_altera_jesd204_tx_mlpcs_191 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
new file mode 100644
index 0000000000..060df7feea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
@@ -0,0 +1,42 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+vmap  altera_jesd204_tx_mlpcs_191           ./work/
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_enc.v"          -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_pcfifo.v"             -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_tx_mlpcs.v"           -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_tx_pcs.v"             -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_wys_lut.v"            -work altera_jesd204_tx_mlpcs_191  
+  vlog         "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_xn_8b10b_enc.v"       -work altera_jesd204_tx_mlpcs_191  
+ 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
new file mode 100644
index 0000000000..27f636b09b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altera_jesd204_tx_mlpcs_191
+hdl_library_clause_name = altera_jesd204_tx_mlpcs_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
new file mode 100644
index 0000000000..23e9f50cad
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+vmap  altera_merlin_master_translator_191 ./work/
+        
+  vlog -sv  "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_master_translator_191_g7h47bq.sv"   -work altera_merlin_master_translator_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
new file mode 100644
index 0000000000..96a1f18f72
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_merlin_master_translator_191
+hdl_library_clause_name = altera_merlin_master_translator_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
index e9fb6118fa..2e7e9ed643 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
@@ -33,5 +33,5 @@ set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
  
 vmap  altera_merlin_slave_translator_191  ./work/
                                                       
-  vcom  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
+  vlog -sv  "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv"  -work altera_merlin_slave_translator_191 
 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
index 2a7891c90c..d4aa7747c3 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
@@ -30,16 +30,9 @@
 #
                                                       
 vmap  altera_mm_interconnect_191          ./work/
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_1600/sim"
-#  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_1600_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
-
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_4g_2000/sim"
-#  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_4g_2000_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd"             -work altera_mm_interconnect_191
   vcom         "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd"             -work altera_mm_interconnect_191
 
-#set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
-#  vcom         "$IP_DIR/../altera_mm_interconnect_194/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_mm_interconnect_194_7km4trq.vhd"             -work altera_mm_interconnect_194
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
index c8ba8fa026..2ddb7be056 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
@@ -1,8 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_altera_mm_interconnect_191
 hdl_library_clause_name = altera_mm_interconnect_191
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = 
-#ip_arria10_e2sg_altera_merlin_master_translator_191 ip_arria10_e2sg_altera_merlin_slave_translator_191
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_merlin_master_translator_191 
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
new file mode 100644
index 0000000000..20acf8a3b7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
@@ -0,0 +1,44 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist      
+#
+
+vmap  altera_reset_sequencer_191         ./work/
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
+ 
+
+  vlog     "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_controller.v"                -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_av_csr.sv"         -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_deglitch_main.sv"  -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_deglitch.sv"       -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_dlycntr.sv"        -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_main.sv"           -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer_seq.sv"            -work altera_reset_sequencer_191 
+  vlog -sv "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_sequencer.sv"                -work altera_reset_sequencer_191 
+  vlog     "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_synchronizer.v"              -work altera_reset_sequencer_191 
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
new file mode 100644
index 0000000000..74ffede0c2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e2sg_altera_reset_sequencer_191
+hdl_library_clause_name = altera_reset_sequencer_191
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+    
+test_bench_files = 
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
index 51a960a06b..fcb493e25d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
@@ -50,6 +50,6 @@ vmap  altera_xcvr_atx_pll_a10_191         ./work/
   vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/a10_xcvr_atx_pll.sv"                                                 -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
   vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_embedded_debug.sv"                                      -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
   vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_avmm_csr.sv"                                            -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
-  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
+  vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_191_fbvyoua.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
   vlog -sv   "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv"                                 -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191        
                                                                                                
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
index a43ad8edbb..eb13535a2f 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -1,10 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_ddr4_8g_1600
 hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191
-#ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 
-#ip_arria10_e2sg_altera_emif_1910 
-#ip_arria10_e2sg_altera_merlin_master_translator_191 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_emif_cal_slave_nf_191 ip_arria10_e2sg_altera_avalon_onchip_memory2_1920 ip_arria10_e2sg_altera_mm_interconnect_191 ip_arria10_e2sg_altera_reset_controller_191 ip_arria10_e2sg_altera_emif_arch_nf_191 ip_arria10_e2sg_altera_avalon_mm_bridge_191 ip_arria10_e2sg_altera_merlin_slave_translator_191 ip_arria10_e2sg_altera_avalon_sc_fifo_191 ip_arria10_e2sg_altera_ip_col_if_191 ip_arria10_e2sg_altera_jtag_dc_streaming_191 ip_arria10_e2sg_alt_mem_if_jtag_master_191 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_1910 ip_arria10_e2sg_altera_avalon_packets_to_master_1910 ip_arria10_e2sg_channel_adapter_191 ip_arria10_e2sg_timing_adapter_191 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_1910 ip_arria10_e2sg_altera_emif_1910 ip_arria10_e2sg_altera_merlin_master_translator_191 
 
 hdl_lib_technology = ip_arria10_e2sg
 
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
index 56e3d78598..fd070965ac 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
@@ -1,9 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_jesd204b
 hdl_library_clause_name = ip_arria10_e2sg_jesd204b_lib
 hdl_lib_uses_synth = technology tech_pll common dp
-hdl_lib_uses_sim = 
-#ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz_altera_iopll_1930
-#ip_arria10_e2sg_altera_jesd204_180 ip_arria10_e2sg_altera_xcvr_reset_control_180 ip_arria10_e2sg_altera_iopll_180 ip_arria10_e2sg_altera_reset_sequencer_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_1930 ip_arria10_e2sg_altera_jesd204_1920 ip_arria10_e2sg_altera_reset_sequencer_191 ip_arria10_e2sg_altera_xcvr_reset_control_191
 hdl_lib_technology = ip_arria10_e2sg 
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 64187db7ae..2b2c0162a4 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -59,7 +59,7 @@ ENTITY ip_arria10_e2sg_jesd204b IS
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
     mm_rst                : IN  STD_LOGIC;
-    jesd204b_disable_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+    jesd204b_disable_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
          
     jesd204b_mosi         : IN  t_mem_mosi;         --  mm control
     jesd204b_miso         : OUT t_mem_miso; 
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 3defdbf578..b7427c05f0 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -16,7 +16,7 @@ synth_files =
 
 test_bench_files =
 #    tb_tech_jesd204b_pkg.vhd
-    tb_tech_jesd204b.vhd
+#    tb_tech_jesd204b.vhd
 #    tb_tb_tech_jesd204b.vhd
 
 regression_test_vhdl = 
-- 
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