From 0306fe4b019643bb42afabff39d2e4fdd9555445 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 12 Jun 2015 14:20:20 +0000
Subject: [PATCH] Added g_sim_model. Renamed instances.
---
libraries/io/ddr/src/vhdl/mms_io_ddr.vhd | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
index 3a03de15ff..e8f1e68cdb 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
@@ -31,6 +31,7 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY mms_io_ddr IS
GENERIC(
+ g_sim_model : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_cross_domain_dvr_ctlr : BOOLEAN := TRUE;
@@ -83,7 +84,8 @@ ENTITY mms_io_ddr IS
rd_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);
rd_sosi : OUT t_dp_sosi;
rd_siso : IN t_dp_siso;
-
+
+ -- DDR3 pass on termination control from master to slave controller
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
@@ -111,7 +113,7 @@ ARCHITECTURE str OF mms_io_ddr IS
BEGIN
-- Combine the reg map of io_ddr and io_ddr_reg
- u_mm_mux : ENTITY common_lib.common_mem_mux
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => 2,
g_mult_addr_w => ceil_log2(8)
@@ -123,8 +125,9 @@ BEGIN
miso_arr => reg_io_ddr_miso_arr
);
- u_ddr_mem_ctrl : ENTITY work.io_ddr
- GENERIC MAP(
+ u_io_ddr : ENTITY work.io_ddr
+ GENERIC MAP (
+ g_sim_model => g_sim_model,
g_technology => g_technology,
g_tech_ddr => g_tech_ddr,
g_cross_domain_dvr_ctlr => FALSE,
@@ -192,7 +195,8 @@ BEGIN
phy4_ou => phy4_ou
);
- u_ddr_reg : ENTITY work.io_ddr_reg
+ -- MM register map for DDR controller write and read access control via MM
+ u_io_ddr_reg : ENTITY work.io_ddr_reg
PORT MAP(
-- Clocks and reset
mm_rst => mm_rst,
--
GitLab