diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 68a0d39356e85a8b6bc91bbb5c3f9f75b41bb340..05ec67b6c8576091105eaecb67bdb58ff53018ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -110,6 +110,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_mm_clk_period : TIME := 10 ns; -- 100 MHz internal mm_clk
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
@@ -572,8 +573,7 @@ BEGIN
-- . write
v_offset := bset * c_mm_span_reg_bf_scale;
mmf_mm_bus_wr(c_mm_file_reg_bf_scale, v_offset + 0, c_exp_beamlet_scale, tb_clk);
- proc_common_wait_some_cycles(tb_clk, c_cross_clock_domain_latency);
- proc_common_wait_some_cycles(ext_clk, c_cross_clock_domain_latency);
+ proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period);
-- . readback
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index c7cca711f2f77c247415e164bbe5e6f86734710a..1526b134c410682e23adef74492b4f2295c05efb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -110,11 +110,11 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_mm_clk_period : TIME := 10 ns; -- 100 MHz internal mm_clk
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
@@ -554,8 +554,7 @@ BEGIN
-- . write
v_offset := bset * c_mm_span_reg_bf_scale;
mmf_mm_bus_wr(c_mm_file_reg_bf_scale, v_offset + 0, c_exp_beamlet_scale, tb_clk);
- proc_common_wait_some_cycles(tb_clk, c_cross_clock_domain_latency);
- proc_common_wait_some_cycles(ext_clk, c_cross_clock_domain_latency);
+ proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period);
-- . readback
mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 505bdf3885dfaca54168fb75366cd85742ff30fb..b17b13aef8437a9152c22b11f74974f0626eb186 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -39,6 +39,11 @@ USE work.common_pkg.ALL;
PACKAGE tb_common_pkg IS
+ -- Constants
+ CONSTANT c_common_cross_clock_domain_latency : NATURAL := 20;
+
+
+ -- Wait for some time or until
PROCEDURE proc_common_wait_some_cycles(SIGNAL clk : IN STD_LOGIC;
c_nof_cycles : IN NATURAL);
@@ -135,6 +140,21 @@ PACKAGE tb_common_pkg IS
SIGNAL out_valid : OUT STD_LOGIC);
+ -- Wait for clock domain crossing latency, e.g. for MM readback after MM write
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL st_clk : IN STD_LOGIC;
+ CONSTANT c_nof_cycles : IN NATURAL);
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL st_clk : IN STD_LOGIC);
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(CONSTANT c_mm_clk_period : IN TIME;
+ CONSTANT c_st_clk_period : IN TIME;
+ CONSTANT c_nof_cycles : IN NATURAL);
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(CONSTANT c_mm_clk_period : IN TIME;
+ CONSTANT c_st_clk_period : IN TIME);
+
-- Generate a single active, inactive pulse
PROCEDURE proc_common_gen_pulse(CONSTANT c_active : IN NATURAL; -- pulse active for nof clk
CONSTANT c_period : IN NATURAL; -- pulse period for nof clk
@@ -623,6 +643,40 @@ PACKAGE BODY tb_common_pkg IS
END IF;
END proc_common_ready_latency;
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Wait for clock domain crossing latency, e.g. for MM readback after MM write
+ ------------------------------------------------------------------------------
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL st_clk : IN STD_LOGIC;
+ CONSTANT c_nof_cycles : IN NATURAL) IS
+ BEGIN
+ proc_common_wait_some_cycles(mm_clk, c_nof_cycles);
+ proc_common_wait_some_cycles(st_clk, c_nof_cycles);
+ END proc_common_wait_cross_clock_domain_latency;
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL st_clk : IN STD_LOGIC) IS
+ BEGIN
+ proc_common_wait_some_cycles(mm_clk, c_common_cross_clock_domain_latency);
+ proc_common_wait_some_cycles(st_clk, c_common_cross_clock_domain_latency);
+ END proc_common_wait_cross_clock_domain_latency;
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(CONSTANT c_mm_clk_period : IN TIME;
+ CONSTANT c_st_clk_period : IN TIME;
+ CONSTANT c_nof_cycles : IN NATURAL) IS
+ BEGIN
+ WAIT FOR c_nof_cycles * c_mm_clk_period;
+ WAIT FOR c_nof_cycles * c_st_clk_period;
+ END proc_common_wait_cross_clock_domain_latency;
+
+ PROCEDURE proc_common_wait_cross_clock_domain_latency(CONSTANT c_mm_clk_period : IN TIME;
+ CONSTANT c_st_clk_period : IN TIME) IS
+ BEGIN
+ WAIT FOR c_common_cross_clock_domain_latency * c_mm_clk_period;
+ WAIT FOR c_common_cross_clock_domain_latency * c_st_clk_period;
+ END proc_common_wait_cross_clock_domain_latency;
+
------------------------------------------------------------------------------
-- PROCEDURE: Generate a single active, inactive pulse
------------------------------------------------------------------------------