diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index e98d884217eae21a8b170dc9a47891e1986e762d..a7851a6999cb1cf5c0c0e87010b927f1d14bd63d 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -48,7 +48,7 @@ ENTITY apertif_unb1_fn_beamformer IS
     g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_use_MB_I    : NATURAL := 0;
+    g_use_MB_I    : NATURAL := 0; --FIXME - Now we have g_use_MB_I, c_use_phy and c_use_transpose to select DDR3....?
     g_bf          : t_c_bf  := c_bf;
     g_use_bf      : BOOLEAN := TRUE
   );
@@ -105,9 +105,9 @@ ENTITY apertif_unb1_fn_beamformer IS
     SI_FN_RSTN             : OUT   STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
                                                     -- So we need to assign a '1' to it.
     -- SO-DIMM Memory Bank I
-    MB_I_IN                : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
-    MB_I_IO                : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); 
-    MB_I_OU                : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) 
+    MB_I_IN                : IN    t_tech_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
+    MB_I_IO                : INOUT t_tech_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); 
+    MB_I_OU                : OUT   t_tech_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) 
   );
 END apertif_unb1_fn_beamformer;
 
@@ -533,7 +533,6 @@ BEGIN
   ---------------------------------------------------------------------------- 
     u_transpose: ENTITY reorder_lib.reorder_transpose
     GENERIC MAP(
-      g_sim              => g_sim,   
       g_nof_streams      => g_bf.nof_bf_units,      
       g_in_dat_w         => c_offload_dat_w, 
       g_frame_size_in    => g_bf.nof_weights,               
@@ -575,7 +574,6 @@ BEGIN
     
     u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
     GENERIC MAP( 
-      g_sim                    => g_sim,
       g_technology             => c_tech_select_default, 
       g_tech_ddr               => c_tech_ddr,      
       g_cross_domain_dvr_ctlr  => FALSE, 
@@ -623,9 +621,9 @@ BEGIN
       rd_sosi       => from_mem_sosi,
       rd_siso       => from_mem_siso,     
     
-      phy_in        => MB_I_IN(0),
-      phy_io        => MB_I_IO(0),  
-      phy_ou        => MB_I_OU(0)
+      phy3_in       => MB_I_IN(0),
+      phy3_io       => MB_I_IO(0),  
+      phy3_ou       => MB_I_OU(0)
     );
   END GENERATE;
   
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer.vhd
index 6966eab18193acdab1ebeed984178505c5d9bd3a..1ff3182eceff4c3d52a9e4e1c836e9a5c18ce1fc 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer.vhd
@@ -78,9 +78,9 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_beamformer IS
   SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
   
   -- Signals to interface with the DDR3 memory model.
-  SIGNAL phy_in              : t_tech_ddr_phy_in_arr(0 DOWNTO 0);
-  SIGNAL phy_io              : t_tech_ddr_phy_io_arr(0 DOWNTO 0);
-  SIGNAL phy_ou              : t_tech_ddr_phy_ou_arr(0 DOWNTO 0);   
+  SIGNAL phy_in              : t_tech_ddr3_phy_in_arr(0 DOWNTO 0);
+  SIGNAL phy_io              : t_tech_ddr3_phy_io_arr(0 DOWNTO 0);
+  SIGNAL phy_ou              : t_tech_ddr3_phy_ou_arr(0 DOWNTO 0);   
   
   SIGNAL ras_n               : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL cas_n               : STD_LOGIC_VECTOR(0 DOWNTO 0);