diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
similarity index 76%
rename from boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/hdllib.cfg
rename to boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index aed8ff14576537ca054fe5b14db33f1fc0d24455..50e443058bfa9d244a3a69e030716d2787dadde0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -1,10 +1,9 @@
-hdl_lib_name = unb2_test_ddr
-hdl_library_clause_name = unb2_test_ddr_lib
+hdl_lib_name = unb2_test_ddr_MB_I
+hdl_library_clause_name = unb2_test_ddr_MB_I_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddio
- ip_arria10_tse_sgmii_gx
+hdl_lib_excludes = ip_arria10_tse_sgmii_gx
ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
@@ -15,10 +14,10 @@ hdl_lib_excludes = ip_arria10_ddio
ip_arria10_ddr4_8g_2400
synth_files =
- unb2_test_ddr.vhd
+ unb2_test_ddr_MB_I.vhd
test_bench_files =
- tb_unb2_test_ddr.vhd
+ tb_unb2_test_ddr_MB_I.vhd
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -36,10 +35,10 @@ quartus_qsf_files =
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
- quartus/unb2_test_ddr_pins.tcl
+ quartus/unb2_test_ddr_MB_I_pins.tcl
quartus_sdc_files =
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/quartus/unb2_test_ddr_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
similarity index 100%
rename from boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/quartus/unb2_test_ddr_pins.tcl
rename to boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
similarity index 89%
rename from boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd
rename to boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index 05a40ec8120536374d763bb7caf874878de5b98e..ddca8eb30727b0d9211b31285046072ec4876248 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -26,15 +26,15 @@ LIBRARY IEEE, unb2_test_lib;
USE IEEE.std_logic_1164.ALL;
-ENTITY tb_unb2_test_ddr IS
-END tb_unb2_test_ddr;
+ENTITY tb_unb2_test_ddr_MB_I IS
+END tb_unb2_test_ddr_MB_I;
-ARCHITECTURE tb OF tb_unb2_test_ddr IS
+ARCHITECTURE tb OF tb_unb2_test_ddr_MB_I IS
BEGIN
u_tb_unb2_test : ENTITY unb2_test_lib.tb_unb2_test
GENERIC MAP (
- g_design_name => "unb2_test_ddr",
+ g_design_name => "unb2_test_ddr_MB_I",
g_sim_model_ddr => FALSE
);
END tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ec7834994ec3de03c8f2b748e4a893731e10e95d
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+
+ENTITY unb2_test_ddr_MB_I IS
+ GENERIC (
+ g_design_name : STRING := "unb2_test_ddr_MB_I";
+ g_design_note : STRING := "Test design with ddr4";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN : IN t_tech_ddr4_phy_in;
+ MB_I_IO : INOUT t_tech_ddr4_phy_io;
+ MB_I_OU : OUT t_tech_ddr4_phy_ou;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2_test_ddr_MB_I;
+
+
+ARCHITECTURE str OF unb2_test_ddr_MB_I IS
+
+BEGIN
+ u_revision : ENTITY unb2_test_lib.unb2_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..61a5e209d190dba451cc297a08e576849cbd7783
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -0,0 +1,45 @@
+hdl_lib_name = unb2_test_ddr_MB_II
+hdl_library_clause_name = unb2_test_ddr_MB_II_lib
+hdl_lib_uses_synth = common mm technology unb2_board unb2_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_tse_sgmii_gx
+ ip_arria10_pll_xgmii_mac_clocks
+ ip_arria10_mac_10g
+ ip_arria10_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_24
+ ip_arria10_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_24
+ ip_arria10_ddr4_8g_2400
+
+synth_files =
+ unb2_test_ddr_MB_II.vhd
+
+test_bench_files =
+ tb_unb2_test_ddr_MB_II.vhd
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+
+modelsim_copy_files =
+ ../../src/hex hex
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_unb2_test.qsys .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+
+quartus_tcl_files =
+ quartus/unb2_test_ddr_MB_II_pins.tcl
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..83eeedee0b6b9e9797b11764a286b93f6182fbd4
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c1d47fe2b25b7eac2e4a88b80e32569ade928f89
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+
+LIBRARY IEEE, unb2_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2_test_ddr_MB_II IS
+END tb_unb2_test_ddr_MB_II;
+
+
+ARCHITECTURE tb OF tb_unb2_test_ddr_MB_II IS
+BEGIN
+ u_tb_unb2_test : ENTITY unb2_test_lib.tb_unb2_test
+ GENERIC MAP (
+ g_design_name => "unb2_test_ddr_MB_II",
+ g_sim_model_ddr => FALSE
+ );
+END tb;
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..06f5b01fb069f39e6f2911545f6c8a39b74e42cf
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+
+ENTITY unb2_test_ddr_MB_II IS
+ GENERIC (
+ g_design_name : STRING := "unb2_test_ddr_MB_II";
+ g_design_note : STRING := "Test design with ddr4";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+ -- DDR reference clocks
+ MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN : IN t_tech_ddr4_phy_in;
+ MB_II_IO : INOUT t_tech_ddr4_phy_io;
+ MB_II_OU : OUT t_tech_ddr4_phy_ou;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2_test_ddr_MB_II;
+
+
+ARCHITECTURE str OF unb2_test_ddr_MB_II IS
+
+BEGIN
+ u_revision : ENTITY unb2_test_lib.unb2_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..50bdf0d744212110daff5d71e872d0b45c96d9e9
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -0,0 +1,45 @@
+hdl_lib_name = unb2_test_ddr_MB_I_II
+hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib
+hdl_lib_uses_synth = common mm technology unb2_board unb2_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_tse_sgmii_gx
+ ip_arria10_pll_xgmii_mac_clocks
+ ip_arria10_mac_10g
+ ip_arria10_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_24
+ ip_arria10_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_24
+ ip_arria10_ddr4_8g_2400
+
+synth_files =
+ unb2_test_ddr_MB_I_II.vhd
+
+test_bench_files =
+ tb_unb2_test_ddr_MB_I_II.vhd
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+
+modelsim_copy_files =
+ ../../src/hex hex
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_unb2_test.qsys .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+
+quartus_tcl_files =
+ quartus/unb2_test_ddr_MB_I_II_pins.tcl
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..83eeedee0b6b9e9797b11764a286b93f6182fbd4
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d709afea4afaf0247eae8fa7d1aa7cfb07da2a4
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+
+LIBRARY IEEE, unb2_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2_test_ddr_MB_I_II IS
+END tb_unb2_test_ddr_MB_I_II;
+
+
+ARCHITECTURE tb OF tb_unb2_test_ddr_MB_I_II IS
+BEGIN
+ u_tb_unb2_test : ENTITY unb2_test_lib.tb_unb2_test
+ GENERIC MAP (
+ g_design_name => "unb2_test_ddr_MB_I_II",
+ g_sim_model_ddr => FALSE
+ );
+END tb;
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
similarity index 93%
rename from boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd
rename to boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index a7ea8386df61437665b2ba4c4bb7354b884dc5ce..7430f0b809aed5e09f74d1dd9129f652bb91aaa0 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/unb2_test_ddr.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -29,9 +29,9 @@ USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY unb2_test_ddr IS
+ENTITY unb2_test_ddr_MB_I_II IS
GENERIC (
- g_design_name : STRING := "unb2_test_ddr";
+ g_design_name : STRING := "unb2_test_ddr_MB_I_II";
g_design_note : STRING := "Test design with ddr4";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -75,13 +75,13 @@ ENTITY unb2_test_ddr IS
MB_II_IN : IN t_tech_ddr4_phy_in;
MB_II_IO : INOUT t_tech_ddr4_phy_io;
MB_II_OU : OUT t_tech_ddr4_phy_ou;
-
+
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
-END unb2_test_ddr;
+END unb2_test_ddr_MB_I_II;
-ARCHITECTURE str OF unb2_test_ddr IS
+ARCHITECTURE str OF unb2_test_ddr_MB_I_II IS
BEGIN
u_revision : ENTITY unb2_test_lib.unb2_test
@@ -130,7 +130,7 @@ BEGIN
MB_II_IN => MB_II_IN,
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU,
-
+
QSFP_LED => QSFP_LED
);
END str;