diff --git a/libraries/base/dp/src/vhdl/dp_repack_dev.vhd b/libraries/base/dp/src/vhdl/dp_repack_dev.vhd
index e75ec1a07fa79788b236eb6ce590ee56c30437d7..f79e29edcf95dbd15e208c2deaaff996948e2503 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_dev.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_dev.vhd
@@ -24,68 +24,47 @@
--
-- Block diagram:
--
--- A) Functional
--- g_in_nof_words=4 g_out_nof_words=2
---
--- r_in r_out
--- ___ r_out_ready ___ <-- src_in.ready
--- | |<---------------------| |--> src_out.data
+-- A) Functional
+-- The drawing shows g_in_nof_words=4 and g_out_nof_words=2 as example:
+--
+-- dp_repack_in dp_repack_out
+-- ___ ___
+-- | | pack_sosi | |--> src_out
-- | 3 |--------------------->| 1 |
--- | | load | |
--- | 2 | | |
--- | | ^ | | ^
--- | 1 | |valid | 0 | |shift
--- | | |flush | | |
--- | 0 | | | | |
--- snk_in.data -->|___| |___|
--- snk_out.ready <--
+-- | | | |
+-- | 2 | ^ | | ^
+-- | | |valid | | |shift
+-- | 1 | |flush | 0 | |
+-- | | | | | |
+-- | 0 | | |
+-- snk_in -->|___| pack_siso |___|
+-- snk_out.ready <-- <--------------------- <-- src_in.ready
-- snk_out.xon <------------------------------------- src_in.xon
--
--
--- B) No src_in flow control, but can issue local comb_snk_out flow control
---
--- /----------------------------\
--- | nxt_r r |
--- | /------\ . . |
--- \-->| |----> p_reg -----*--> src_out
--- | | . .
--- snk_in -------->| | . .
--- comb_snk_out <---|p_comb| . .
--- . \------/ . .
--- . . .
--- RL=1 RL=1 RL=2
---
--- C) Add src_in flow control using dp_pipeline
---
--- /----------------------------\
--- | nxt_r r |
--- | /------\ . . |
--- \-->| |----> p_reg -----/ ____
--- | | | |dp |
--- snk_in -------->| | \------------------|pipe|---> src_out
--- /--|p_comb| . |line|
--- | \------/ . | |
--- comb_snk_out | . | |
--- v . | |
--- /-\ . pipe_snk_out | |
--- snk_out <----| |<-----------------------------| |<--- src_in
--- . \-/ . |____| .
--- . . .
--- RL=1 RL=1 RL=1
+-- B) Flow control
--
--- Default flow control:
--- snk_out.ready <= comb_snk_out.ready AND pipe_snk_out.ready -- when function maintains or increases the data valid rate
--- snk_out.ready <= '0' WHEN comb_snk_out.ready='0' ELSE pipe_snk_out.ready; -- when function increases the data valid rate (equivalent boolean condition)
---
--- Advanced flow control for maximum throughput:
--- snk_out.ready <= '1' WHEN comb_snk_out.ready='1' ELSE pipe_snk_out.ready; -- when function reduces the data valid rate
---
--- The default flow control condition is that both the local function and
--- the downstream function have to be ready. The default flow control
--- condition works in any case, but if the local function reduces the valid
--- data output rate, then the throughput can be increased by using the
--- advanced flow control condition. The local function can reduce the valid
--- data rate by packing data into larger words or by removing data.
+-- RL=1 RL=1 RL=1
+-- . . .
+-- . /-----------------------------------------\
+-- . | . _____ . |
+-- . | /------\ nxt_r | | r |
+-- . \-->| |---*-------*----->|p_reg|-----*---> src_out
+-- . | | | | |_____|
+-- snk_in -------->|p_comb|<--|-------|--------------*-------- src_in
+-- | | | | |
+-- | | | v |
+-- | | | /-------\ |
+-- | | | |p_flow | |
+-- \------/ | \-------/ |
+-- | | |
+-- nxt_r.hold_out.valid | | |
+-- v | |
+-- /| |r_snk_out |
+-- |1|------/ |
+-- snk_out <------------------| | |
+-- |0|---------------------/
+-- \|
--
-- Description:
-- The dp_repack_dev repacks g_in_nof_words of width g_in_dat_w into
@@ -94,80 +73,58 @@
-- . bypass
-- If g_in_nof_words=g_out_nof_words then snk_in is simply passed on directly
-- to src_out via wires.
+-- If g_in_nof_words=1 then the dp_repack_in stage is bypassed to safe logic.
+-- If g_out_nof_words=1 then the dp_repack_out stage is bypassed to safe logic.
+-- Both the dp_repack_in and dp_repack_out stage do work correctly when
+-- nof_words=1. They then merely add a transparant pipeline delay. It is
+-- important that they also work for nof_words=1 because that gives confidence
+-- that their implementation structure is ok.
--
-- . g_in_nof_words and input block size
-- The input block size in words is indicated by snk_in.sop and snk_in.eop.
-- Each subsection of g_in_nof_words is packed into g_out_nof_words. The
-- input block size does not have to be a multiple of g_in_nof_words. When
--- the snk_in.eop
--- occurs the last repack is initiated without need for input data padding.
---
--- . c_out_buf_dat_w >= c_in_buf_dat_w
--- To avoid loss of input data the c_out_buf_dat_w must be >= c_in_buf_dat_w.
--- If c_out_buf_dat_w > c_in_buf_dat_w then there will be unused LSbits in
--- the output data.
+-- the snk_in.eop occurs the last repack is initiated without need for input
+-- data padding. If the block length is an integer multiple of
+-- g_in_nof_words then the dp_repack_dev introduces no gaps between blocks.
+-- If the block length is a fractional multiple of g_in_nof_words then there
+-- will be a gap after the block due to that the dp_repack_in needs to
+-- shift up the last subsection for the 'missing' input words.
--
--- Remark:
+-- Remarks:
-- . Originally reused from LOFAR rad_repack.vhd and rad_repack(rtl).vhd. This
-- dp_repack_dev still uses the shift in input register in and the shift out
-- output register, but no longer the intermediate buffer register.
--- Using shift in and shift out probably eases timing closure compared to
--- using a demultiplexer to put the input data in the input register and a
--- multiplexer to get the data directly from the output register. For the
--- demultiplexer / multiplexer it would be possible to only use one internal
--- register.
+-- Using shift in and shift out may ease timing closure because the routing
+-- is more local compared to using a demultiplexer to put the input data in
+-- the input register and a multiplexer to get the data directly from the
+-- output register. For the demultiplexer / multiplexer it would be possible
+-- to only use one internal register.
+-- Using shift up is sufficient, the shift down option is not needed. With
+-- shift up the data is input a [0] and output the high index.
-- Instead of requiring an snk_in.valid duty cycle this dp_repack_dev uses
-- snk_out.ready flow control and can handle src_in.ready flow control.
+-- . The case of g_in_dat_w*g_in_nof_words /= g_out_dat_w*g_out_nof_words
+-- needs to be supported for both < and also > to be able to use a pack and
+-- a unpack instance.
--
-- Design steps:
--- * Day 1
--- . Studied original dp_repack with shift in stage, buffer stage and shift
--- out stage. Concluded that:
--- - the buffer stage is not needed
--- - using shift in and shift out stages is better than using one stage
--- with input demux and output mux.
--- - using shift up is sufficient, the shift down optionvis not needed.
--- With shift up the data is input a [0] and output the high index.
--- . Design improvements:
--- - Treat the input stage and output stage as two separate components,
--- each introducing 1 cycle pipeline and each with its own set of
--- registers (r_in and r_out). Describe them using the Gaisler two
--- process method.
--- - Support c_out_buf_dat_w > c_in_buf_dat_w
--- . Started the new dp_repack with streaming interfaces and flow control
--- in a new file dp_repack_dev.vhd. Copied tb_dp_repack.vhd to
--- tb_dp_repack_dev.vhd.
--- . Treat the input stage and output stage as two separate components,
--- each introducing 1 cycle pipeline and each with its own registers
--- (r_in and r_out). Describe them using the Gaisler two process method.
--- . Distinghuised generate cases for g_in_nof_words=1 or >1 and similar
--- for g_out_nof_words=1 or >1. Started with implementing >1 first for
--- r_in and then for r_out.
--- . Defined flow control between r_in and r_out using r_in.load (which acts
--- as sosi.valid) and r_out_ready (which acts as siso.ready with RL=1).
--- * Day 2
--- . Added g_no_unpack to the tb_dp_repack.vhd to be able to verify one DUT
--- instead of DUT and inverse opertion DUT together. Being able to verify
--- a single DUT and using e_active eases the checking that no clock
--- cycles are lost unnecessarily.
--- . Verified that the gap between input blocks can be 0, it does not have
--- to be >= g_out_nof_words.
--- . Added r_out.eos to avoid loosing a clk cycle after loading a new
--- subsection.
--- . Corrected src_out.empty
--- . Corrected src_out.data.
--- . Added block diagram drawing in the description.
--- . Added multi testbench tb_tb_repack_dev.vhd
--- . Committed all.
---
--- * Day 3
--- . Panic and distress : I can not get it to work for blocks with multiple
--- subsections and also not for flow control. Need to rethink.
--- . Split dp_repack_dev into separate dp_repack_in input stage component
--- and dp_repack_out output stage component for more clarity.
---
--- * Day 4
-
+-- * In total the development took 5 days. On day 3 I was in distress because
+-- I could not get it to work so I needed to rethink. After changing to the
+-- new flow control scheme that uses nxt_r the design was gradually improved
+-- by getting the dp_repack_dev instances in tb_tb_dp_repack_dev to work one
+-- by one. First only for e_active stimuli and then also for e_random and
+-- e_pulse. This step by step approach makes that the bugs appear one by one
+-- instead of all together.
+-- * The development used the tb_dp_repack_dev testbench that does a pack and
+-- an unpack to be able to verify the data. The g_no_unpack and
+-- c_enable_repack_in / c_enable_repack_out parameters in the tb were useful
+-- to be able to isolate a component for debugging.
+-- * First the cases with g_in_nof_words=1 and g_out_nof_words were made to
+-- work for different g_pkt_len. Then the empty functionality was added.
+-- Then apply external flow control using c_dp_flow_control_enum_arr in
+-- the tb_tb_dp_repack_dev was verified resulting in small corrections.
+-- Then verified g_in_dat_w*g_in_nof_words /= g_out_dat_w*g_out_nof_words.
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
@@ -207,23 +164,23 @@ ARCHITECTURE rtl OF dp_repack_in IS
hold_out : t_dp_sosi; -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
flush : STD_LOGIC; -- shift when snk_in.valid or flush in case the last subsection has < g_in_nof_words
dat_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- actual nof bits in subsection
- pack_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- count nof bits in subsection
+ pack_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- count nof bits in subsection
END RECORD;
-
+
SIGNAL data_vec : STD_LOGIC_VECTOR(c_in_buf_dat_w-1 DOWNTO 0);
-
+
SIGNAL r_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
-
+
-- Debug signals
SIGNAL snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL src_out_data : STD_LOGIC_VECTOR(c_in_buf_dat_w-1 DOWNTO 0);
-
+
SIGNAL dbg_g_in_dat_w : NATURAL := g_in_dat_w;
SIGNAL dbg_in_nof_words : NATURAL := g_in_nof_words;
SIGNAL dbg_in_symbol_w : NATURAL := g_in_symbol_w;
-
+
BEGIN
p_comb : PROCESS(rst, r, snk_in, data_vec, src_in)
@@ -240,25 +197,25 @@ BEGIN
--------------------------------------------------------------------------
-- Function
IF r.hold_out.valid='0' THEN
-
+
-- Clear hold_out for new output valid (= new subsection)
IF r.src_out.valid='1' THEN
v.hold_out := c_dp_sosi_rst;
END IF;
-
- -- Capture the snk_in block info that is valid at sop and eop
+
+ -- Capture the snk_in block info that is valid at sop and eop
IF snk_in.sop='1' THEN
v.hold_out.sop := '1';
v.hold_out.sync := snk_in.sync;
v.src_out.bsn := snk_in.bsn;
v.src_out.channel := snk_in.channel;
- END IF;
+ END IF;
IF snk_in.eop='1' THEN
v.hold_out.eop := '1';
v.hold_out.empty := SHIFT_UVEC(snk_in.empty, -c_in_empty_lo); -- use snk_in.empty as offset for src_out.empty in nof bits
v.src_out.err := snk_in.err;
END IF;
-
+
-- Capture the data per subsection in a block
IF snk_in.valid='1' OR r.flush='1' THEN
-- shift in during block
@@ -268,11 +225,11 @@ BEGIN
ELSE
v.dat_arr(0) := snk_in.data(g_in_dat_w-1 DOWNTO 0); -- shift in valid data
END IF;
-
+
-- pack subsection
IF r.pack_bit_cnt<c_in_buf_dat_w-g_in_dat_w THEN
v.pack_bit_cnt := r.pack_bit_cnt + g_in_dat_w;
-
+
-- early end of pack subsection
IF snk_in.eop='1' THEN
v.flush := '1'; -- enable flush in case eop occurs before end of pack subsection
@@ -285,7 +242,7 @@ BEGIN
IF r.flush='0' THEN
v.dat_bit_cnt := c_in_buf_dat_w; -- set default subsection pack_bit_cnt
END IF;
-
+
-- output input stage into output stage when ready, else hold_out.valid to signal pending output
IF src_in.ready='1' THEN
v.src_out.valid := '1';
@@ -295,28 +252,28 @@ BEGIN
ELSE
v.hold_out.valid := '1';
END IF;
- END IF;
+ END IF;
END IF;
-
+
-- pass on the v.dat_arr as data vector
v.src_out.data := RESIZE_DP_DATA(data_vec);
-
- -- pass on dat_bit_cnt via DP empty field
+
+ -- pass on dat_bit_cnt via DP empty field
v.src_out.empty := INCR_UVEC(v.hold_out.empty, c_in_buf_dat_w - v.dat_bit_cnt);
-
+
ELSE
-- pending output
IF src_in.ready='1' THEN
v.src_out.valid := '1';
- v.src_out.sync := v.hold_out.sync;
- v.src_out.sop := v.hold_out.sop;
- v.src_out.eop := v.hold_out.eop;
+ v.src_out.sync := r.hold_out.sync;
+ v.src_out.sop := r.hold_out.sop;
+ v.src_out.eop := r.hold_out.eop;
v.hold_out.valid := '0';
END IF;
END IF;
-
+
------------------------------------------------------------------------
- -- Reset and nxt_r
+ -- Reset and nxt_r
IF rst = '1' THEN
v.src_out := c_dp_sosi_rst;
v.hold_out := c_dp_sosi_rst;
@@ -327,11 +284,11 @@ BEGIN
nxt_r <= v;
END PROCESS;
-
+
--------------------------------------------------------------------------
- -- p_in_reg
+ -- p_reg
r <= nxt_r WHEN rising_edge(clk);
-
+
--------------------------------------------------------------------------
-- Wires
p_data_vec : PROCESS(nxt_r)
@@ -340,30 +297,30 @@ BEGIN
data_vec((I+1)*g_in_dat_w-1 DOWNTO I*g_in_dat_w) <= nxt_r.dat_arr(I);
END LOOP;
END PROCESS;
-
+
--------------------------------------------------------------------------
-- Wired output
snk_in_data <= snk_in.data(g_in_dat_w-1 DOWNTO 0);
-
- src_out <= r.src_out;
+
+ src_out <= r.src_out;
src_out_data <= r.src_out.data(c_in_buf_dat_w-1 DOWNTO 0);
-
+
--------------------------------------------------------------------------
-- Flow control
-
+
-- local function flow control
- p_flow_control : PROCESS(nxt_r)
+ p_flow : PROCESS(nxt_r)
BEGIN
- r_snk_out <= c_dp_siso_rdy;
+ r_snk_out <= c_dp_siso_rdy;
IF nxt_r.flush='1' THEN
r_snk_out.ready <= '0'; -- input shift in stage function is always ready except when flushing
END IF;
END PROCESS;
-
+
-- combined local and remote src_in flow control
snk_out.ready <= r_snk_out.ready WHEN nxt_r.hold_out.valid='0' ELSE src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
-
+
END rtl;
@@ -407,26 +364,26 @@ ARCHITECTURE rtl OF dp_repack_out IS
hold_out : t_dp_sosi; -- hold src_out valid and sync/sop/eop until src_in.ready
shift : STD_LOGIC; -- shift out the dat_arr
dat_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- actual nof bits in subsection
- pack_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- count nof bits in subsection
- empty_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- empty nof bits in subsection
- eos : STD_LOGIC; -- end of subsection
+ pack_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- count nof bits in subsection
+ empty_bit_cnt : NATURAL RANGE 0 TO c_bit_cnt_max; -- empty nof bits in subsection
+ eos : STD_LOGIC; -- end of subsection
END RECORD;
-
+
SIGNAL data_vec : STD_LOGIC_VECTOR(c_out_buf_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
-
+
SIGNAL r_snk_out : t_dp_siso := c_dp_siso_rdy;
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
-
+
-- Debug signals
SIGNAL snk_in_data : STD_LOGIC_VECTOR(g_in_buf_dat_w-1 DOWNTO 0);
SIGNAL src_out_data : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
-
+
SIGNAL dbg_g_in_buf_dat_w : NATURAL := g_in_buf_dat_w;
SIGNAL dbg_g_out_dat_w : NATURAL := g_out_dat_w;
SIGNAL dbg_out_nof_words : NATURAL := g_out_nof_words;
SIGNAL dbg_out_symbol_w : NATURAL := g_out_symbol_w;
-
+
BEGIN
p_comb : PROCESS(rst, snk_in, r, data_vec, src_in)
@@ -439,12 +396,11 @@ BEGIN
v.src_out.valid := '0';
v.src_out.sop := '0';
v.src_out.eop := '0';
- v.eos := '0';
-
+
------------------------------------------------------------------------
-- Function
IF r.hold_out.valid='0' THEN
-
+
-- Clear hold_out for new output valid
IF r.src_out.valid='1' THEN
v.hold_out.sync := '0';
@@ -453,55 +409,55 @@ BEGIN
IF r.src_out.eop='1' THEN
v.hold_out.eop := '0';
END IF;
-
- -- Capture the snk_in block info that is valid at sop and eop
+
+ -- Capture the snk_in block info that is valid at sop and eop
IF snk_in.sop='1' THEN
v.hold_out.sop := '1';
v.hold_out.sync := snk_in.sync;
v.src_out.bsn := snk_in.bsn;
v.src_out.channel := snk_in.channel;
- END IF;
+ END IF;
IF snk_in.eop='1' THEN
v.hold_out.eop := '1'; -- local function will calculate src_out.empty based on snk_in.empty
v.src_out.err := snk_in.err;
END IF;
-
+
IF r.shift='1' THEN
-- shift out rest of subsection
v.hold_out.valid := '1';
-
+
v.dat_arr(g_out_nof_words-1 DOWNTO 1) := r.dat_arr(g_out_nof_words-2 DOWNTO 0); -- shift up from low to high and shift out at high index
v.dat_arr(0) := (OTHERS=>'0'); -- shift in data=0
-
+
v.pack_bit_cnt := r.pack_bit_cnt - g_out_dat_w;
-
+
-- end of pack subsection
IF v.pack_bit_cnt<=r.empty_bit_cnt THEN
v.eos := '1'; -- end of subsection, so ready for new snk_in
v.shift := '0'; -- stop shifting
END IF;
-
+
ELSIF snk_in.valid='1' THEN
-- start of pack subsection
v.hold_out.valid := '1';
-
+
FOR I IN 0 TO g_out_nof_words-1 LOOP
v.dat_arr(I) := data_vec((I+1)*g_out_dat_w-1 DOWNTO I*g_out_dat_w);
END LOOP;
-
+
v.dat_bit_cnt := g_in_buf_dat_w - TO_UINT(snk_in.empty); -- pass on dat_bit_cnt via DP empty field
v.pack_bit_cnt := c_out_buf_dat_w - g_out_dat_w;
v.empty_bit_cnt := c_out_buf_dat_w - v.dat_bit_cnt;
v.eos := '0';
v.shift := '1';
-
+
-- end of pack subsection
IF v.pack_bit_cnt<=v.empty_bit_cnt THEN
v.eos := '1'; -- end of subsection, so ready for new snk_in
v.shift := '0';
END IF;
END IF;
-
+
-- fill in local empty if this is the last subsection of a block
IF v.eos='1' THEN
IF v.hold_out.eop='1' THEN
@@ -509,7 +465,7 @@ BEGIN
v.src_out.empty := SHIFT_UVEC(v.src_out.empty, c_out_empty_lo); -- in nof symbols
END IF;
END IF;
-
+
-- pass on the v.dat_arr as data vector
v.src_out.data := RESIZE_DP_DATA(v.dat_arr(g_out_nof_words-1));
@@ -525,20 +481,20 @@ BEGIN
v.hold_out.valid := '0';
END IF;
END IF;
-
+
ELSE
-- pending output
IF src_in.ready='1' THEN
v.src_out.valid := '1';
- v.src_out.sync := v.hold_out.sync;
- v.src_out.sop := v.hold_out.sop;
- IF v.eos='1' THEN
- v.src_out.eop := v.hold_out.eop; -- output eop at end of subsection
+ v.src_out.sync := r.hold_out.sync;
+ v.src_out.sop := r.hold_out.sop;
+ IF r.eos='1' THEN
+ v.src_out.eop := r.hold_out.eop; -- output eop at end of subsection
END IF;
v.hold_out.valid := '0';
END IF;
END IF;
-
+
------------------------------------------------------------------------
-- Reset and nxt_r
IF rst = '1' THEN
@@ -553,38 +509,38 @@ BEGIN
nxt_r <= v;
END PROCESS;
-
+
--------------------------------------------------------------------------
- -- p_out_reg
+ -- p_reg
r <= nxt_r WHEN rising_edge(clk);
--------------------------------------------------------------------------
-- Wires
data_vec(c_out_buf_dat_w-1 DOWNTO c_out_buf_dat_lo) <= snk_in.data(g_in_buf_dat_w-1 DOWNTO 0);
-
+
--------------------------------------------------------------------------
-- Wired output
snk_in_data <= snk_in.data(g_in_buf_dat_w-1 DOWNTO 0);
-
- src_out <= r.src_out;
+
+ src_out <= r.src_out;
src_out_data <= r.src_out.data(g_out_dat_w-1 DOWNTO 0);
-
+
--------------------------------------------------------------------------
-- Flow control
-
+
-- local function flow control
- p_flow_control : PROCESS(nxt_r)
+ p_flow : PROCESS(nxt_r)
BEGIN
- r_snk_out <= c_dp_siso_rdy;
+ r_snk_out <= c_dp_siso_rdy;
IF nxt_r.shift='1' AND nxt_r.eos='0' THEN
r_snk_out.ready <= '0'; -- output shift out stage function is only ready when it is not shifting or at the end of the subsection
END IF;
END PROCESS;
-
+
-- combined local and remote src_in flow control
snk_out.ready <= r_snk_out.ready WHEN nxt_r.hold_out.valid='0' ELSE src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
-
+
END rtl;
@@ -621,34 +577,34 @@ END dp_repack_dev;
ARCHITECTURE str OF dp_repack_dev IS
CONSTANT c_in_buf_dat_w : NATURAL := g_in_dat_w * g_in_nof_words;
-
+
SIGNAL snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL i_snk_out : t_dp_siso;
-
+
SIGNAL pack_siso : t_dp_siso;
SIGNAL pack_sosi : t_dp_sosi;
SIGNAL pack_sosi_data : STD_LOGIC_VECTOR(c_in_buf_dat_w-1 DOWNTO 0);
-
+
SIGNAL i_src_out : t_dp_sosi;
SIGNAL src_out_data : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
-
+
SIGNAL snk_out_ready_reg : STD_LOGIC_VECTOR(0 TO c_dp_stream_rl);
SIGNAL pack_ready_reg : STD_LOGIC_VECTOR(0 TO c_dp_stream_rl);
-
+
BEGIN
snk_out <= i_snk_out;
src_out <= i_src_out;
-
+
snk_in_data <= snk_in.data(g_in_dat_w-1 DOWNTO 0);
pack_sosi_data <= pack_sosi.data(c_in_buf_dat_w-1 DOWNTO 0);
src_out_data <= i_src_out.data(g_out_dat_w-1 DOWNTO 0);
-
+
no_dp_repack_in : IF g_enable_repack_in=FALSE GENERATE
i_snk_out <= pack_siso;
pack_sosi <= snk_in;
END GENERATE;
-
+
gen_dp_repack_in : IF g_enable_repack_in=TRUE GENERATE
u_dp_repack_in : ENTITY work.dp_repack_in
GENERIC MAP (
@@ -659,20 +615,20 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
-
+
snk_out => i_snk_out,
snk_in => snk_in,
-
+
src_in => pack_siso,
src_out => pack_sosi
);
END GENERATE;
-
+
no_dp_repack_out : IF g_enable_repack_out=FALSE GENERATE
pack_siso <= src_in;
i_src_out <= pack_sosi;
END GENERATE;
-
+
gen_dp_repack_out : IF g_enable_repack_out=TRUE GENERATE
u_dp_repack_out : ENTITY work.dp_repack_out
GENERIC MAP (
@@ -684,17 +640,17 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
-
+
snk_out => pack_siso,
snk_in => pack_sosi,
-
+
src_in => src_in,
src_out => i_src_out
);
END GENERATE;
-
+
-- Simulation only: internal stream RL verification
- --proc_dp_siso_alert(clk, snk_in, i_snk_out, snk_out_ready_reg);
- --proc_dp_siso_alert(clk, pack_sosi, pack_siso, pack_ready_reg);
-
+ proc_dp_siso_alert(clk, snk_in, i_snk_out, snk_out_ready_reg);
+ proc_dp_siso_alert(clk, pack_sosi, pack_siso, pack_ready_reg);
+
END str;