From 01c068b902b0063725d10c570fddc85ac8585c46 Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Tue, 15 Mar 2022 16:41:12 +0100
Subject: [PATCH] Ready for review.
---
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 12 +++---
.../src/vhdl/ddrctrl_address_counter.vhd | 6 +--
.../ddrctrl/src/vhdl/ddrctrl_pack.vhd | 6 +--
.../ddrctrl/src/vhdl/ddrctrl_repack.vhd | 42 +++++++++----------
.../ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd | 2 +-
5 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 5bef72ca9a..838e8f5c89 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -76,14 +76,14 @@ BEGIN
u_pack : ENTITY work.ddrctrl_pack
GENERIC MAP(
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
+ g_nof_streams => g_nof_streams, -- number of input streams
+ g_data_w => g_data_w -- data with of input data vectors
)
PORT MAP(
in_sosi_arr => in_sosi_arr, -- input data
- out_data => data -- output data
+ out_data => data -- output data
);
@@ -91,13 +91,13 @@ BEGIN
u_repack : ENTITY work.ddrctrl_repack
GENERIC MAP(
g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w -- the input data with
+ g_in_data_w => c_out_data_w -- the input data with
)
PORT MAP(
- clk => clk,
+ clk => clk,
rst => rst,
in_data => data, -- input data
- out_of => a_of, -- amount of internal overflow
+ out_of => a_of, -- amount of internal overflow
out_sosi => sosi -- output data
);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
index ef295d5d3a..25d43e825a 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
@@ -92,9 +92,9 @@ BEGIN
BEGIN
v := q_reg;
- v.out_mosi.wrdata(c_data_w-1 DOWNTO 0) := v.s_in_sosi.data(c_data_w - 1 DOWNTO 0);
- v.out_mosi.wr := v.s_in_sosi.valid;
- v.out_of := v.s_in_of;
+ v.out_mosi.wrdata(c_data_w-1 DOWNTO 0) := q_reg.s_in_sosi.data(c_data_w - 1 DOWNTO 0);
+ v.out_mosi.wr := q_reg.s_in_sosi.valid;
+ v.out_of := q_reg.s_in_of;
v.s_in_sosi := in_sosi;
v.s_in_of := in_of;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
index 1fde708fef..5d7630a29b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
@@ -34,14 +34,14 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY ddrctrl_pack IS
GENERIC (
- g_nof_streams : POSITIVE := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
);
PORT (
in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input data
- out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
+ out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
);
END ddrctrl_pack;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
index 57f3afd205..e650494588 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
@@ -37,13 +37,13 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddrctrl_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_in_data_w : NATURAL := 168 -- the input data with
+ g_in_data_w : NATURAL := 168 -- the input data with
);
PORT (
- clk : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
- in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
- out_of : OUT NATURAL := 0; -- amount of internal overflow this output
+ in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
+ out_of : OUT NATURAL := 0; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
);
END ddrctrl_repack;
@@ -53,7 +53,7 @@ ARCHITECTURE rtl OF ddrctrl_repack IS
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
- CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
+ CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
-- type for statemachine
TYPE t_state IS (OVERFLOW_OUTPUT, FILL_VECTOR, FIRST_OUTPUT, RESET);
@@ -89,27 +89,27 @@ BEGIN
v := q_reg;
CASE q_reg.state IS
- WHEN FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
+ WHEN FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.a_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.a_of) := in_data(g_in_data_w-1 DOWNTO 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count+1; -- increase the counter of c_v with 1
- v.out_sosi.valid := '0'; -- out_sosi.valid 0
+ v.c_v_count := q_reg.c_v_count+1; -- increase the counter of c_v with 1
+ v.out_sosi.valid := '0'; -- out_sosi.valid 0
- WHEN FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
+ WHEN FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.a_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.a_of) := in_data(g_in_data_w-1 DOWNTO 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.data(c_out_data_w - 1 DOWNTO 0) := v.c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.out_data_count := q_reg.out_data_count+1; -- increase the counter of out_sosi.data with 1
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
+ v.out_sosi.data(c_out_data_w - 1 DOWNTO 0) := v.c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_data_count := q_reg.out_data_count+1; -- increase the counter of out_sosi.data with 1
WHEN OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
- v.a_of := q_reg.a_of + (g_in_data_w*(q_reg.c_v_count+1)) - (c_out_data_w*(q_reg.out_data_count+1)); -- check how much overflow there is and safe it in a_of
- v.out_of := v.a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector
- v.c_v(k_c_v_w-1 DOWNTO k_c_v_w-(g_in_data_w-v.a_of)) := in_data(g_in_data_w-v.a_of-1 DOWNTO 0); -- fill the rest of c_v untill the end
- v.c_v(v.a_of-1 DOWNTO 0) := in_data(g_in_data_w-1 DOWNTO g_in_data_w-v.a_of); -- fill the start of c_v untill the a_of
- v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.c_v_count := 0; -- reset counter
- v.out_data_count := 0; -- reset counter
+ v.a_of := q_reg.a_of + (g_in_data_w*(q_reg.c_v_count+1)) - (c_out_data_w*(q_reg.out_data_count+1)); -- check how much overflow there is and safe it in a_of
+ v.out_of := v.a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector
+ v.c_v(k_c_v_w-1 DOWNTO k_c_v_w-(g_in_data_w-v.a_of)) := in_data(g_in_data_w-v.a_of-1 DOWNTO 0); -- fill the rest of c_v untill the end
+ v.c_v(v.a_of-1 DOWNTO 0) := in_data(g_in_data_w-1 DOWNTO g_in_data_w-v.a_of); -- fill the start of c_v untill the a_of
+ v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.c_v_count := 0; -- reset counter
+ v.out_data_count := 0; -- reset counter
WHEN RESET =>
v := c_t_reg_init;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
index b458fc3ca7..395cb88961 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
@@ -36,7 +36,7 @@ ENTITY tb_ddrctrl_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
- g_in_data_w : NATURAL := 168; -- input data vector with
+ g_in_data_w : NATURAL := 168; -- input data vector with
g_sim_lengt : NATURAL := 52 -- amount of times there wil be input data for ddrctrl_repack in this testbench
);
--
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