diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index adbc1c3ab85a7caf739dd553b60ad66d90048c5d..f401444b33ad8c7adb696d3271f735dd80bfa337 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -112,23 +112,6 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
 
   SIGNAL i_reset_n         : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index c7fb668951b72fbe03eda899fddfc198bc67f1b8..315fbdfe35f47511380b1b31eb25d79a2c15e318 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -108,23 +108,6 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
 
   SIGNAL i_reset_n         : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 0c98297f43c3393ab7831cd84aa62a91c2c40dbf..b52e100aba21c1beab54647df08be4b1029a01e4 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -284,23 +284,6 @@ ARCHITECTURE str OF mmm_unb2b_test IS
   SIGNAL sim_eth1g_eth1_reg_mosi                   : t_mem_mosi;
   SIGNAL i_reset_n                                 : STD_LOGIC;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
 BEGIN
 
   ----------------------------------------------------------------------------