ip_arria10_e1sg_ddr4_8g_2400

2019.10.10.13:20:50 Datasheet
Overview

All Components
   ddr4_inst altera_emif 18.0
   ddr4_inst_arch altera_emif_arch_nf 18.0
   ddr4_inst_cal_slave_component altera_emif_cal_slave_nf 18.0
   ddr4_inst_cal_slave_component_ioaux_master_bridge altera_avalon_mm_bridge 18.0
   ddr4_inst_cal_slave_component_ioaux_soft_ram altera_avalon_onchip_memory2 18.0
Memory Map
ddr4_inst_arch
 cal_master_avalon_master
  ddr4_inst
ctrl_amm_avalon_slave_0 
  ddr4_inst_arch
ctrl_amm_avalon_slave_0 
  ddr4_inst_cal_slave_component
avl 
  ddr4_inst_cal_slave_component_ioaux_soft_ram
s1  0x00000000

ddr4_inst

altera_emif v18.0


Parameters

PROTOCOL_ENUM PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI E1 (Production) - change device under 'View'->'Device Family'
PHY_RZQ 240
PLL_ADD_EXTRA_CLKS false
PHY_DDR4_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_USER_PING_PONG_EN false
PHY_DDR4_MEM_CLK_FREQ_MHZ 1200.0
PHY_DDR4_DEFAULT_REF_CLK_FREQ false
PHY_DDR4_USER_REF_CLK_FREQ_MHZ 25.0
PHY_DDR4_REF_CLK_JITTER_PS 10.0
PHY_DDR4_RATE_ENUM RATE_QUARTER
PHY_DDR4_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_DDR4_IO_VOLTAGE 1.2
PHY_DDR4_DEFAULT_IO true
PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_DDR4_AC_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_CK_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_DATA_IO_STD_ENUM IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM OUT_OCT_34_CAL
PHY_DDR4_DATA_IN_MODE_ENUM IN_OCT_120_CAL
PHY_DDR4_STARTING_VREFIN 61.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM IO_STD_LVDS
PHY_DDR4_RZQ_IO_STD_ENUM IO_STD_CMOS_12
MEM_DDR4_FORMAT_ENUM MEM_FORMAT_SODIMM
MEM_DDR4_DQ_WIDTH 72
MEM_DDR4_DQ_PER_DQS 8
MEM_DDR4_NUM_OF_DIMMS 1
MEM_DDR4_RANKS_PER_DIMM 2
MEM_DDR4_CK_WIDTH 2
MEM_DDR4_ROW_ADDR_WIDTH 15
MEM_DDR4_COL_ADDR_WIDTH 10
MEM_DDR4_BANK_ADDR_WIDTH 2
MEM_DDR4_BANK_GROUP_WIDTH 2
MEM_DDR4_DM_EN true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM DDR4_ALERT_N_PLACEMENT_DATA_LANES
MEM_DDR4_ALERT_N_DQS_GROUP 0
MEM_DDR4_MIRROR_ADDRESSING_EN false
MEM_DDR4_HIDE_ADV_MR_SETTINGS true
MEM_DDR4_TCL 18
MEM_DDR4_RTT_NOM_ENUM DDR4_RTT_NOM_ODT_DISABLED
MEM_DDR4_ATCL_ENUM DDR4_ATCL_DISABLED
MEM_DDR4_DRV_STR_ENUM DDR4_DRV_STR_RZQ_7
MEM_DDR4_RTT_WR_ENUM DDR4_RTT_WR_ODT_DISABLED
MEM_DDR4_WTCL 18
MEM_DDR4_RTT_PARK DDR4_RTT_PARK_ODT_DISABLED
MEM_DDR4_WRITE_DBI false
MEM_DDR4_READ_DBI false
MEM_DDR4_DEFAULT_VREFOUT false
MEM_DDR4_USER_VREFDQ_TRAINING_VALUE 60.0
MEM_DDR4_USER_VREFDQ_TRAINING_RANGE DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_DQS_WIDTH 9
MEM_DDR4_CS_PER_DIMM 2
MEM_DDR4_USE_DEFAULT_ODT true
MEM_DDR4_R_ODTN_1X1 Rank 0
MEM_DDR4_R_ODT0_1X1 off
MEM_DDR4_W_ODTN_1X1 Rank 0
MEM_DDR4_W_ODT0_1X1 on
MEM_DDR4_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 off,on
MEM_DDR4_R_ODT1_2X2 on,off
MEM_DDR4_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 on,on
MEM_DDR4_W_ODT1_2X2 on,on
MEM_DDR4_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 off,off,on,on
MEM_DDR4_R_ODT1_4X2 on,on,off,off
MEM_DDR4_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 off,off,on,on
MEM_DDR4_W_ODT1_4X2 on,on,off,off
MEM_DDR4_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 off,off,off,off
MEM_DDR4_R_ODT1_4X4 off,off,on,on
MEM_DDR4_R_ODT2_4X4 off,off,off,off
MEM_DDR4_R_ODT3_4X4 on,on,off,off
MEM_DDR4_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 on,on,off,off
MEM_DDR4_W_ODT1_4X4 off,off,on,on
MEM_DDR4_W_ODT2_4X4 off,off,on,on
MEM_DDR4_W_ODT3_4X4 on,on,off,off
MEM_DDR4_R_DERIVED_ODTN Rank 0,Rank 1,-,-
MEM_DDR4_R_DERIVED_ODT0 (Drive) RZQ/7 (34 Ohm),ODT Disabled,-,-
MEM_DDR4_R_DERIVED_ODT1 ODT Disabled,(Drive) RZQ/7 (34 Ohm),-,-
MEM_DDR4_R_DERIVED_ODT2 -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 -,-,-,-
MEM_DDR4_W_DERIVED_ODTN Rank 0,Rank 1,-,-
MEM_DDR4_W_DERIVED_ODT0 (Park) Park ODT off,ODT Disabled,-,-
MEM_DDR4_W_DERIVED_ODT1 ODT Disabled,(Park) Park ODT off,-,-
MEM_DDR4_W_DERIVED_ODT2 -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 -,-,-,-
MEM_DDR4_SPEEDBIN_ENUM DDR4_SPEEDBIN_2400
MEM_DDR4_TIS_PS 60
MEM_DDR4_TIS_AC_MV 100
MEM_DDR4_TIH_PS 95
MEM_DDR4_TIH_DC_MV 75
MEM_DDR4_TDIVW_TOTAL_UI 0.2
MEM_DDR4_VDIVW_TOTAL 136
MEM_DDR4_TDQSQ_UI 0.16
MEM_DDR4_TQH_UI 0.76
MEM_DDR4_TDVWP_UI 0.72
MEM_DDR4_TDQSCK_PS 180
MEM_DDR4_TDQSS_CYC 0.27
MEM_DDR4_TQSH_CYC 0.38
MEM_DDR4_TDSH_CYC 0.18
MEM_DDR4_TDSS_CYC 0.18
MEM_DDR4_TWLS_CYC 0.13
MEM_DDR4_TWLH_CYC 0.13
MEM_DDR4_TINIT_US 500
MEM_DDR4_TMRD_CK_CYC 8
MEM_DDR4_TRAS_NS 33.0
MEM_DDR4_TRCD_NS 14.06
MEM_DDR4_TRP_NS 14.06
MEM_DDR4_TREFI_US 7.8
MEM_DDR4_TRFC_NS 160.0
MEM_DDR4_TWR_NS 15.0
MEM_DDR4_TWTR_L_CYC 4
MEM_DDR4_TWTR_S_CYC 2
MEM_DDR4_TFAW_NS 25.0
MEM_DDR4_TRRD_L_CYC 5
MEM_DDR4_TRRD_S_CYC 4
MEM_DDR4_TCCD_L_CYC 5
MEM_DDR4_TCCD_S_CYC 4
BOARD_DDR4_USE_DEFAULT_ISI_VALUES true
BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED true
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED false
BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR4_DQS_TO_CK_SKEW_NS 0.02
BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_DDR4_SKEW_BETWEEN_DQS_NS 0.02
BOARD_DDR4_AC_TO_CK_SKEW_NS 0.0
BOARD_DDR4_MAX_CK_DELAY_NS 0.6
BOARD_DDR4_MAX_DQS_DELAY_NS 0.6
BOARD_DDR4_AC_ISI_NS 0.22
BOARD_DDR4_RCLK_ISI_NS 0.22
BOARD_DDR4_WCLK_ISI_NS 0.078
BOARD_DDR4_RDATA_ISI_NS 0.155
BOARD_DDR4_WDATA_ISI_NS 0.16
CTRL_DDR4_AUTO_POWER_DOWN_EN false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR4_USER_REFRESH_EN false
CTRL_DDR4_USER_PRIORITY_EN false
CTRL_DDR4_AUTO_PRECHARGE_EN false
CTRL_DDR4_ADDR_ORDER_ENUM DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN false
CTRL_DDR4_ECC_AUTO_CORRECTION_EN false
CTRL_DDR4_REORDER_EN true
CTRL_DDR4_STARVE_LIMIT 63
CTRL_DDR4_MMR_EN false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
DIAG_SOFT_NIOS_MODE SOFT_NIOS_MODE_DISABLED
DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE false
DIAG_EXPORT_PLL_LOCKED false
SHORT_QSYS_INTERFACE_NAMES false
DIAG_DDR4_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER true
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR4_EX_DESIGN_ISSP_EN true
DIAG_DDR4_INTERFACE_ID 0
DIAG_DDR4_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR4_SIM_VERBOSE true
DIAG_DDR4_USE_TG_AVL_2 false
DIAG_DDR4_ABSTRACT_PHY false
DIAG_DDR4_BYPASS_DEFAULT_PATTERN false
DIAG_DDR4_BYPASS_USER_STAGE true
DIAG_DDR4_BYPASS_REPEAT_STAGE true
DIAG_DDR4_BYPASS_STRESS_STAGE true
DIAG_DDR4_SKIP_CA_LEVEL false
DIAG_DDR4_SKIP_CA_DESKEW false
DIAG_DDR4_SKIP_VREF_CAL true
EX_DESIGN_GUI_DDR4_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR4_GEN_SIM true
EX_DESIGN_GUI_DDR4_GEN_SYNTH true
EX_DESIGN_GUI_DDR4_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_arch

altera_emif_arch_nf v18.0
ddr4_inst_arch cal_slave_clk_clock_source   ddr4_inst_cal_slave_component_clk_bridge
  in_clk
cal_slave_reset_n_reset_source   ddr4_inst_cal_slave_component_rst_bridge
  in_reset
cal_master_avalon_master   ddr4_inst_cal_slave_component_ioaux_master_bridge
  s0


Parameters

SILICON_REV 20nm5
IS_HPS false
IS_VID false
USER_CLK_RATIO 4
C2P_P2C_CLK_RATIO 4
PHY_HMC_CLK_RATIO 2
DIAG_ABSTRACT_PHY_WLAT 9
DIAG_ABSTRACT_PHY_RLAT 18
DIAG_CPA_OUT_1_EN false
DIAG_USE_CPA_LOCK false
DQS_BUS_MODE_ENUM DQS_BUS_MODE_X8_X9
AC_PIN_MAP_SCHEME use_0_1_2_3_lane
NUM_OF_HMC_PORTS 1
HMC_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_MM
HMC_CTRL_DIMM_TYPE sodimm
REGISTER_AFI true
SEQ_SYNTH_CPU_CLK_DIVIDE 2
SEQ_SYNTH_CAL_CLK_DIVIDE 8
SEQ_SIM_CPU_CLK_DIVIDE 1
SEQ_SIM_CAL_CLK_DIVIDE 32
SEQ_SYNTH_OSC_FREQ_MHZ 450
SEQ_SIM_OSC_FREQ_MHZ 2390
NUM_OF_RTL_TILES 4
PRI_RDATA_TILE_INDEX 0
PRI_RDATA_LANE_INDEX 0
PRI_WDATA_TILE_INDEX 0
PRI_WDATA_LANE_INDEX 0
PRI_AC_TILE_INDEX 1
SEC_RDATA_TILE_INDEX 0
SEC_RDATA_LANE_INDEX 0
SEC_WDATA_TILE_INDEX 0
SEC_WDATA_LANE_INDEX 0
SEC_AC_TILE_INDEX 1
LANES_USAGE_0 757373805
LANES_USAGE_1 365
LANES_USAGE_2 0
LANES_USAGE_3 0
LANES_USAGE_AUTOGEN_WCNT 4
PINS_USAGE_0 1056960511
PINS_USAGE_1 763363263
PINS_USAGE_2 955224063
PINS_USAGE_3 1073479600
PINS_USAGE_4 1056960510
PINS_USAGE_5 63
PINS_USAGE_6 0
PINS_USAGE_7 0
PINS_USAGE_8 0
PINS_USAGE_9 0
PINS_USAGE_10 0
PINS_USAGE_11 0
PINS_USAGE_12 0
PINS_USAGE_AUTOGEN_WCNT 13
PINS_RATE_0 1
PINS_RATE_1 561774592
PINS_RATE_2 955224063
PINS_RATE_3 0
PINS_RATE_4 0
PINS_RATE_5 0
PINS_RATE_6 0
PINS_RATE_7 0
PINS_RATE_8 0
PINS_RATE_9 0
PINS_RATE_10 0
PINS_RATE_11 0
PINS_RATE_12 0
PINS_RATE_AUTOGEN_WCNT 13
PINS_WDB_0 920202678
PINS_WDB_1 910912566
PINS_WDB_2 316345782
PINS_WDB_3 918777270
PINS_WDB_4 165375378
PINS_WDB_5 136581193
PINS_WDB_6 153391689
PINS_WDB_7 153387017
PINS_WDB_8 153092680
PINS_WDB_9 918589440
PINS_WDB_10 819686802
PINS_WDB_11 920347830
PINS_WDB_12 920202672
PINS_WDB_13 910912566
PINS_WDB_14 316345782
PINS_WDB_15 224694
PINS_WDB_16 0
PINS_WDB_17 0
PINS_WDB_18 0
PINS_WDB_19 0
PINS_WDB_20 0
PINS_WDB_21 0
PINS_WDB_22 0
PINS_WDB_23 0
PINS_WDB_24 0
PINS_WDB_25 0
PINS_WDB_26 0
PINS_WDB_27 0
PINS_WDB_28 0
PINS_WDB_29 0
PINS_WDB_30 0
PINS_WDB_31 0
PINS_WDB_32 0
PINS_WDB_33 0
PINS_WDB_34 0
PINS_WDB_35 0
PINS_WDB_36 0
PINS_WDB_37 0
PINS_WDB_38 0
PINS_WDB_AUTOGEN_WCNT 39
PINS_DATA_IN_MODE_0 153612873
PINS_DATA_IN_MODE_1 167547401
PINS_DATA_IN_MODE_2 1059357257
PINS_DATA_IN_MODE_3 153129545
PINS_DATA_IN_MODE_4 153391743
PINS_DATA_IN_MODE_5 150736969
PINS_DATA_IN_MODE_6 153391689
PINS_DATA_IN_MODE_7 153387017
PINS_DATA_IN_MODE_8 153092680
PINS_DATA_IN_MODE_9 153350144
PINS_DATA_IN_MODE_10 136614527
PINS_DATA_IN_MODE_11 153395145
PINS_DATA_IN_MODE_12 153612872
PINS_DATA_IN_MODE_13 167547401
PINS_DATA_IN_MODE_14 1059357257
PINS_DATA_IN_MODE_15 37449
PINS_DATA_IN_MODE_16 0
PINS_DATA_IN_MODE_17 0
PINS_DATA_IN_MODE_18 0
PINS_DATA_IN_MODE_19 0
PINS_DATA_IN_MODE_20 0
PINS_DATA_IN_MODE_21 0
PINS_DATA_IN_MODE_22 0
PINS_DATA_IN_MODE_23 0
PINS_DATA_IN_MODE_24 0
PINS_DATA_IN_MODE_25 0
PINS_DATA_IN_MODE_26 0
PINS_DATA_IN_MODE_27 0
PINS_DATA_IN_MODE_28 0
PINS_DATA_IN_MODE_29 0
PINS_DATA_IN_MODE_30 0
PINS_DATA_IN_MODE_31 0
PINS_DATA_IN_MODE_32 0
PINS_DATA_IN_MODE_33 0
PINS_DATA_IN_MODE_34 0
PINS_DATA_IN_MODE_35 0
PINS_DATA_IN_MODE_36 0
PINS_DATA_IN_MODE_37 0
PINS_DATA_IN_MODE_38 0
PINS_DATA_IN_MODE_AUTOGEN_WCNT 39
PINS_C2L_DRIVEN_0 251457486
PINS_C2L_DRIVEN_1 259007
PINS_C2L_DRIVEN_2 0
PINS_C2L_DRIVEN_3 1060893568
PINS_C2L_DRIVEN_4 251457486
PINS_C2L_DRIVEN_5 63
PINS_C2L_DRIVEN_6 0
PINS_C2L_DRIVEN_7 0
PINS_C2L_DRIVEN_8 0
PINS_C2L_DRIVEN_9 0
PINS_C2L_DRIVEN_10 0
PINS_C2L_DRIVEN_11 0
PINS_C2L_DRIVEN_12 0
PINS_C2L_DRIVEN_AUTOGEN_WCNT 13
PINS_DB_IN_BYPASS_0 1
PINS_DB_IN_BYPASS_1 763101184
PINS_DB_IN_BYPASS_2 955224063
PINS_DB_IN_BYPASS_3 48
PINS_DB_IN_BYPASS_4 0
PINS_DB_IN_BYPASS_5 0
PINS_DB_IN_BYPASS_6 0
PINS_DB_IN_BYPASS_7 0
PINS_DB_IN_BYPASS_8 0
PINS_DB_IN_BYPASS_9 0
PINS_DB_IN_BYPASS_10 0
PINS_DB_IN_BYPASS_11 0
PINS_DB_IN_BYPASS_12 0
PINS_DB_IN_BYPASS_AUTOGEN_WCNT 13
PINS_DB_OUT_BYPASS_0 1
PINS_DB_OUT_BYPASS_1 763101184
PINS_DB_OUT_BYPASS_2 955224063
PINS_DB_OUT_BYPASS_3 48
PINS_DB_OUT_BYPASS_4 0
PINS_DB_OUT_BYPASS_5 0
PINS_DB_OUT_BYPASS_6 0
PINS_DB_OUT_BYPASS_7 0
PINS_DB_OUT_BYPASS_8 0
PINS_DB_OUT_BYPASS_9 0
PINS_DB_OUT_BYPASS_10 0
PINS_DB_OUT_BYPASS_11 0
PINS_DB_OUT_BYPASS_12 0
PINS_DB_OUT_BYPASS_AUTOGEN_WCNT 13
PINS_DB_OE_BYPASS_0 1
PINS_DB_OE_BYPASS_1 763101184
PINS_DB_OE_BYPASS_2 955224063
PINS_DB_OE_BYPASS_3 48
PINS_DB_OE_BYPASS_4 0
PINS_DB_OE_BYPASS_5 0
PINS_DB_OE_BYPASS_6 0
PINS_DB_OE_BYPASS_7 0
PINS_DB_OE_BYPASS_8 0
PINS_DB_OE_BYPASS_9 0
PINS_DB_OE_BYPASS_10 0
PINS_DB_OE_BYPASS_11 0
PINS_DB_OE_BYPASS_12 0
PINS_DB_OE_BYPASS_AUTOGEN_WCNT 13
PINS_INVERT_WR_0 537002016
PINS_INVERT_WR_1 2048
PINS_INVERT_WR_2 0
PINS_INVERT_WR_3 8390656
PINS_INVERT_WR_4 537002016
PINS_INVERT_WR_5 0
PINS_INVERT_WR_6 0
PINS_INVERT_WR_7 0
PINS_INVERT_WR_8 0
PINS_INVERT_WR_9 0
PINS_INVERT_WR_10 0
PINS_INVERT_WR_11 0
PINS_INVERT_WR_12 0
PINS_INVERT_WR_AUTOGEN_WCNT 13
PINS_INVERT_OE_0 1056960510
PINS_INVERT_OE_1 763363263
PINS_INVERT_OE_2 955224063
PINS_INVERT_OE_3 1073479600
PINS_INVERT_OE_4 1056960510
PINS_INVERT_OE_5 63
PINS_INVERT_OE_6 0
PINS_INVERT_OE_7 0
PINS_INVERT_OE_8 0
PINS_INVERT_OE_9 0
PINS_INVERT_OE_10 0
PINS_INVERT_OE_11 0
PINS_INVERT_OE_12 0
PINS_INVERT_OE_AUTOGEN_WCNT 13
PINS_AC_HMC_DATA_OVERRIDE_ENA_0 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_1 201326592
PINS_AC_HMC_DATA_OVERRIDE_ENA_2 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_3 48
PINS_AC_HMC_DATA_OVERRIDE_ENA_4 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_5 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_6 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_7 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_8 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_9 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_10 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_11 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_12 0
PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT 13
PINS_OCT_MODE_0 1056960510
PINS_OCT_MODE_1 262079
PINS_OCT_MODE_2 0
PINS_OCT_MODE_3 1073479552
PINS_OCT_MODE_4 1056960510
PINS_OCT_MODE_5 63
PINS_OCT_MODE_6 0
PINS_OCT_MODE_7 0
PINS_OCT_MODE_8 0
PINS_OCT_MODE_9 0
PINS_OCT_MODE_10 0
PINS_OCT_MODE_11 0
PINS_OCT_MODE_12 0
PINS_OCT_MODE_AUTOGEN_WCNT 13
PINS_GPIO_MODE_0 1
PINS_GPIO_MODE_1 0
PINS_GPIO_MODE_2 0
PINS_GPIO_MODE_3 0
PINS_GPIO_MODE_4 0
PINS_GPIO_MODE_5 0
PINS_GPIO_MODE_6 0
PINS_GPIO_MODE_7 0
PINS_GPIO_MODE_8 0
PINS_GPIO_MODE_9 0
PINS_GPIO_MODE_10 0
PINS_GPIO_MODE_11 0
PINS_GPIO_MODE_12 0
PINS_GPIO_MODE_AUTOGEN_WCNT 13
UNUSED_MEM_PINS_PINLOC_0 199425082
UNUSED_MEM_PINS_PINLOC_1 196276413
UNUSED_MEM_PINS_PINLOC_2 193127610
UNUSED_MEM_PINS_PINLOC_3 189978807
UNUSED_MEM_PINS_PINLOC_4 186830004
UNUSED_MEM_PINS_PINLOC_5 183681201
UNUSED_MEM_PINS_PINLOC_6 180532398
UNUSED_MEM_PINS_PINLOC_7 177383595
UNUSED_MEM_PINS_PINLOC_8 174234792
UNUSED_MEM_PINS_PINLOC_9 171085989
UNUSED_MEM_PINS_PINLOC_10 167937186
UNUSED_MEM_PINS_PINLOC_11 164788383
UNUSED_MEM_PINS_PINLOC_12 138559644
UNUSED_MEM_PINS_PINLOC_13 100774008
UNUSED_MEM_PINS_PINLOC_14 95514717
UNUSED_MEM_PINS_PINLOC_15 89217114
UNUSED_MEM_PINS_PINLOC_16 77676628
UNUSED_MEM_PINS_PINLOC_17 60891209
UNUSED_MEM_PINS_PINLOC_18 37803063
UNUSED_MEM_PINS_PINLOC_19 12312
UNUSED_MEM_PINS_PINLOC_20 0
UNUSED_MEM_PINS_PINLOC_21 0
UNUSED_MEM_PINS_PINLOC_22 0
UNUSED_MEM_PINS_PINLOC_23 0
UNUSED_MEM_PINS_PINLOC_24 0
UNUSED_MEM_PINS_PINLOC_25 0
UNUSED_MEM_PINS_PINLOC_26 0
UNUSED_MEM_PINS_PINLOC_27 0
UNUSED_MEM_PINS_PINLOC_28 0
UNUSED_MEM_PINS_PINLOC_29 0
UNUSED_MEM_PINS_PINLOC_30 0
UNUSED_MEM_PINS_PINLOC_31 0
UNUSED_MEM_PINS_PINLOC_32 0
UNUSED_MEM_PINS_PINLOC_33 0
UNUSED_MEM_PINS_PINLOC_34 0
UNUSED_MEM_PINS_PINLOC_35 0
UNUSED_MEM_PINS_PINLOC_36 0
UNUSED_MEM_PINS_PINLOC_37 0
UNUSED_MEM_PINS_PINLOC_38 0
UNUSED_MEM_PINS_PINLOC_39 0
UNUSED_MEM_PINS_PINLOC_40 0
UNUSED_MEM_PINS_PINLOC_41 0
UNUSED_MEM_PINS_PINLOC_42 0
UNUSED_MEM_PINS_PINLOC_43 0
UNUSED_MEM_PINS_PINLOC_44 0
UNUSED_MEM_PINS_PINLOC_45 0
UNUSED_MEM_PINS_PINLOC_46 0
UNUSED_MEM_PINS_PINLOC_47 0
UNUSED_MEM_PINS_PINLOC_48 0
UNUSED_MEM_PINS_PINLOC_49 0
UNUSED_MEM_PINS_PINLOC_50 0
UNUSED_MEM_PINS_PINLOC_51 0
UNUSED_MEM_PINS_PINLOC_52 0
UNUSED_MEM_PINS_PINLOC_53 0
UNUSED_MEM_PINS_PINLOC_54 0
UNUSED_MEM_PINS_PINLOC_55 0
UNUSED_MEM_PINS_PINLOC_56 0
UNUSED_MEM_PINS_PINLOC_57 0
UNUSED_MEM_PINS_PINLOC_58 0
UNUSED_MEM_PINS_PINLOC_59 0
UNUSED_MEM_PINS_PINLOC_60 0
UNUSED_MEM_PINS_PINLOC_61 0
UNUSED_MEM_PINS_PINLOC_62 0
UNUSED_MEM_PINS_PINLOC_63 0
UNUSED_MEM_PINS_PINLOC_64 0
UNUSED_MEM_PINS_PINLOC_65 0
UNUSED_MEM_PINS_PINLOC_66 0
UNUSED_MEM_PINS_PINLOC_67 0
UNUSED_MEM_PINS_PINLOC_68 0
UNUSED_MEM_PINS_PINLOC_69 0
UNUSED_MEM_PINS_PINLOC_70 0
UNUSED_MEM_PINS_PINLOC_71 0
UNUSED_MEM_PINS_PINLOC_72 0
UNUSED_MEM_PINS_PINLOC_73 0
UNUSED_MEM_PINS_PINLOC_74 0
UNUSED_MEM_PINS_PINLOC_75 0
UNUSED_MEM_PINS_PINLOC_76 0
UNUSED_MEM_PINS_PINLOC_77 0
UNUSED_MEM_PINS_PINLOC_78 0
UNUSED_MEM_PINS_PINLOC_79 0
UNUSED_MEM_PINS_PINLOC_80 0
UNUSED_MEM_PINS_PINLOC_81 0
UNUSED_MEM_PINS_PINLOC_82 0
UNUSED_MEM_PINS_PINLOC_83 0
UNUSED_MEM_PINS_PINLOC_84 0
UNUSED_MEM_PINS_PINLOC_85 0
UNUSED_MEM_PINS_PINLOC_86 0
UNUSED_MEM_PINS_PINLOC_87 0
UNUSED_MEM_PINS_PINLOC_88 0
UNUSED_MEM_PINS_PINLOC_89 0
UNUSED_MEM_PINS_PINLOC_90 0
UNUSED_MEM_PINS_PINLOC_91 0
UNUSED_MEM_PINS_PINLOC_92 0
UNUSED_MEM_PINS_PINLOC_93 0
UNUSED_MEM_PINS_PINLOC_94 0
UNUSED_MEM_PINS_PINLOC_95 0
UNUSED_MEM_PINS_PINLOC_96 0
UNUSED_MEM_PINS_PINLOC_97 0
UNUSED_MEM_PINS_PINLOC_98 0
UNUSED_MEM_PINS_PINLOC_99 0
UNUSED_MEM_PINS_PINLOC_100 0
UNUSED_MEM_PINS_PINLOC_101 0
UNUSED_MEM_PINS_PINLOC_102 0
UNUSED_MEM_PINS_PINLOC_103 0
UNUSED_MEM_PINS_PINLOC_104 0
UNUSED_MEM_PINS_PINLOC_105 0
UNUSED_MEM_PINS_PINLOC_106 0
UNUSED_MEM_PINS_PINLOC_107 0
UNUSED_MEM_PINS_PINLOC_108 0
UNUSED_MEM_PINS_PINLOC_109 0
UNUSED_MEM_PINS_PINLOC_110 0
UNUSED_MEM_PINS_PINLOC_111 0
UNUSED_MEM_PINS_PINLOC_112 0
UNUSED_MEM_PINS_PINLOC_113 0
UNUSED_MEM_PINS_PINLOC_114 0
UNUSED_MEM_PINS_PINLOC_115 0
UNUSED_MEM_PINS_PINLOC_116 0
UNUSED_MEM_PINS_PINLOC_117 0
UNUSED_MEM_PINS_PINLOC_118 0
UNUSED_MEM_PINS_PINLOC_119 0
UNUSED_MEM_PINS_PINLOC_120 0
UNUSED_MEM_PINS_PINLOC_121 0
UNUSED_MEM_PINS_PINLOC_122 0
UNUSED_MEM_PINS_PINLOC_123 0
UNUSED_MEM_PINS_PINLOC_124 0
UNUSED_MEM_PINS_PINLOC_125 0
UNUSED_MEM_PINS_PINLOC_126 0
UNUSED_MEM_PINS_PINLOC_127 0
UNUSED_MEM_PINS_PINLOC_128 0
UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT 129
UNUSED_DQS_BUSES_LANELOC_0 14695431
UNUSED_DQS_BUSES_LANELOC_1 6298637
UNUSED_DQS_BUSES_LANELOC_2 4101
UNUSED_DQS_BUSES_LANELOC_3 0
UNUSED_DQS_BUSES_LANELOC_4 0
UNUSED_DQS_BUSES_LANELOC_5 0
UNUSED_DQS_BUSES_LANELOC_6 0
UNUSED_DQS_BUSES_LANELOC_7 0
UNUSED_DQS_BUSES_LANELOC_8 0
UNUSED_DQS_BUSES_LANELOC_9 0
UNUSED_DQS_BUSES_LANELOC_10 0
UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT 11
CENTER_TIDS_0 542119940
CENTER_TIDS_1 3
CENTER_TIDS_2 0
CENTER_TIDS_AUTOGEN_WCNT 3
HMC_TIDS_0 676600325
HMC_TIDS_1 3
HMC_TIDS_2 0
HMC_TIDS_AUTOGEN_WCNT 3
LANE_TIDS_0 403177984
LANE_TIDS_1 168067584
LANE_TIDS_2 35717208
LANE_TIDS_3 140518930
LANE_TIDS_4 886403
LANE_TIDS_5 0
LANE_TIDS_6 0
LANE_TIDS_7 0
LANE_TIDS_8 0
LANE_TIDS_9 0
LANE_TIDS_AUTOGEN_WCNT 10
PREAMBLE_MODE preamble_one_cycle
DBI_WR_ENABLE false
DBI_RD_ENABLE false
CRC_EN crc_disable
SWAP_DQS_A_B false
DQS_PACK_MODE packed
OCT_SIZE 3
DBC_WB_RESERVED_ENTRY 8
DLL_MODE ctl_dynamic
DLL_CODEWORD 0
ABPHY_WRITE_PROTOCOL 0
PHY_USERMODE_OCT false
PHY_PERIODIC_OCT_RECAL false
PHY_HAS_DCC true
PRI_HMC_CFG_ENABLE_ECC disable
PRI_HMC_CFG_REORDER_DATA enable
PRI_HMC_CFG_REORDER_READ enable
PRI_HMC_CFG_REORDER_RDATA enable
PRI_HMC_CFG_STARVE_LIMIT 63
PRI_HMC_CFG_DQS_TRACKING_EN disable
PRI_HMC_CFG_ARBITER_TYPE twot
PRI_HMC_CFG_OPEN_PAGE_EN enable
PRI_HMC_CFG_GEAR_DOWN_EN disable
PRI_HMC_CFG_RLD3_MULTIBANK_MODE singlebank
PRI_HMC_CFG_PING_PONG_MODE pingpong_off
PRI_HMC_CFG_SLOT_ROTATE_EN 0
PRI_HMC_CFG_SLOT_OFFSET 2
PRI_HMC_CFG_COL_CMD_SLOT 2
PRI_HMC_CFG_ROW_CMD_SLOT 1
PRI_HMC_CFG_ENABLE_RC enable
PRI_HMC_CFG_CS_TO_CHIP_MAPPING 33825
PRI_HMC_CFG_RB_RESERVED_ENTRY 8
PRI_HMC_CFG_WB_RESERVED_ENTRY 8
PRI_HMC_CFG_TCL 18
PRI_HMC_CFG_POWER_SAVING_EXIT_CYC 3
PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC 15
PRI_HMC_CFG_WRITE_ODT_CHIP 33
PRI_HMC_CFG_READ_ODT_CHIP 0
PRI_HMC_CFG_WR_ODT_ON 0
PRI_HMC_CFG_RD_ODT_ON 0
PRI_HMC_CFG_WR_ODT_PERIOD 6
PRI_HMC_CFG_RD_ODT_PERIOD 6
PRI_HMC_CFG_RLD3_REFRESH_SEQ0 15
PRI_HMC_CFG_RLD3_REFRESH_SEQ1 240
PRI_HMC_CFG_RLD3_REFRESH_SEQ2 3840
PRI_HMC_CFG_RLD3_REFRESH_SEQ3 61440
PRI_HMC_CFG_SRF_ZQCAL_DISABLE disable
PRI_HMC_CFG_MPS_ZQCAL_DISABLE disable
PRI_HMC_CFG_MPS_DQSTRK_DISABLE disable
PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN disable
PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN disable
PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL 512
PRI_HMC_CFG_DQSTRK_TO_VALID_LAST 27
PRI_HMC_CFG_DQSTRK_TO_VALID 3
PRI_HMC_CFG_RFSH_WARN_THRESHOLD 4
PRI_HMC_CFG_SB_CG_DISABLE disable
PRI_HMC_CFG_USER_RFSH_EN disable
PRI_HMC_CFG_SRF_AUTOEXIT_EN disable
PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK presrfexit
PRI_HMC_CFG_SB_DDR4_MR3 197120
PRI_HMC_CFG_SB_DDR4_MR4 262144
PRI_HMC_CFG_SB_DDR4_MR5 1056
PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR 0
PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH col_width_10
PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH row_width_15
PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH bank_width_2
PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH bg_width_2
PRI_HMC_CFG_LOCAL_IF_CS_WIDTH cs_width_1
PRI_HMC_CFG_ADDR_ORDER chip_row_bank_col
PRI_HMC_CFG_ACT_TO_RDWR 8
PRI_HMC_CFG_ACT_TO_PCH 20
PRI_HMC_CFG_ACT_TO_ACT 29
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK 3
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG 2
PRI_HMC_CFG_RD_TO_RD 3
PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP 3
PRI_HMC_CFG_RD_TO_RD_DIFF_BG 2
PRI_HMC_CFG_RD_TO_WR 5
PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP 5
PRI_HMC_CFG_RD_TO_WR_DIFF_BG 5
PRI_HMC_CFG_RD_TO_PCH 5
PRI_HMC_CFG_RD_AP_TO_VALID 14
PRI_HMC_CFG_WR_TO_WR 3
PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP 3
PRI_HMC_CFG_WR_TO_WR_DIFF_BG 2
PRI_HMC_CFG_WR_TO_RD 16
PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP 6
PRI_HMC_CFG_WR_TO_RD_DIFF_BG 16
PRI_HMC_CFG_WR_TO_PCH 21
PRI_HMC_CFG_WR_AP_TO_VALID 29
PRI_HMC_CFG_PCH_TO_VALID 9
PRI_HMC_CFG_PCH_ALL_TO_VALID 9
PRI_HMC_CFG_ARF_TO_VALID 97
PRI_HMC_CFG_PDN_TO_VALID 5
PRI_HMC_CFG_SRF_TO_VALID 513
PRI_HMC_CFG_SRF_TO_ZQ_CAL 449
PRI_HMC_CFG_ARF_PERIOD 4681
PRI_HMC_CFG_PDN_PERIOD 0
PRI_HMC_CFG_ZQCL_TO_VALID 257
PRI_HMC_CFG_ZQCS_TO_VALID 65
PRI_HMC_CFG_MRS_TO_VALID 7
PRI_HMC_CFG_MPS_TO_VALID 768
PRI_HMC_CFG_MRR_TO_VALID 0
PRI_HMC_CFG_MPR_TO_VALID 16
PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE 5
PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS 6
PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY 0
PRI_HMC_CFG_MMR_CMD_TO_VALID 16
PRI_HMC_CFG_4_ACT_TO_ACT 14
PRI_HMC_CFG_16_ACT_TO_ACT 0
SEC_HMC_CFG_ENABLE_ECC disable
SEC_HMC_CFG_REORDER_DATA enable
SEC_HMC_CFG_REORDER_READ enable
SEC_HMC_CFG_REORDER_RDATA enable
SEC_HMC_CFG_STARVE_LIMIT 63
SEC_HMC_CFG_DQS_TRACKING_EN disable
SEC_HMC_CFG_ARBITER_TYPE twot
SEC_HMC_CFG_OPEN_PAGE_EN enable
SEC_HMC_CFG_GEAR_DOWN_EN disable
SEC_HMC_CFG_RLD3_MULTIBANK_MODE singlebank
SEC_HMC_CFG_PING_PONG_MODE pingpong_off
SEC_HMC_CFG_SLOT_ROTATE_EN 0
SEC_HMC_CFG_SLOT_OFFSET 2
SEC_HMC_CFG_COL_CMD_SLOT 2
SEC_HMC_CFG_ROW_CMD_SLOT 1
SEC_HMC_CFG_ENABLE_RC enable
SEC_HMC_CFG_CS_TO_CHIP_MAPPING 33825
SEC_HMC_CFG_RB_RESERVED_ENTRY 8
SEC_HMC_CFG_WB_RESERVED_ENTRY 8
SEC_HMC_CFG_TCL 18
SEC_HMC_CFG_POWER_SAVING_EXIT_CYC 3
SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC 15
SEC_HMC_CFG_WRITE_ODT_CHIP 33
SEC_HMC_CFG_READ_ODT_CHIP 0
SEC_HMC_CFG_WR_ODT_ON 0
SEC_HMC_CFG_RD_ODT_ON 0
SEC_HMC_CFG_WR_ODT_PERIOD 6
SEC_HMC_CFG_RD_ODT_PERIOD 6
SEC_HMC_CFG_RLD3_REFRESH_SEQ0 15
SEC_HMC_CFG_RLD3_REFRESH_SEQ1 240
SEC_HMC_CFG_RLD3_REFRESH_SEQ2 3840
SEC_HMC_CFG_RLD3_REFRESH_SEQ3 61440
SEC_HMC_CFG_SRF_ZQCAL_DISABLE disable
SEC_HMC_CFG_MPS_ZQCAL_DISABLE disable
SEC_HMC_CFG_MPS_DQSTRK_DISABLE disable
SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN disable
SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN disable
SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL 512
SEC_HMC_CFG_DQSTRK_TO_VALID_LAST 27
SEC_HMC_CFG_DQSTRK_TO_VALID 3
SEC_HMC_CFG_RFSH_WARN_THRESHOLD 4
SEC_HMC_CFG_SB_CG_DISABLE disable
SEC_HMC_CFG_USER_RFSH_EN disable
SEC_HMC_CFG_SRF_AUTOEXIT_EN disable
SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK presrfexit
SEC_HMC_CFG_SB_DDR4_MR3 197120
SEC_HMC_CFG_SB_DDR4_MR4 262144
SEC_HMC_CFG_SB_DDR4_MR5 1056
SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR 0
SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH col_width_10
SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH row_width_15
SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH bank_width_2
SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH bg_width_2
SEC_HMC_CFG_LOCAL_IF_CS_WIDTH cs_width_1
SEC_HMC_CFG_ADDR_ORDER chip_row_bank_col
SEC_HMC_CFG_ACT_TO_RDWR 8
SEC_HMC_CFG_ACT_TO_PCH 20
SEC_HMC_CFG_ACT_TO_ACT 29
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK 3
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG 2
SEC_HMC_CFG_RD_TO_RD 3
SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP 3
SEC_HMC_CFG_RD_TO_RD_DIFF_BG 2
SEC_HMC_CFG_RD_TO_WR 5
SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP 5
SEC_HMC_CFG_RD_TO_WR_DIFF_BG 5
SEC_HMC_CFG_RD_TO_PCH 5
SEC_HMC_CFG_RD_AP_TO_VALID 14
SEC_HMC_CFG_WR_TO_WR 3
SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP 3
SEC_HMC_CFG_WR_TO_WR_DIFF_BG 2
SEC_HMC_CFG_WR_TO_RD 16
SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP 6
SEC_HMC_CFG_WR_TO_RD_DIFF_BG 16
SEC_HMC_CFG_WR_TO_PCH 21
SEC_HMC_CFG_WR_AP_TO_VALID 29
SEC_HMC_CFG_PCH_TO_VALID 9
SEC_HMC_CFG_PCH_ALL_TO_VALID 9
SEC_HMC_CFG_ARF_TO_VALID 97
SEC_HMC_CFG_PDN_TO_VALID 5
SEC_HMC_CFG_SRF_TO_VALID 513
SEC_HMC_CFG_SRF_TO_ZQ_CAL 449
SEC_HMC_CFG_ARF_PERIOD 4681
SEC_HMC_CFG_PDN_PERIOD 0
SEC_HMC_CFG_ZQCL_TO_VALID 257
SEC_HMC_CFG_ZQCS_TO_VALID 65
SEC_HMC_CFG_MRS_TO_VALID 7
SEC_HMC_CFG_MPS_TO_VALID 768
SEC_HMC_CFG_MRR_TO_VALID 0
SEC_HMC_CFG_MPR_TO_VALID 16
SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE 5
SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS 6
SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY 0
SEC_HMC_CFG_MMR_CMD_TO_VALID 16
SEC_HMC_CFG_4_ACT_TO_ACT 14
SEC_HMC_CFG_16_ACT_TO_ACT 0
PINS_PER_LANE 12
LANES_PER_TILE 4
OCT_CONTROL_WIDTH 16
PORT_MEM_CK_WIDTH 2
PORT_MEM_CK_PINLOC_0 98623490
PORT_MEM_CK_PINLOC_1 0
PORT_MEM_CK_PINLOC_2 0
PORT_MEM_CK_PINLOC_3 0
PORT_MEM_CK_PINLOC_4 0
PORT_MEM_CK_PINLOC_5 0
PORT_MEM_CK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CK_N_WIDTH 2
PORT_MEM_CK_N_PINLOC_0 99673090
PORT_MEM_CK_N_PINLOC_1 0
PORT_MEM_CK_N_PINLOC_2 0
PORT_MEM_CK_N_PINLOC_3 0
PORT_MEM_CK_N_PINLOC_4 0
PORT_MEM_CK_N_PINLOC_5 0
PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DK_WIDTH 1
PORT_MEM_DK_PINLOC_0 0
PORT_MEM_DK_PINLOC_1 0
PORT_MEM_DK_PINLOC_2 0
PORT_MEM_DK_PINLOC_3 0
PORT_MEM_DK_PINLOC_4 0
PORT_MEM_DK_PINLOC_5 0
PORT_MEM_DK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DK_N_WIDTH 1
PORT_MEM_DK_N_PINLOC_0 0
PORT_MEM_DK_N_PINLOC_1 0
PORT_MEM_DK_N_PINLOC_2 0
PORT_MEM_DK_N_PINLOC_3 0
PORT_MEM_DK_N_PINLOC_4 0
PORT_MEM_DK_N_PINLOC_5 0
PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKA_WIDTH 1
PORT_MEM_DKA_PINLOC_0 0
PORT_MEM_DKA_PINLOC_1 0
PORT_MEM_DKA_PINLOC_2 0
PORT_MEM_DKA_PINLOC_3 0
PORT_MEM_DKA_PINLOC_4 0
PORT_MEM_DKA_PINLOC_5 0
PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKA_N_WIDTH 1
PORT_MEM_DKA_N_PINLOC_0 0
PORT_MEM_DKA_N_PINLOC_1 0
PORT_MEM_DKA_N_PINLOC_2 0
PORT_MEM_DKA_N_PINLOC_3 0
PORT_MEM_DKA_N_PINLOC_4 0
PORT_MEM_DKA_N_PINLOC_5 0
PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKB_WIDTH 1
PORT_MEM_DKB_PINLOC_0 0
PORT_MEM_DKB_PINLOC_1 0
PORT_MEM_DKB_PINLOC_2 0
PORT_MEM_DKB_PINLOC_3 0
PORT_MEM_DKB_PINLOC_4 0
PORT_MEM_DKB_PINLOC_5 0
PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKB_N_WIDTH 1
PORT_MEM_DKB_N_PINLOC_0 0
PORT_MEM_DKB_N_PINLOC_1 0
PORT_MEM_DKB_N_PINLOC_2 0
PORT_MEM_DKB_N_PINLOC_3 0
PORT_MEM_DKB_N_PINLOC_4 0
PORT_MEM_DKB_N_PINLOC_5 0
PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_K_WIDTH 1
PORT_MEM_K_PINLOC_0 0
PORT_MEM_K_PINLOC_1 0
PORT_MEM_K_PINLOC_2 0
PORT_MEM_K_PINLOC_3 0
PORT_MEM_K_PINLOC_4 0
PORT_MEM_K_PINLOC_5 0
PORT_MEM_K_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_K_N_WIDTH 1
PORT_MEM_K_N_PINLOC_0 0
PORT_MEM_K_N_PINLOC_1 0
PORT_MEM_K_N_PINLOC_2 0
PORT_MEM_K_N_PINLOC_3 0
PORT_MEM_K_N_PINLOC_4 0
PORT_MEM_K_N_PINLOC_5 0
PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_A_WIDTH 17
PORT_MEM_A_PINLOC_0 64024593
PORT_MEM_A_PINLOC_1 67173438
PORT_MEM_A_PINLOC_2 70322241
PORT_MEM_A_PINLOC_3 73471044
PORT_MEM_A_PINLOC_4 79768647
PORT_MEM_A_PINLOC_5 82917453
PORT_MEM_A_PINLOC_6 0
PORT_MEM_A_PINLOC_7 0
PORT_MEM_A_PINLOC_8 0
PORT_MEM_A_PINLOC_9 0
PORT_MEM_A_PINLOC_10 0
PORT_MEM_A_PINLOC_11 0
PORT_MEM_A_PINLOC_12 0
PORT_MEM_A_PINLOC_13 0
PORT_MEM_A_PINLOC_14 0
PORT_MEM_A_PINLOC_15 0
PORT_MEM_A_PINLOC_16 0
PORT_MEM_A_PINLOC_AUTOGEN_WCNT 17
PORT_MEM_BA_WIDTH 2
PORT_MEM_BA_PINLOC_0 86066178
PORT_MEM_BA_PINLOC_1 0
PORT_MEM_BA_PINLOC_2 0
PORT_MEM_BA_PINLOC_3 0
PORT_MEM_BA_PINLOC_4 0
PORT_MEM_BA_PINLOC_5 0
PORT_MEM_BA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_BG_WIDTH 2
PORT_MEM_BG_PINLOC_0 50416642
PORT_MEM_BG_PINLOC_1 0
PORT_MEM_BG_PINLOC_2 0
PORT_MEM_BG_PINLOC_3 0
PORT_MEM_BG_PINLOC_4 0
PORT_MEM_BG_PINLOC_5 0
PORT_MEM_BG_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_C_WIDTH 1
PORT_MEM_C_PINLOC_0 0
PORT_MEM_C_PINLOC_1 0
PORT_MEM_C_PINLOC_2 0
PORT_MEM_C_PINLOC_3 0
PORT_MEM_C_PINLOC_4 0
PORT_MEM_C_PINLOC_5 0
PORT_MEM_C_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CKE_WIDTH 2
PORT_MEM_CKE_PINLOC_0 93378562
PORT_MEM_CKE_PINLOC_1 0
PORT_MEM_CKE_PINLOC_2 0
PORT_MEM_CKE_PINLOC_3 0
PORT_MEM_CKE_PINLOC_4 0
PORT_MEM_CKE_PINLOC_5 0
PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CS_N_WIDTH 2
PORT_MEM_CS_N_PINLOC_0 91277314
PORT_MEM_CS_N_PINLOC_1 0
PORT_MEM_CS_N_PINLOC_2 0
PORT_MEM_CS_N_PINLOC_3 0
PORT_MEM_CS_N_PINLOC_4 0
PORT_MEM_CS_N_PINLOC_5 0
PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_RM_WIDTH 1
PORT_MEM_RM_PINLOC_0 0
PORT_MEM_RM_PINLOC_1 0
PORT_MEM_RM_PINLOC_2 0
PORT_MEM_RM_PINLOC_3 0
PORT_MEM_RM_PINLOC_4 0
PORT_MEM_RM_PINLOC_5 0
PORT_MEM_RM_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_ODT_WIDTH 2
PORT_MEM_ODT_PINLOC_0 92327938
PORT_MEM_ODT_PINLOC_1 0
PORT_MEM_ODT_PINLOC_2 0
PORT_MEM_ODT_PINLOC_3 0
PORT_MEM_ODT_PINLOC_4 0
PORT_MEM_ODT_PINLOC_5 0
PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_RAS_N_WIDTH 1
PORT_MEM_RAS_N_PINLOC_0 0
PORT_MEM_RAS_N_PINLOC_1 0
PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CAS_N_WIDTH 1
PORT_MEM_CAS_N_PINLOC_0 0
PORT_MEM_CAS_N_PINLOC_1 0
PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_WE_N_WIDTH 1
PORT_MEM_WE_N_PINLOC_0 0
PORT_MEM_WE_N_PINLOC_1 0
PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_RESET_N_WIDTH 1
PORT_MEM_RESET_N_PINLOC_0 50177
PORT_MEM_RESET_N_PINLOC_1 0
PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_ACT_N_WIDTH 1
PORT_MEM_ACT_N_PINLOC_0 52225
PORT_MEM_ACT_N_PINLOC_1 0
PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_PAR_WIDTH 1
PORT_MEM_PAR_PINLOC_0 60417
PORT_MEM_PAR_PINLOC_1 0
PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CA_WIDTH 1
PORT_MEM_CA_PINLOC_0 0
PORT_MEM_CA_PINLOC_1 0
PORT_MEM_CA_PINLOC_2 0
PORT_MEM_CA_PINLOC_3 0
PORT_MEM_CA_PINLOC_4 0
PORT_MEM_CA_PINLOC_5 0
PORT_MEM_CA_PINLOC_6 0
PORT_MEM_CA_PINLOC_7 0
PORT_MEM_CA_PINLOC_8 0
PORT_MEM_CA_PINLOC_9 0
PORT_MEM_CA_PINLOC_10 0
PORT_MEM_CA_PINLOC_11 0
PORT_MEM_CA_PINLOC_12 0
PORT_MEM_CA_PINLOC_13 0
PORT_MEM_CA_PINLOC_14 0
PORT_MEM_CA_PINLOC_15 0
PORT_MEM_CA_PINLOC_16 0
PORT_MEM_CA_PINLOC_AUTOGEN_WCNT 17
PORT_MEM_REF_N_WIDTH 1
PORT_MEM_REF_N_PINLOC_0 0
PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_WPS_N_WIDTH 1
PORT_MEM_WPS_N_PINLOC_0 0
PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RPS_N_WIDTH 1
PORT_MEM_RPS_N_PINLOC_0 0
PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_DOFF_N_WIDTH 1
PORT_MEM_DOFF_N_PINLOC_0 0
PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LDA_N_WIDTH 1
PORT_MEM_LDA_N_PINLOC_0 0
PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LDB_N_WIDTH 1
PORT_MEM_LDB_N_PINLOC_0 0
PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RWA_N_WIDTH 1
PORT_MEM_RWA_N_PINLOC_0 0
PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RWB_N_WIDTH 1
PORT_MEM_RWB_N_PINLOC_0 0
PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LBK0_N_WIDTH 1
PORT_MEM_LBK0_N_PINLOC_0 0
PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LBK1_N_WIDTH 1
PORT_MEM_LBK1_N_PINLOC_0 0
PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_CFG_N_WIDTH 1
PORT_MEM_CFG_N_PINLOC_0 0
PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_AP_WIDTH 1
PORT_MEM_AP_PINLOC_0 0
PORT_MEM_AP_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_AINV_WIDTH 1
PORT_MEM_AINV_PINLOC_0 0
PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_DM_WIDTH 1
PORT_MEM_DM_PINLOC_0 0
PORT_MEM_DM_PINLOC_1 0
PORT_MEM_DM_PINLOC_2 0
PORT_MEM_DM_PINLOC_3 0
PORT_MEM_DM_PINLOC_4 0
PORT_MEM_DM_PINLOC_5 0
PORT_MEM_DM_PINLOC_6 0
PORT_MEM_DM_PINLOC_7 0
PORT_MEM_DM_PINLOC_8 0
PORT_MEM_DM_PINLOC_9 0
PORT_MEM_DM_PINLOC_10 0
PORT_MEM_DM_PINLOC_11 0
PORT_MEM_DM_PINLOC_12 0
PORT_MEM_DM_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_BWS_N_WIDTH 1
PORT_MEM_BWS_N_PINLOC_0 0
PORT_MEM_BWS_N_PINLOC_1 0
PORT_MEM_BWS_N_PINLOC_2 0
PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_D_WIDTH 1
PORT_MEM_D_PINLOC_0 0
PORT_MEM_D_PINLOC_1 0
PORT_MEM_D_PINLOC_2 0
PORT_MEM_D_PINLOC_3 0
PORT_MEM_D_PINLOC_4 0
PORT_MEM_D_PINLOC_5 0
PORT_MEM_D_PINLOC_6 0
PORT_MEM_D_PINLOC_7 0
PORT_MEM_D_PINLOC_8 0
PORT_MEM_D_PINLOC_9 0
PORT_MEM_D_PINLOC_10 0
PORT_MEM_D_PINLOC_11 0
PORT_MEM_D_PINLOC_12 0
PORT_MEM_D_PINLOC_13 0
PORT_MEM_D_PINLOC_14 0
PORT_MEM_D_PINLOC_15 0
PORT_MEM_D_PINLOC_16 0
PORT_MEM_D_PINLOC_17 0
PORT_MEM_D_PINLOC_18 0
PORT_MEM_D_PINLOC_19 0
PORT_MEM_D_PINLOC_20 0
PORT_MEM_D_PINLOC_21 0
PORT_MEM_D_PINLOC_22 0
PORT_MEM_D_PINLOC_23 0
PORT_MEM_D_PINLOC_24 0
PORT_MEM_D_PINLOC_25 0
PORT_MEM_D_PINLOC_26 0
PORT_MEM_D_PINLOC_27 0
PORT_MEM_D_PINLOC_28 0
PORT_MEM_D_PINLOC_29 0
PORT_MEM_D_PINLOC_30 0
PORT_MEM_D_PINLOC_31 0
PORT_MEM_D_PINLOC_32 0
PORT_MEM_D_PINLOC_33 0
PORT_MEM_D_PINLOC_34 0
PORT_MEM_D_PINLOC_35 0
PORT_MEM_D_PINLOC_36 0
PORT_MEM_D_PINLOC_37 0
PORT_MEM_D_PINLOC_38 0
PORT_MEM_D_PINLOC_39 0
PORT_MEM_D_PINLOC_40 0
PORT_MEM_D_PINLOC_41 0
PORT_MEM_D_PINLOC_42 0
PORT_MEM_D_PINLOC_43 0
PORT_MEM_D_PINLOC_44 0
PORT_MEM_D_PINLOC_45 0
PORT_MEM_D_PINLOC_46 0
PORT_MEM_D_PINLOC_47 0
PORT_MEM_D_PINLOC_48 0
PORT_MEM_D_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQ_WIDTH 72
PORT_MEM_DQ_PINLOC_0 2098248
PORT_MEM_DQ_PINLOC_1 7346179
PORT_MEM_DQ_PINLOC_2 10494984
PORT_MEM_DQ_PINLOC_3 15742989
PORT_MEM_DQ_PINLOC_4 20990994
PORT_MEM_DQ_PINLOC_5 26236949
PORT_MEM_DQ_PINLOC_6 31484954
PORT_MEM_DQ_PINLOC_7 34635807
PORT_MEM_DQ_PINLOC_8 39883810
PORT_MEM_DQ_PINLOC_9 45131815
PORT_MEM_DQ_PINLOC_10 48280620
PORT_MEM_DQ_PINLOC_11 103909473
PORT_MEM_DQ_PINLOC_12 109157478
PORT_MEM_DQ_PINLOC_13 114403433
PORT_MEM_DQ_PINLOC_14 119651438
PORT_MEM_DQ_PINLOC_15 122802291
PORT_MEM_DQ_PINLOC_16 128050294
PORT_MEM_DQ_PINLOC_17 133298299
PORT_MEM_DQ_PINLOC_18 136447104
PORT_MEM_DQ_PINLOC_19 141695109
PORT_MEM_DQ_PINLOC_20 146943114
PORT_MEM_DQ_PINLOC_21 152189069
PORT_MEM_DQ_PINLOC_22 157437074
PORT_MEM_DQ_PINLOC_23 160587927
PORT_MEM_DQ_PINLOC_24 154
PORT_MEM_DQ_PINLOC_25 0
PORT_MEM_DQ_PINLOC_26 0
PORT_MEM_DQ_PINLOC_27 0
PORT_MEM_DQ_PINLOC_28 0
PORT_MEM_DQ_PINLOC_29 0
PORT_MEM_DQ_PINLOC_30 0
PORT_MEM_DQ_PINLOC_31 0
PORT_MEM_DQ_PINLOC_32 0
PORT_MEM_DQ_PINLOC_33 0
PORT_MEM_DQ_PINLOC_34 0
PORT_MEM_DQ_PINLOC_35 0
PORT_MEM_DQ_PINLOC_36 0
PORT_MEM_DQ_PINLOC_37 0
PORT_MEM_DQ_PINLOC_38 0
PORT_MEM_DQ_PINLOC_39 0
PORT_MEM_DQ_PINLOC_40 0
PORT_MEM_DQ_PINLOC_41 0
PORT_MEM_DQ_PINLOC_42 0
PORT_MEM_DQ_PINLOC_43 0
PORT_MEM_DQ_PINLOC_44 0
PORT_MEM_DQ_PINLOC_45 0
PORT_MEM_DQ_PINLOC_46 0
PORT_MEM_DQ_PINLOC_47 0
PORT_MEM_DQ_PINLOC_48 0
PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DBI_N_WIDTH 9
PORT_MEM_DBI_N_PINLOC_0 24128521
PORT_MEM_DBI_N_PINLOC_1 112245795
PORT_MEM_DBI_N_PINLOC_2 150080631
PORT_MEM_DBI_N_PINLOC_3 155
PORT_MEM_DBI_N_PINLOC_4 0
PORT_MEM_DBI_N_PINLOC_5 0
PORT_MEM_DBI_N_PINLOC_6 0
PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT 7
PORT_MEM_DQA_WIDTH 1
PORT_MEM_DQA_PINLOC_0 0
PORT_MEM_DQA_PINLOC_1 0
PORT_MEM_DQA_PINLOC_2 0
PORT_MEM_DQA_PINLOC_3 0
PORT_MEM_DQA_PINLOC_4 0
PORT_MEM_DQA_PINLOC_5 0
PORT_MEM_DQA_PINLOC_6 0
PORT_MEM_DQA_PINLOC_7 0
PORT_MEM_DQA_PINLOC_8 0
PORT_MEM_DQA_PINLOC_9 0
PORT_MEM_DQA_PINLOC_10 0
PORT_MEM_DQA_PINLOC_11 0
PORT_MEM_DQA_PINLOC_12 0
PORT_MEM_DQA_PINLOC_13 0
PORT_MEM_DQA_PINLOC_14 0
PORT_MEM_DQA_PINLOC_15 0
PORT_MEM_DQA_PINLOC_16 0
PORT_MEM_DQA_PINLOC_17 0
PORT_MEM_DQA_PINLOC_18 0
PORT_MEM_DQA_PINLOC_19 0
PORT_MEM_DQA_PINLOC_20 0
PORT_MEM_DQA_PINLOC_21 0
PORT_MEM_DQA_PINLOC_22 0
PORT_MEM_DQA_PINLOC_23 0
PORT_MEM_DQA_PINLOC_24 0
PORT_MEM_DQA_PINLOC_25 0
PORT_MEM_DQA_PINLOC_26 0
PORT_MEM_DQA_PINLOC_27 0
PORT_MEM_DQA_PINLOC_28 0
PORT_MEM_DQA_PINLOC_29 0
PORT_MEM_DQA_PINLOC_30 0
PORT_MEM_DQA_PINLOC_31 0
PORT_MEM_DQA_PINLOC_32 0
PORT_MEM_DQA_PINLOC_33 0
PORT_MEM_DQA_PINLOC_34 0
PORT_MEM_DQA_PINLOC_35 0
PORT_MEM_DQA_PINLOC_36 0
PORT_MEM_DQA_PINLOC_37 0
PORT_MEM_DQA_PINLOC_38 0
PORT_MEM_DQA_PINLOC_39 0
PORT_MEM_DQA_PINLOC_40 0
PORT_MEM_DQA_PINLOC_41 0
PORT_MEM_DQA_PINLOC_42 0
PORT_MEM_DQA_PINLOC_43 0
PORT_MEM_DQA_PINLOC_44 0
PORT_MEM_DQA_PINLOC_45 0
PORT_MEM_DQA_PINLOC_46 0
PORT_MEM_DQA_PINLOC_47 0
PORT_MEM_DQA_PINLOC_48 0
PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQB_WIDTH 1
PORT_MEM_DQB_PINLOC_0 0
PORT_MEM_DQB_PINLOC_1 0
PORT_MEM_DQB_PINLOC_2 0
PORT_MEM_DQB_PINLOC_3 0
PORT_MEM_DQB_PINLOC_4 0
PORT_MEM_DQB_PINLOC_5 0
PORT_MEM_DQB_PINLOC_6 0
PORT_MEM_DQB_PINLOC_7 0
PORT_MEM_DQB_PINLOC_8 0
PORT_MEM_DQB_PINLOC_9 0
PORT_MEM_DQB_PINLOC_10 0
PORT_MEM_DQB_PINLOC_11 0
PORT_MEM_DQB_PINLOC_12 0
PORT_MEM_DQB_PINLOC_13 0
PORT_MEM_DQB_PINLOC_14 0
PORT_MEM_DQB_PINLOC_15 0
PORT_MEM_DQB_PINLOC_16 0
PORT_MEM_DQB_PINLOC_17 0
PORT_MEM_DQB_PINLOC_18 0
PORT_MEM_DQB_PINLOC_19 0
PORT_MEM_DQB_PINLOC_20 0
PORT_MEM_DQB_PINLOC_21 0
PORT_MEM_DQB_PINLOC_22 0
PORT_MEM_DQB_PINLOC_23 0
PORT_MEM_DQB_PINLOC_24 0
PORT_MEM_DQB_PINLOC_25 0
PORT_MEM_DQB_PINLOC_26 0
PORT_MEM_DQB_PINLOC_27 0
PORT_MEM_DQB_PINLOC_28 0
PORT_MEM_DQB_PINLOC_29 0
PORT_MEM_DQB_PINLOC_30 0
PORT_MEM_DQB_PINLOC_31 0
PORT_MEM_DQB_PINLOC_32 0
PORT_MEM_DQB_PINLOC_33 0
PORT_MEM_DQB_PINLOC_34 0
PORT_MEM_DQB_PINLOC_35 0
PORT_MEM_DQB_PINLOC_36 0
PORT_MEM_DQB_PINLOC_37 0
PORT_MEM_DQB_PINLOC_38 0
PORT_MEM_DQB_PINLOC_39 0
PORT_MEM_DQB_PINLOC_40 0
PORT_MEM_DQB_PINLOC_41 0
PORT_MEM_DQB_PINLOC_42 0
PORT_MEM_DQB_PINLOC_43 0
PORT_MEM_DQB_PINLOC_44 0
PORT_MEM_DQB_PINLOC_45 0
PORT_MEM_DQB_PINLOC_46 0
PORT_MEM_DQB_PINLOC_47 0
PORT_MEM_DQB_PINLOC_48 0
PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DINVA_WIDTH 1
PORT_MEM_DINVA_PINLOC_0 0
PORT_MEM_DINVA_PINLOC_1 0
PORT_MEM_DINVA_PINLOC_2 0
PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_DINVB_WIDTH 1
PORT_MEM_DINVB_PINLOC_0 0
PORT_MEM_DINVB_PINLOC_1 0
PORT_MEM_DINVB_PINLOC_2 0
PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_Q_WIDTH 1
PORT_MEM_Q_PINLOC_0 0
PORT_MEM_Q_PINLOC_1 0
PORT_MEM_Q_PINLOC_2 0
PORT_MEM_Q_PINLOC_3 0
PORT_MEM_Q_PINLOC_4 0
PORT_MEM_Q_PINLOC_5 0
PORT_MEM_Q_PINLOC_6 0
PORT_MEM_Q_PINLOC_7 0
PORT_MEM_Q_PINLOC_8 0
PORT_MEM_Q_PINLOC_9 0
PORT_MEM_Q_PINLOC_10 0
PORT_MEM_Q_PINLOC_11 0
PORT_MEM_Q_PINLOC_12 0
PORT_MEM_Q_PINLOC_13 0
PORT_MEM_Q_PINLOC_14 0
PORT_MEM_Q_PINLOC_15 0
PORT_MEM_Q_PINLOC_16 0
PORT_MEM_Q_PINLOC_17 0
PORT_MEM_Q_PINLOC_18 0
PORT_MEM_Q_PINLOC_19 0
PORT_MEM_Q_PINLOC_20 0
PORT_MEM_Q_PINLOC_21 0
PORT_MEM_Q_PINLOC_22 0
PORT_MEM_Q_PINLOC_23 0
PORT_MEM_Q_PINLOC_24 0
PORT_MEM_Q_PINLOC_25 0
PORT_MEM_Q_PINLOC_26 0
PORT_MEM_Q_PINLOC_27 0
PORT_MEM_Q_PINLOC_28 0
PORT_MEM_Q_PINLOC_29 0
PORT_MEM_Q_PINLOC_30 0
PORT_MEM_Q_PINLOC_31 0
PORT_MEM_Q_PINLOC_32 0
PORT_MEM_Q_PINLOC_33 0
PORT_MEM_Q_PINLOC_34 0
PORT_MEM_Q_PINLOC_35 0
PORT_MEM_Q_PINLOC_36 0
PORT_MEM_Q_PINLOC_37 0
PORT_MEM_Q_PINLOC_38 0
PORT_MEM_Q_PINLOC_39 0
PORT_MEM_Q_PINLOC_40 0
PORT_MEM_Q_PINLOC_41 0
PORT_MEM_Q_PINLOC_42 0
PORT_MEM_Q_PINLOC_43 0
PORT_MEM_Q_PINLOC_44 0
PORT_MEM_Q_PINLOC_45 0
PORT_MEM_Q_PINLOC_46 0
PORT_MEM_Q_PINLOC_47 0
PORT_MEM_Q_PINLOC_48 0
PORT_MEM_Q_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQS_WIDTH 9
PORT_MEM_DQS_PINLOC_0 16781321
PORT_MEM_DQS_PINLOC_1 104898588
PORT_MEM_DQS_PINLOC_2 142733424
PORT_MEM_DQS_PINLOC_3 148
PORT_MEM_DQS_PINLOC_4 0
PORT_MEM_DQS_PINLOC_5 0
PORT_MEM_DQS_PINLOC_6 0
PORT_MEM_DQS_PINLOC_7 0
PORT_MEM_DQS_PINLOC_8 0
PORT_MEM_DQS_PINLOC_9 0
PORT_MEM_DQS_PINLOC_10 0
PORT_MEM_DQS_PINLOC_11 0
PORT_MEM_DQS_PINLOC_12 0
PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_DQS_N_WIDTH 9
PORT_MEM_DQS_N_PINLOC_0 17830921
PORT_MEM_DQS_N_PINLOC_1 105948189
PORT_MEM_DQS_N_PINLOC_2 143783025
PORT_MEM_DQS_N_PINLOC_3 149
PORT_MEM_DQS_N_PINLOC_4 0
PORT_MEM_DQS_N_PINLOC_5 0
PORT_MEM_DQS_N_PINLOC_6 0
PORT_MEM_DQS_N_PINLOC_7 0
PORT_MEM_DQS_N_PINLOC_8 0
PORT_MEM_DQS_N_PINLOC_9 0
PORT_MEM_DQS_N_PINLOC_10 0
PORT_MEM_DQS_N_PINLOC_11 0
PORT_MEM_DQS_N_PINLOC_12 0
PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_QK_WIDTH 1
PORT_MEM_QK_PINLOC_0 0
PORT_MEM_QK_PINLOC_1 0
PORT_MEM_QK_PINLOC_2 0
PORT_MEM_QK_PINLOC_3 0
PORT_MEM_QK_PINLOC_4 0
PORT_MEM_QK_PINLOC_5 0
PORT_MEM_QK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QK_N_WIDTH 1
PORT_MEM_QK_N_PINLOC_0 0
PORT_MEM_QK_N_PINLOC_1 0
PORT_MEM_QK_N_PINLOC_2 0
PORT_MEM_QK_N_PINLOC_3 0
PORT_MEM_QK_N_PINLOC_4 0
PORT_MEM_QK_N_PINLOC_5 0
PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKA_WIDTH 1
PORT_MEM_QKA_PINLOC_0 0
PORT_MEM_QKA_PINLOC_1 0
PORT_MEM_QKA_PINLOC_2 0
PORT_MEM_QKA_PINLOC_3 0
PORT_MEM_QKA_PINLOC_4 0
PORT_MEM_QKA_PINLOC_5 0
PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKA_N_WIDTH 1
PORT_MEM_QKA_N_PINLOC_0 0
PORT_MEM_QKA_N_PINLOC_1 0
PORT_MEM_QKA_N_PINLOC_2 0
PORT_MEM_QKA_N_PINLOC_3 0
PORT_MEM_QKA_N_PINLOC_4 0
PORT_MEM_QKA_N_PINLOC_5 0
PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKB_WIDTH 1
PORT_MEM_QKB_PINLOC_0 0
PORT_MEM_QKB_PINLOC_1 0
PORT_MEM_QKB_PINLOC_2 0
PORT_MEM_QKB_PINLOC_3 0
PORT_MEM_QKB_PINLOC_4 0
PORT_MEM_QKB_PINLOC_5 0
PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKB_N_WIDTH 1
PORT_MEM_QKB_N_PINLOC_0 0
PORT_MEM_QKB_N_PINLOC_1 0
PORT_MEM_QKB_N_PINLOC_2 0
PORT_MEM_QKB_N_PINLOC_3 0
PORT_MEM_QKB_N_PINLOC_4 0
PORT_MEM_QKB_N_PINLOC_5 0
PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CQ_WIDTH 1
PORT_MEM_CQ_PINLOC_0 0
PORT_MEM_CQ_PINLOC_1 0
PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CQ_N_WIDTH 1
PORT_MEM_CQ_N_PINLOC_0 0
PORT_MEM_CQ_N_PINLOC_1 0
PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_ALERT_N_WIDTH 1
PORT_MEM_ALERT_N_PINLOC_0 1
PORT_MEM_ALERT_N_PINLOC_1 0
PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_PE_N_WIDTH 1
PORT_MEM_PE_N_PINLOC_0 0
PORT_MEM_PE_N_PINLOC_1 0
PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT 2
PORT_CLKS_SHARING_MASTER_OUT_WIDTH 32
PORT_CLKS_SHARING_SLAVE_IN_WIDTH 32
PORT_CLKS_SHARING_SLAVE_OUT_WIDTH 32
PORT_AFI_RLAT_WIDTH 6
PORT_AFI_WLAT_WIDTH 6
PORT_AFI_SEQ_BUSY_WIDTH 4
PORT_AFI_ADDR_WIDTH 1
PORT_AFI_BA_WIDTH 1
PORT_AFI_BG_WIDTH 1
PORT_AFI_C_WIDTH 1
PORT_AFI_CKE_WIDTH 1
PORT_AFI_CS_N_WIDTH 1
PORT_AFI_RM_WIDTH 1
PORT_AFI_ODT_WIDTH 1
PORT_AFI_RAS_N_WIDTH 1
PORT_AFI_CAS_N_WIDTH 1
PORT_AFI_WE_N_WIDTH 1
PORT_AFI_RST_N_WIDTH 1
PORT_AFI_ACT_N_WIDTH 1
PORT_AFI_PAR_WIDTH 1
PORT_AFI_CA_WIDTH 1
PORT_AFI_REF_N_WIDTH 1
PORT_AFI_WPS_N_WIDTH 1
PORT_AFI_RPS_N_WIDTH 1
PORT_AFI_DOFF_N_WIDTH 1
PORT_AFI_LD_N_WIDTH 1
PORT_AFI_RW_N_WIDTH 1
PORT_AFI_LBK0_N_WIDTH 1
PORT_AFI_LBK1_N_WIDTH 1
PORT_AFI_CFG_N_WIDTH 1
PORT_AFI_AP_WIDTH 1
PORT_AFI_AINV_WIDTH 1
PORT_AFI_DM_WIDTH 1
PORT_AFI_DM_N_WIDTH 1
PORT_AFI_BWS_N_WIDTH 1
PORT_AFI_RDATA_DBI_N_WIDTH 1
PORT_AFI_WDATA_DBI_N_WIDTH 1
PORT_AFI_RDATA_DINV_WIDTH 1
PORT_AFI_WDATA_DINV_WIDTH 1
PORT_AFI_DQS_BURST_WIDTH 1
PORT_AFI_WDATA_VALID_WIDTH 1
PORT_AFI_WDATA_WIDTH 1
PORT_AFI_RDATA_EN_FULL_WIDTH 1
PORT_AFI_RDATA_WIDTH 1
PORT_AFI_RDATA_VALID_WIDTH 1
PORT_AFI_RRANK_WIDTH 1
PORT_AFI_WRANK_WIDTH 1
PORT_AFI_ALERT_N_WIDTH 1
PORT_AFI_PE_N_WIDTH 1
PORT_CTRL_AST_CMD_DATA_WIDTH 1
PORT_CTRL_AST_WR_DATA_WIDTH 1
PORT_CTRL_AST_RD_DATA_WIDTH 1
PORT_CTRL_AMM_ADDRESS_WIDTH 27
PORT_CTRL_AMM_RDATA_WIDTH 576
PORT_CTRL_AMM_WDATA_WIDTH 576
PORT_CTRL_AMM_BCOUNT_WIDTH 7
PORT_CTRL_AMM_BYTEEN_WIDTH 72
PORT_CTRL_USER_REFRESH_REQ_WIDTH 4
PORT_CTRL_USER_REFRESH_BANK_WIDTH 16
PORT_CTRL_SELF_REFRESH_REQ_WIDTH 4
PORT_CTRL_ECC_WRITE_INFO_WIDTH 15
PORT_CTRL_ECC_RDATA_ID_WIDTH 13
PORT_CTRL_ECC_READ_INFO_WIDTH 3
PORT_CTRL_ECC_CMD_INFO_WIDTH 3
PORT_CTRL_ECC_WB_POINTER_WIDTH 12
PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH 10
PORT_CTRL_MMR_SLAVE_RDATA_WIDTH 32
PORT_CTRL_MMR_SLAVE_WDATA_WIDTH 32
PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH 2
PORT_HPS_EMIF_H2E_WIDTH 4096
PORT_HPS_EMIF_E2H_WIDTH 4096
PORT_HPS_EMIF_H2E_GP_WIDTH 2
PORT_HPS_EMIF_E2H_GP_WIDTH 1
PORT_CAL_DEBUG_ADDRESS_WIDTH 24
PORT_CAL_DEBUG_RDATA_WIDTH 32
PORT_CAL_DEBUG_WDATA_WIDTH 32
PORT_CAL_DEBUG_BYTEEN_WIDTH 4
PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH 24
PORT_CAL_DEBUG_OUT_RDATA_WIDTH 32
PORT_CAL_DEBUG_OUT_WDATA_WIDTH 32
PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH 4
PORT_CAL_MASTER_ADDRESS_WIDTH 16
PORT_CAL_MASTER_RDATA_WIDTH 32
PORT_CAL_MASTER_WDATA_WIDTH 32
PORT_CAL_MASTER_BYTEEN_WIDTH 4
PORT_DFT_NF_IOAUX_PIO_IN_WIDTH 8
PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH 8
PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH 9
PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH 8
PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH 8
PORT_DFT_NF_PLL_CNTSEL_WIDTH 4
PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH 3
PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH 2
PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH 2
PLL_VCO_FREQ_MHZ_INT 1200
PLL_VCO_TO_MEM_CLK_FREQ_RATIO 1
PLL_PHY_CLK_VCO_PHASE 1
PLL_VCO_FREQ_PS_STR 834 ps
PLL_REF_CLK_FREQ_PS_STR 40032 ps
PLL_REF_CLK_FREQ_PS 40032
PLL_SIM_VCO_FREQ_PS 840
PLL_SIM_PHYCLK_0_FREQ_PS 1680
PLL_SIM_PHYCLK_1_FREQ_PS 3360
PLL_SIM_PHYCLK_FB_FREQ_PS 3360
PLL_SIM_PHY_CLK_VCO_PHASE_PS 105
PLL_SIM_CAL_SLAVE_CLK_FREQ_PS 6720
PLL_SIM_CAL_MASTER_CLK_FREQ_PS 6720
PLL_M_CNT_HIGH 24
PLL_M_CNT_LOW 24
PLL_N_CNT_HIGH 256
PLL_N_CNT_LOW 256
PLL_M_CNT_BYPASS_EN false
PLL_N_CNT_BYPASS_EN true
PLL_M_CNT_EVEN_DUTY_EN false
PLL_N_CNT_EVEN_DUTY_EN false
PLL_FBCLK_MUX_1 pll_fbclk_mux_1_glb
PLL_FBCLK_MUX_2 pll_fbclk_mux_2_m_cnt
PLL_M_CNT_IN_SRC c_m_cnt_in_src_ph_mux_clk
PLL_CP_SETTING pll_cp_setting28
PLL_BW_CTRL pll_bw_res_setting5
PLL_BW_SEL high
PLL_C_CNT_HIGH_0 2
PLL_C_CNT_LOW_0 2
PLL_C_CNT_PRST_0 1
PLL_C_CNT_PH_MUX_PRST_0 1
PLL_C_CNT_BYPASS_EN_0 false
PLL_C_CNT_EVEN_DUTY_EN_0 false
PLL_C_CNT_FREQ_PS_STR_0 3336 ps
PLL_C_CNT_PHASE_PS_STR_0 104 ps
PLL_C_CNT_DUTY_CYCLE_0 50
PLL_C_CNT_OUT_EN_0 true
PLL_C_CNT_HIGH_1 1
PLL_C_CNT_LOW_1 1
PLL_C_CNT_PRST_1 1
PLL_C_CNT_PH_MUX_PRST_1 1
PLL_C_CNT_BYPASS_EN_1 false
PLL_C_CNT_EVEN_DUTY_EN_1 false
PLL_C_CNT_FREQ_PS_STR_1 1668 ps
PLL_C_CNT_PHASE_PS_STR_1 104 ps
PLL_C_CNT_DUTY_CYCLE_1 50
PLL_C_CNT_OUT_EN_1 true
PLL_C_CNT_HIGH_2 2
PLL_C_CNT_LOW_2 2
PLL_C_CNT_PRST_2 1
PLL_C_CNT_PH_MUX_PRST_2 1
PLL_C_CNT_BYPASS_EN_2 false
PLL_C_CNT_EVEN_DUTY_EN_2 false
PLL_C_CNT_FREQ_PS_STR_2 3336 ps
PLL_C_CNT_PHASE_PS_STR_2 104 ps
PLL_C_CNT_DUTY_CYCLE_2 50
PLL_C_CNT_OUT_EN_2 true
PLL_C_CNT_HIGH_3 4
PLL_C_CNT_LOW_3 4
PLL_C_CNT_PRST_3 1
PLL_C_CNT_PH_MUX_PRST_3 0
PLL_C_CNT_BYPASS_EN_3 false
PLL_C_CNT_EVEN_DUTY_EN_3 false
PLL_C_CNT_FREQ_PS_STR_3 6672 ps
PLL_C_CNT_PHASE_PS_STR_3 0 ps
PLL_C_CNT_DUTY_CYCLE_3 50
PLL_C_CNT_OUT_EN_3 true
PLL_C_CNT_HIGH_4 4
PLL_C_CNT_LOW_4 4
PLL_C_CNT_PRST_4 1
PLL_C_CNT_PH_MUX_PRST_4 0
PLL_C_CNT_BYPASS_EN_4 false
PLL_C_CNT_EVEN_DUTY_EN_4 false
PLL_C_CNT_FREQ_PS_STR_4 6672 ps
PLL_C_CNT_PHASE_PS_STR_4 0 ps
PLL_C_CNT_DUTY_CYCLE_4 50
PLL_C_CNT_OUT_EN_4 true
PLL_C_CNT_HIGH_5 256
PLL_C_CNT_LOW_5 256
PLL_C_CNT_PRST_5 1
PLL_C_CNT_PH_MUX_PRST_5 0
PLL_C_CNT_BYPASS_EN_5 true
PLL_C_CNT_EVEN_DUTY_EN_5 false
PLL_C_CNT_FREQ_PS_STR_5 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_5 0 ps
PLL_C_CNT_DUTY_CYCLE_5 50
PLL_C_CNT_OUT_EN_5 false
PLL_C_CNT_HIGH_6 256
PLL_C_CNT_LOW_6 256
PLL_C_CNT_PRST_6 1
PLL_C_CNT_PH_MUX_PRST_6 0
PLL_C_CNT_BYPASS_EN_6 true
PLL_C_CNT_EVEN_DUTY_EN_6 false
PLL_C_CNT_FREQ_PS_STR_6 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_6 0 ps
PLL_C_CNT_DUTY_CYCLE_6 50
PLL_C_CNT_OUT_EN_6 false
PLL_C_CNT_HIGH_7 256
PLL_C_CNT_LOW_7 256
PLL_C_CNT_PRST_7 1
PLL_C_CNT_PH_MUX_PRST_7 0
PLL_C_CNT_BYPASS_EN_7 true
PLL_C_CNT_EVEN_DUTY_EN_7 false
PLL_C_CNT_FREQ_PS_STR_7 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_7 0 ps
PLL_C_CNT_DUTY_CYCLE_7 50
PLL_C_CNT_OUT_EN_7 false
PLL_C_CNT_HIGH_8 256
PLL_C_CNT_LOW_8 256
PLL_C_CNT_PRST_8 1
PLL_C_CNT_PH_MUX_PRST_8 0
PLL_C_CNT_BYPASS_EN_8 true
PLL_C_CNT_EVEN_DUTY_EN_8 false
PLL_C_CNT_FREQ_PS_STR_8 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_8 0 ps
PLL_C_CNT_DUTY_CYCLE_8 50
PLL_C_CNT_OUT_EN_8 false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_cal_slave_component

altera_emif_cal_slave_nf v18.0


Parameters

ENABLE_JTAG_UART false
ENABLE_SOFT_RAM true
SOFT_RAM_HEXFILE ../../emif/ip_arch_nf/src/seq_cal_soft_m20k.hex
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_cal_slave_component_clk_bridge

altera_clock_bridge v18.0
ddr4_inst_arch cal_slave_clk_clock_source   ddr4_inst_cal_slave_component_clk_bridge
  in_clk
out_clk   ddr4_inst_cal_slave_component_ioaux_master_bridge
  clk
out_clk   ddr4_inst_cal_slave_component_ioaux_soft_ram
  clk1


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_cal_slave_component_rst_bridge

altera_reset_bridge v18.0
ddr4_inst_arch cal_slave_reset_n_reset_source   ddr4_inst_cal_slave_component_rst_bridge
  in_reset
out_reset   ddr4_inst_cal_slave_component_ioaux_master_bridge
  reset
out_reset   ddr4_inst_cal_slave_component_ioaux_soft_ram
  reset1


Parameters

ACTIVE_LOW_RESET 0
SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
USE_RESET_REQUEST 0
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_cal_slave_component_ioaux_master_bridge

altera_avalon_mm_bridge v18.0
ddr4_inst_cal_slave_component_clk_bridge out_clk   ddr4_inst_cal_slave_component_ioaux_master_bridge
  clk
ddr4_inst_cal_slave_component_rst_bridge out_reset  
  reset
ddr4_inst_arch cal_master_avalon_master  
  s0
m0   ddr4_inst_cal_slave_component_ioaux_soft_ram
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 16
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 14
ADDRESS_UNITS SYMBOLS
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_inst_cal_slave_component_ioaux_soft_ram

altera_avalon_onchip_memory2 v18.0
ddr4_inst_cal_slave_component_ioaux_master_bridge m0   ddr4_inst_cal_slave_component_ioaux_soft_ram
  s1
ddr4_inst_cal_slave_component_clk_bridge out_clk  
  clk1
ddr4_inst_cal_slave_component_rst_bridge out_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
enableDiffWidth false
initMemContent true
initializationFileName ../../emif/ip_arch_nf/src/seq_cal_soft_m20k.hex
enPRInitMode false
instanceID NONE
memorySize 16383
readDuringWriteMode DONT_CARE
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile true
useShallowMemBlocks false
writable false
ecc_enabled false
resetrequest_enabled false
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE seq_cal_soft_m20k
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 1
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 16383
WRITABLE 0
generation took 0.00 seconds rendering took 0.04 seconds