diff --git a/args_logger.py b/args_logger.py
new file mode 100644
index 0000000000000000000000000000000000000000..415dd27d59b08512c4cff5465fb185e733d2be0a
--- /dev/null
+++ b/args_logger.py
@@ -0,0 +1,87 @@
+
+import os
+import logging
+import time
+
+
+class MyLogger(object):
+    def __init__(self, log_path=None, file_name=None):
+        self.log_levels = {'DEBUG'  : logging.DEBUG,
+                           'INFO'   : logging.INFO,
+                           'WARNING': logging.WARNING,
+                           'ERROR'  : logging.ERROR}
+        
+        self.log_path = os.getcwd() if log_path is None else log_path
+        try:
+            os.stat(self.log_path)
+        except FileNotFoundError:
+            print("'%s' does not exist, making it now", self.log_path)
+            os.makedirs(self.log_path)
+        
+        self.filename = None
+        self.stdout_log_level = 'WARNING'
+        self.file_log_level = 'INFO'
+        self.backup_depth = 0
+        self.file_logger_handler = None
+        self.stdout_logger_handler = None
+        
+        self.logger = logging.getLogger('main')
+        self.logger.setLevel(logging.DEBUG)
+        self._setup_stdout_logging()
+        if file_name is not None:
+            self.set_logfile_name(file_name)
+
+    def get_logger(self):
+        return self.logger
+
+    def set_logfile_name(self, name):
+        self.filename = name
+        self._backup_logfiles()
+        self._setup_file_logging()
+    
+    def set_stdout_log_level(self, level):
+        _level = level.upper()
+        if _level in self.log_levels:
+            self.stdout_log_level = _level
+            if self.stdout_logger_handler:
+                self.stdout_logger_handler.setLevel(self.log_levels[_level])
+        else:
+            self.logger.error("'{}' is not a valid level".format(level))
+    
+    def set_file_log_level(self, level):
+        _level = level.upper()
+        if _level in self.log_levels:
+            self.file_log_level = _level
+            if self.file_logger_handler:
+                self.file_logger_handler.setLevel(self.log_levels[_level])
+        else:
+            self.logger.error("'{}' is not a valid level".format(level))
+        
+    def _backup_logfiles(self):
+        for nr in range(self.backup_depth-1, -1, -1):
+            if nr == 0:
+                full_filename = os.path.join(self.log_path, '{}.log'.format(self.filename))
+            else:
+                full_filename = os.path.join(self.log_path, '{}.log.{}'.format(self.filename, nr))
+            full_filename_new = os.path.join(self.log_path, '{}.log.{}'.format(self.filename, nr+1))
+            if os.path.exists(full_filename):
+                os.rename(full_filename, full_filename_new)
+
+    def _setup_stdout_logging(self):
+        # create console handler
+        stream_handler = logging.StreamHandler()
+        formatter = logging.Formatter('%(asctime)s %(name)-19s %(levelname)-7s %(message)s')
+        stream_handler.setFormatter(formatter)
+        stream_handler.setLevel(self.log_levels[self.stdout_log_level])
+        self.logger.addHandler(stream_handler)
+        self.stdout_logger_handler = self.logger.handlers[0]
+        
+    def _setup_file_logging(self):
+        # create file handler
+        full_filename = os.path.join(self.log_path, '{}.log'.format(self.filename))
+        file_handler = logging.FileHandler(full_filename, mode='w')
+        formatter = logging.Formatter('%(asctime)s %(name)-19s %(levelname)-8s %(message)s')
+        file_handler.setFormatter(formatter)
+        file_handler.setLevel(self.log_levels[self.file_log_level])
+        self.logger.addHandler(file_handler)
+        self.file_logger_handler = self.logger.handlers[1]
\ No newline at end of file
diff --git a/gen_c_config.py b/gen_c_config.py
index c84ed355f39fef00bde5320604afae17a36751a6..d5fd0c5149ce563291f2512601dff39e70aa4b3f 100755
--- a/gen_c_config.py
+++ b/gen_c_config.py
@@ -184,7 +184,9 @@ if __name__ == '__main__':
     parser = ArgumentParser(
         description='ARGS tool script to generate fpgamap.py M&C Python client include file')
     parser.add_argument('-f', '--fpga', required=True, help='ARGS fpga_name')
-    fpga_name = parser.parse_args().fpga
+    args = parser.parse_args()
+
+    fpga_name = args.fpga
 
     # Find and parse all *.fpga.yaml YAML files under root directory for RADIOHDL
     # For each FPGA file it extracts a list of the peripherals that are used by that FPGA
diff --git a/gen_doc.py b/gen_doc.py
index 48287c7ed41e40910a679c1c3810e7ddc7c98595..3ca639b1c2d64a4477ba543e44dc25dd0264c829 100755
--- a/gen_doc.py
+++ b/gen_doc.py
@@ -44,9 +44,9 @@ from pylatex.utils import italic, bold, NoEscape, verbatim, escape_latex
 from copy import deepcopy
 from math import ceil
 
+from args_logger import MyLogger
 from py_args_lib import *
 
-
 def gen_reg_tables(subsection, group_fields):
     """
     Takes a list of fields belonging to a field group and a register subsection
@@ -144,23 +144,24 @@ def gen_reg_tables(subsection, group_fields):
 
 def main():
     # find all "*.fpga.yaml" files
-    if args.fpga:
-        fpga_libs = FPGALibrary(os.path.expandvars('$ARGS_WORK'), use_qsys_base_addr=args.useqsys).library
+    if args.fpga_name:
+        fpga_lib = FPGALibrary(os.path.expandvars('$ARGS_WORK'), use_avalon_base_addr=args.use_avalon_base_addr)
     
     # find all "*.peripheral.yaml" files
-    if args.peripheral:
-        periph_libs = PeripheralLibrary(os.path.expandvars('$ARGS_WORK')).library
+    if args.peripheral_name:
+        periph_lib = PeripheralLibrary(os.path.expandvars('$ARGS_WORK'))
       
     try:
-        if args.fpga in fpga_libs:
-            doc = FPGADocumentation(args.board, args.fpga, fpga_libs[args.fpga])
+        if args.fpga_name:
+            doc = FPGADocumentation(args.board_name, args.fpga_name, fpga_lib.get_fpga(args.fpga_name))
             doc.fill()
             doc.make_pdf()
             del doc
+            logger.info('Made documentation for "%s"', args.fpga_name)
             time.sleep(0.5)
 
-        for peripheralname in args.peripheral:
-            doc = PeripheralDocumentation(peripheralname, periph_libs[peripheralname])
+        if args.peripheral_name:
+            doc = PeripheralDocumentation(peripheralname, periph_lib.find_peripheral(args.peripheral_name))
             doc.fill()
             doc.make_pdf()
             del doc
@@ -640,29 +641,32 @@ class PeripheralDocumentation(object):
 
 
 if __name__ == "__main__":
-    # setup first log system before importing other user libraries
-    PROGRAM_NAME = __file__.split('/')[-1].split('.')[0]
-    unit_logger.set_logfile_name(name=PROGRAM_NAME)
-    unit_logger.set_file_log_level('DEBUG')
-
     # Parse command line arguments
     parser = argparse.ArgumentParser(description="System and peripheral config command line parser arguments")
-    parser.add_argument('-b', '--board', required=True, type=str, help="board name, [unb2b, ...]")
-    parser.add_argument('-f', '--fpga', type=str, help="fpga system name")
-    parser.add_argument('-u', '--useqsys', action='store_true', default=False, help="use qsys for base addresses")
-    parser.add_argument('-p', '--peripheral', nargs='*', default=[], help="peripheral names separated by spaces")
-    parser.add_argument('-v', '--verbosity', default='INFO', help="verbosity level can be [ERROR | WARNING | INFO | DEBUG]")
+    parser.add_argument('-b', '--board', dest='board_name', required=True, type=str, help="board name, [unb2b, ...]")
+    parser.add_argument('-f', '--fpga', dest='fpga_name', type=str, help="fpga system name")
+    parser.add_argument('-a', '--avalon', dest='use_avalon_base_addr', action='store_true', default=False, help="use avalon base addresses")
+    parser.add_argument('-p', '--peripheral', dest='peripheral_name', type=str, help="peripheral name")
+    parser.add_argument('-v', '--verbosity', default='INFO', help="stdout log level can be [ERROR | WARNING | INFO | DEBUG]")
     args = parser.parse_args()
 
-    unit_logger.set_stdout_log_level(args.verbosity)
+    # setup first log system before importing other user libraries
+    program_name = __file__.split('/')[-1].split('.')[0]
+    out_dir = os.path.join(os.getenv('ARGS_BUILD_DIR'), args.board_name, 'args', args.fpga_name, 'log')
+    my_logger = MyLogger(log_path=out_dir, file_name=program_name)
+    my_logger.set_file_log_level('DEBUG')
+    my_logger.set_stdout_log_level(args.verbosity)
+
+    logger = my_logger.get_logger()
     logger.debug("Used arguments: {}".format(args))
 
-    if not args.peripheral and not args.fpga:
+    if not args.peripheral_name and not args.fpga_name:
         parser.print_help()
         sys.exit(1)
-
     try:
         main()
+    except (ARGSNameError, ARGSModeError, ARGSYamlError):
+        handle_args_error(sys.exc_info()[0])
     except:
         logger.error('Program fault, reporting and cleanup')
         logger.error('Caught %s', str(sys.exc_info()[0]))
diff --git a/gen_fpgamap_py.py b/gen_fpgamap_py.py
index f1d41b76f867b07c44917c077363fc0b2ce6ff33..e20dac471ee917d7a95168ee6eade1a5af8e454c 100755
--- a/gen_fpgamap_py.py
+++ b/gen_fpgamap_py.py
@@ -20,6 +20,7 @@
 #
 #   Author           Date      Version comments
 #   John Matthews    Dec 2017  Original
+#   Pieter Donker    Mrt 2020  add logging
 #
 ###############################################################################
 
@@ -31,13 +32,11 @@ import sys
 import os
 import logging
 from argparse import ArgumentParser
+from args_logger import MyLogger
 from py_args_lib import FPGA, RAM, FIFO, Register, PeripheralLibrary, FPGALibrary, ceil_pow2
-# from common import ceil_pow2
 import pprint
 # import code
 
-# logging.basicConfig(stream=sys.stdout, level=logging.INFO)
-
 
 def genPython(fpga, boardName, fpgaName, readable):
     slavePorts = {}
@@ -170,18 +169,31 @@ if __name__ == '__main__':
     parser = ArgumentParser(description='ARGS tool script to generate fpgamap.py M&C Python client include file')
     parser.add_argument('-b', '--board', required=True, help='ARGS board_name, [unb2b, ...]')
     parser.add_argument('-f', '--fpga', required=True, help='ARGS fpga_name')
+    parser.add_argument('-a', '--avalon', action='store_true', default=False, help="use config file qsys/sopc for base addresses")
     parser.add_argument('-r', '--readable', action='store_true', help='Generate human readable map file')
+    parser.add_argument('-v', '--verbosity', default='INFO', help="stdout log level can be [ERROR | WARNING | INFO | DEBUG]")
     args = parser.parse_args()
 
     boardName = args.board
     fpgaName = args.fpga
+    useAvalon = args.avalon
     readable = args.readable
 
     libRootDir = os.path.expandvars('$ARGS_WORK')
 
+    # setup first log system before importing other user libraries
+    program_name = __file__.split('/')[-1].split('.')[0]
+    out_dir = os.path.join(os.getenv('ARGS_BUILD_DIR'), args.board, 'args', args.fpga, 'log')
+    my_logger = MyLogger(log_path=out_dir, file_name=program_name)
+    my_logger.set_file_log_level('DEBUG')
+    my_logger.set_stdout_log_level(args.verbosity)
+
+    logger = my_logger.get_logger()
+    logger.debug("Used arguments: {}".format(args))
+
     # Find and parse all *.fpga.yaml YAML files under libRootDir
     # For each FPGA file it extracts a list of the peripherals that are used by that FPGA
     # Here we select the FPGA YAML that matches up with the supplied fpga command line argument
-    fpga = FPGALibrary(root_dir=libRootDir).library[fpgaName]
+    fpga = FPGALibrary(root_dir=libRootDir, use_avalon_base_addr=useAvalon).library[fpgaName]
 
     genPython(fpga, boardName, fpgaName, readable)
diff --git a/py_args_lib/__init__.py b/py_args_lib/__init__.py
index 2df1151ca6e6dda5ac87fa52b4f3d2903caa045b..fd6fd7c3dbc9ad725b9c583eb66e899742ffe1de 100644
--- a/py_args_lib/__init__.py
+++ b/py_args_lib/__init__.py
@@ -8,11 +8,6 @@ cwd = __file__[:__file__.rfind('/')]
 # cwd = os.path.dirname(os.path.realpath(__file__))
 sys.path.append(cwd)
 
-from unit_logger import UnitLogger
-
-unit_logger = UnitLogger(os.path.join(cwd, '../log'))
-logger = unit_logger.logger
-
 from peripheral import PeripheralLibrary, Peripheral
 from fpga import FPGA, FPGALibrary
 from peripheral_lib import *
diff --git a/py_args_lib/fpga.py b/py_args_lib/fpga.py
index 5930e478b04c5f38ceb90d7aec1b728806734264..a627401ce11349ac734cff6f9875ce14e0ef16c4 100644
--- a/py_args_lib/fpga.py
+++ b/py_args_lib/fpga.py
@@ -26,6 +26,7 @@
 ###############################################################################
 
 import os
+import sys
 import copy
 import logging
 import yaml
@@ -41,15 +42,15 @@ logger = logging.getLogger('main.fpga')
 class FPGA(object):
     """ An FPGA consist of a set of one or more Peripherals.
     """
-    def __init__(self, file_path_name=None, periph_lib=None, use_qsys_base_addr=None):
+    def __init__(self, file_path_name=None, periph_lib=None, use_avalon_base_addr=None):
         self.file_path_name  = file_path_name
         self.root_dir        = os.environ['RADIOHDL_WORK']
         if periph_lib is None:
-            self.peri_lib        = PeripheralLibrary(self.root_dir)
+            self.peri_lib = PeripheralLibrary(self.root_dir)
         else:
             self.peri_lib = periph_lib
-        
-        self.use_qsys_base_addr = False if use_qsys_base_addr is None else use_qsys_base_addr
+
+        self.use_avalon_base_addr = False if use_avalon_base_addr is None else use_avalon_base_addr
 
         self.fpga_name = ""
         self.fpga_description = ""
@@ -78,7 +79,7 @@ class FPGA(object):
     def read_fpga_file(self, file_path_name):
         """Read the FPGA information from the file_path_name file."""
 
-        logger.info("Load FPGA from '%s'", file_path_name)
+        logger.debug("Load FPGA from '%s'", file_path_name)
         fpga_config = yaml.load(open(file_path_name, 'r'))
 
         self.valid_file_type = True
@@ -181,10 +182,10 @@ class FPGA(object):
         for peripheral_config in self.peripherals.values():
             peripheral_config.eval_peripheral()
 
-        if self.use_qsys_base_addr is True:
-            logger.info("Use qsys base addresses for the slaves")
-            if self.read_qsys_address_map() == -1:
-                logger.info("Now trying auto_create")
+        if self.use_avalon_base_addr is True:
+            logger.debug("Use qsys/sopc base addresses for the slaves")
+            if self.read_avalon_address_map() == -1:
+                logger.debug("Now trying auto_create")
                 self.create_address_map()
         else:
             self.create_address_map()
@@ -211,30 +212,44 @@ class FPGA(object):
         logger.debug("_eval(%s) returns eval(%s) = %s", str(val), _val, str(result))
         return result
 
-    def read_qsys_address_map(self):
+    def read_avalon_address_map(self):
         """
         read qsys file, and use base_addresses
         """
         filename = os.path.basename(self.file_path_name)
         dirname  = os.path.dirname(self.file_path_name)
 
+        if '_sopc' in self.fpga_name:
+            filename = 'sopc_{}.sopc'.format(self.fpga_name.replace('_sopc', ''))
+            logger.debug('sopc system, config filename = "%s"', filename)
+        else:
+            filename = 'qsys_{}.qsys'.format(self.fpga_name.replace('_qsys', ''))
+            logger.debug('qsys system, config filename = "%s"', filename)
 
-        # TODO find qsys file, if it is a revisions it can be 1 dir up
-        qsys_filename = 'qsys_{}.qsys'.format(self.fpga_name)
-        qsys_file_path_name = os.path.join(dirname, '..', 'quartus', qsys_filename)
-
-        # TODO: used for test
-        # qsys_file_path_name = '/home/donker/git/hdl/boards/uniboard1/designs/unb1_minimal/quartus/qsys_unb1_minimal.qsys'
-        
         try:
-            with open(qsys_file_path_name, 'r') as fd:
-                data = fd.read()
-        except:
-            logger.error("qsys file not found")
+            file_path_name = os.path.join(dirname, 'quartus', filename)
+            os.stat(file_path_name)
+        except FileNotFoundError:
+            logger.debug('"%s" does not exist.', file_path_name)
+            file_path_name = None
+        
+        if file_path_name is None:  # must be a revision, try 2 dirs up.
+            try:
+                file_path_name = os.path.join(dirname, '../..', 'quartus', filename)
+                os.stat(file_path_name)
+            except FileNotFoundError:
+                logger.debug('"%s" does not exist.', file_path_name)
+                file_path_name = None
+
+        if file_path_name is None:
+            logger.error('file "%s" not found', filename)
             return -1
 
-        qsys_base_addr = {}
-        
+        with open(file_path_name, 'r') as fd:
+            data = fd.read()
+
+        avalon_base_addr = {}
+
         p1 = 0
         while p1 > -1:
             p1 = data.find('kind="avalon"', p1)
@@ -249,35 +264,35 @@ class FPGA(object):
                 p1 = p2
                 logger.debug("%27s %s", name, addr)
                 if name.endswith('.mem'):
-                    qsys_base_addr[name.replace('.mem', '')] = int(addr, 16)
+                    avalon_base_addr[name.replace('.mem', '')] = int(addr, 16)
                 elif name.endswith('.s1'):
-                    qsys_base_addr[name.replace('.s1', '')] = int(addr, 16)
+                    avalon_base_addr[name.replace('.s1', '')] = int(addr, 16)
                 elif '.mms' in name:
-                    qsys_base_addr[name.replace('.mms', '')] = int(addr, 16)
+                    avalon_base_addr[name.replace('.mms', '')] = int(addr, 16)
                 else:
-                    qsys_base_addr[name] = int(addr, 16)
+                    avalon_base_addr[name] = int(addr, 16)
 
-        print(qsys_base_addr)
+        #print(avalon_base_addr)
 
         for peripheral in self.peripherals.values():
             p_nam = peripheral.name()
             if len(p_nam) > 20:
                 p_nam = p_nam[0:20]
             pad = ' ' * (21-len(peripheral.name()))
-            
+
             #logger.debug('** PERIPHERAL: %21s base_addr=0x%08x [occupied size=0x%04x]',
             #             p_nam, lowest_free_addr, peripheral.reg_len)  # TODO
-            
+
             for periph_num in range(peripheral.number_of_peripherals()):
                 for slave in peripheral.slaves:
-                    
+
                     base_addr = -1
                     if slave.user_defined_name():
                         try:
-                            base_addr = qsys_base_addr[slave.user_defined_name()]
+                            base_addr = avalon_base_addr[slave.user_defined_name()]
                         except:
                             pass
-                    
+
                     addr_map_name = [peripheral.name(), slave.name()]
 
                     if isinstance(slave, Register) and not getattr(slave, 'isIP', False):
@@ -289,11 +304,11 @@ class FPGA(object):
                         if peripheral.number_of_peripherals() > 1:
                             addr_map_name.append(str(periph_num))
                         slave_port_name = '_'.join(addr_map_name)
-                        
+
                         self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': 'LITE',
                                                              'port_index': self.nof_lite, 'peripheral': peripheral,
                                                              'periph_num': periph_num, 'slave': slave}
-                        logger.info("Register for %s has span 0x%x", peripheral.name(), slave_span)
+                        logger.debug("Register for %s has span 0x%x", peripheral.name(), slave_span)
 
                     elif isinstance(slave, Register) and getattr(slave, 'isIP', False):
                         addr_map_name.append('regip')
@@ -305,13 +320,13 @@ class FPGA(object):
                         self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': slave.protocol,
                                                              'port_index': eval("self.nof_{}".format(slave.protocol.lower())),
                                                              'peripheral': peripheral, 'periph_num': periph_num, 'slave': slave}
-                    
+
                     elif isinstance(slave, RAM):
                         addr_map_name.append('ram')
 
                         size_in_bytes = np.ceil(slave.width()/8)*slave.address_length()*ceil_pow2(slave.number_of_slaves())
                         slave_span = ceil_pow2(max(size_in_bytes, 4096))
-                        logger.info("Slave %s has span 0x%x", peripheral.name() + '_' + slave.name() , slave_span)
+                        logger.debug("Slave %s has span 0x%x", peripheral.name() + '_' + slave.name() , slave_span)
 
                         if peripheral.number_of_peripherals() > 1:
                             addr_map_name.append(str(periph_num))
@@ -343,7 +358,7 @@ class FPGA(object):
             Configurable ranges are 4k, 8k, 16k, 32k, 64k i.e. 2^(12,13,14,15,16)
             There is a maximum of one register group per peripheral
         """
-        logger.debug("[fpga.py] create_address_map('{:s}')".format(self.fpga_name))
+        logger.debug("create_address_map('{:s}')".format(self.fpga_name))
 
         # Largest peripheral will determine spacing between peripheral base addresses
         largest_addr_range = 4096  # minimal allowed address-decode spacing with Xilinx interconnect
@@ -356,13 +371,13 @@ class FPGA(object):
         for peripheral in self.peripherals.values():
             # Ensure peripheral base is aligned to address decode
             lowest_free_addr = int(np.ceil(lowest_free_addr / peripheral_spacing) * peripheral_spacing)
-            
+
             p_nam = peripheral.name()
             if len(p_nam) > 20:
                 p_nam = p_nam[0:20]
             pad = ' ' * (21-len(peripheral.name()))
             logger.debug('** PERIPHERAL: {:21s} base_addr=0x{:08x} [occupied size=0x{:04x}]'.format(p_nam, lowest_free_addr, peripheral.reg_len))
-            
+
             # assigned_reg = False
             # _nof_regs =  sum([isinstance(slave, Register) for slave in peripheral.slaves])
             # _minus_regs = _nof_regs - 1 if _nof_regs > 0 else 0
@@ -381,16 +396,16 @@ class FPGA(object):
                             lowest_free_addr = register_base + (slave.base_address() if not any(slave.rams) else slave.rams[0].base_address())
                         ram_span = slave.base_address() - slave.rams[0].base_address() if any(slave.rams) else 0
                         slave_span = slave.address_length()*slave.number_of_slaves()+ram_span
-                        
+
                         _name_list = [peripheral.name(), slave.name(), slave_type]
                         if peripheral.number_of_peripherals() > 1:
                             _name_list.append(str(periph_num))
                         slave_port_name = '_'.join(_name_list)
-                        
+
                         self.address_map[slave_port_name] = {'base': lowest_free_addr, 'span': slave_span, 'type': 'LITE',
                                                              'port_index': self.nof_lite, 'peripheral': peripheral,
                                                              'periph_num': periph_num, 'slave': slave}
-                        logger.info("Register for %s has span 0x%x", peripheral.name(), slave_span)
+                        logger.debug("Register for %s has span 0x%x", peripheral.name(), slave_span)
                         lowest_free_addr = lowest_free_addr + int(slave_span)
                         self.nof_lite = self.nof_lite + 1
                         assigned_reg = True
@@ -399,7 +414,7 @@ class FPGA(object):
                         slave_type = 'regip'
                         slave_span = ceil_pow2(max(slave.address_length()*slave.number_of_slaves(), 4096))  # slave.address_length()*slave.number_of_slaves()#
                         lowest_free_addr = int(np.ceil(lowest_free_addr/slave_span)*slave_span)
-                        
+
                         _name_list = [peripheral.name(), slave.name(), slave_type]
                         slave_port_name = '_'.join(_name_list)
 
@@ -416,10 +431,10 @@ class FPGA(object):
                         slave_type = 'ram'
                         size_in_bytes = np.ceil(slave.width()/8)*slave.address_length()*ceil_pow2(slave.number_of_slaves())
                         slave_span = ceil_pow2(max(size_in_bytes, 4096))
-                        logger.info("Slave %s has span 0x%x", peripheral.name() + '_' + slave.name() , slave_span)
+                        logger.debug("Slave %s has span 0x%x", peripheral.name() + '_' + slave.name() , slave_span)
                         # slave_name = slave.name() + ('_{}'.format(slave_no) if slave.number_of_slaves() >1 else '')
                         lowest_free_addr = int(np.ceil(lowest_free_addr/slave_span)*slave_span)
-                        
+
                         _name_list = [peripheral.name(), slave.name(), slave_type]
                         if peripheral.number_of_peripherals() > 1:
                             _name_list.append(str(periph_num))
@@ -437,7 +452,7 @@ class FPGA(object):
                         slave_span = ceil_pow2(max(size_in_bytes, 4096))
                         for i in range(slave.number_of_slaves()):
                             lowest_free_addr = int(np.ceil(lowest_free_addr/slave_span)*slave_span)
-                            
+
                             _name_list = [peripheral.name(), slave.name(), slave_type]
                             if peripheral.number_of_peripherals() > 1:
                                 _name_list.append(str(periph_num))
@@ -456,22 +471,22 @@ class FPGA(object):
     def show_overview(self):
         """ print FPGA overview
         """
-        logger.info("----------------------")
-        logger.info(" FPGA OVERVIEW ")
-        logger.info("----------------------")
-        logger.info("FPGA name '%s'", self.fpga_name)
-        logger.info("- FPGA parameters:")
+        logger.debug("----------------------")
+        logger.debug(" FPGA OVERVIEW ")
+        logger.debug("----------------------")
+        logger.debug("FPGA name '%s'", self.fpga_name)
+        logger.debug("- FPGA parameters:")
         for key, val in iter(self.parameters.items()):
             if isinstance(val, dict):
                 for _key, _val in val.items():
-                    logger.info("  %-25s  %s", "{}.{}".format(key, _key), str(_val))
+                    logger.debug("  %-25s  %s", "{}.{}".format(key, _key), str(_val))
             else:
-                logger.info("  %-20s  %s", key, str(val))
-        logger.info("- FPGA Address Map:")
+                logger.debug("  %-20s  %s", key, str(val))
+        logger.debug("- FPGA Address Map:")
         for slave_name, attributes in self.address_map.items():
-            logger.info("  %-30s 0x%x, range %dkB at port MSTR_%s[%d]",
+            logger.debug("  %-30s 0x%x, range %dkB at port MSTR_%s[%d]",
                         slave_name, attributes['base'], attributes['span']/1024, attributes['type'], attributes['port_index'])
-        logger.info("- Peripherals:")
+        logger.debug("- Peripherals:")
         for peripheral in sorted(self.peripherals):
             self.peripherals[peripheral].show_overview(header=False)
 
@@ -481,9 +496,9 @@ class FPGALibrary(object):
     List of all information for FPGA config files in the root dir, intended for use in hdl_config.py
     """
 
-    def __init__(self, root_dir=None, use_qsys_base_addr=None):
+    def __init__(self, root_dir=None, use_avalon_base_addr=None):
         self.root_dir = root_dir
-        self.use_qsys_base_addr = use_qsys_base_addr
+        self.use_avalon_base_addr = use_avalon_base_addr
         self.file_extension = ".fpga.yaml"
         self.library = {}
         self.nof_peripherals = 0
@@ -500,16 +515,22 @@ class FPGALibrary(object):
                     try :
                         # try to read yaml file
                         library_config = yaml.load(open(os.path.join(root, name), 'r'))
-                    except:
-                        logger.error('Failed parsing YAML in {}. Check file for YAML syntax errors'.format(name))
-                        logger.error('ERROR:\n' + sys.exc_info()[1])
-                        sys.exit()
+                    except yaml.YAMLError as exc:
+                        logger.error('Failed parsing YAML file "{}". Check file for YAML syntax errors'.format(name))
+                        if hasattr(exc, 'problem_mark'):
+                            mark = exc.problem_mark
+                            logger.error("Error position: (%s:%s)" % (mark.line+1, mark.column+1))
+                        #logger.error('ERROR:\n' + sys.exc_info()[1])
+                        raise ARGSYamlError
+                        continue
+                        #sys.exit()
+
                     if not isinstance(library_config, dict):
                         logger.warning('File %s is not readable as a dictionary, it will not be'
                                        ' included in the FPGA library of peripherals', name)
                         continue
                     lib_name = name.replace(self.file_extension, '')
-                    logger.info("Found fpga.yaml file %s", lib_name)
+                    logger.debug("Found fpga.yaml file %s", lib_name)
                     if lib_name in self.library:
                         logger.warning("%s library already exists in FPGALibrary, being overwritten", lib_name)
                     # looks a valid library
@@ -523,17 +544,27 @@ class FPGALibrary(object):
            Read the information from all FPGA files that were found in the root_dir tree
         """
 
-        self.fpgas = {}
+        #self.fpgas = {}
         periph_lib = PeripheralLibrary(self.root_dir)
         if file_path_names is None:
             file_path_names = [lib_dict['file_path_name'] for lib_dict in self.library.values()]
         for fpn in file_path_names:
-            logger.info("Creating ARGS FPGA object from {}".format(fpn))
+            logger.debug("Creating ARGS FPGA object from {}".format(fpn))
             tic = time.time()
-            fpga = FPGA(fpn, periph_lib=periph_lib, use_qsys_base_addr=self.use_qsys_base_addr)
+            fpga = FPGA(fpn, periph_lib=periph_lib, use_avalon_base_addr=self.use_avalon_base_addr)
             toc = time.time()
             logger.debug("fpga creation for %s took %.4f seconds", fpn, toc-tic)
             fpga.show_overview()
             self.library[fpga.fpga_name].update({'fpga': fpga})
             for lib, peripheral in fpga.peripherals.items():
                 self.library[fpga.fpga_name]['peripherals'].update({lib: peripheral})
+
+    def get_fpga(self, fpga_name):
+        """
+        return fpga system information if found else None
+        """
+        try:
+            return self.library[fpga_name]
+        except KeyError:
+            logger.error("fpga %s not found.", fpga_name)
+        raise ARGSNameError
diff --git a/py_args_lib/peripheral.py b/py_args_lib/peripheral.py
index 9bd578865510c6de3f9457d88ad408cbc44ac302..cc411fa9908cd28107d5fc9e9d38eb9f34645f54 100644
--- a/py_args_lib/peripheral.py
+++ b/py_args_lib/peripheral.py
@@ -662,22 +662,22 @@ class Peripheral(BaseObject):
         """ print system overview
         """
         if header:
-            logger.info("--------------------")
-            logger.info("PERIPHERAL OVERVIEW:")
-            logger.info("--------------------")
+            logger.debug("--------------------")
+            logger.debug("PERIPHERAL OVERVIEW:")
+            logger.debug("--------------------")
 
-        logger.info("Peripheral name:     %s", self.name())
+        logger.debug("Peripheral name:     %s", self.name())
         if self.number_of_peripherals() > 1:
-            logger.info("  number_of_peripheral_instances=%d", self.number_of_peripherals())
-        logger.info("  RAM and REG:")
+            logger.debug("  number_of_peripheral_instances=%d", self.number_of_peripherals())
+        logger.debug("  RAM and REG:")
         # for ram in self.rams.values():
         for ram in self.slaves:
             if not isinstance(ram, RAM):
                 continue
-            logger.info("    %-20s:", ram.name())
+            logger.debug("    %-20s:", ram.name())
             if ram.number_of_slaves() > 1:
-                logger.info("      number_of_slaves=%-3s", str(ram.number_of_slaves()))
-            logger.info("      fields:")
+                logger.debug("      number_of_slaves=%-3s", str(ram.number_of_slaves()))
+            logger.debug("      fields:")
             # first make list with address_offset as first item to print later fields orderd on address.
             fields = []
             # for field_val in ram.fields.values():
@@ -685,10 +685,10 @@ class Peripheral(BaseObject):
 
             for _offset, _name in sorted(fields):
                 field = ram
-                logger.info("        %-20s:", _name)
+                logger.debug("        %-20s:", _name)
                 # if field.number_of_fields() > 1:
-                #    logger.info("          number_of_fields=%s", str(field.number_of_fields()))
-                logger.info("          width=%-2s       number_of_fields=%s",
+                #    logger.debug("          number_of_fields=%s", str(field.number_of_fields()))
+                logger.debug("          width=%-2s       number_of_fields=%s",
                             str(field.width()),
                             str(field.number_of_fields()))
 
@@ -697,33 +697,33 @@ class Peripheral(BaseObject):
             if not isinstance(reg, Register):
                 continue
             # logger.debug("reg_fields=%s", str(reg.fields))
-            logger.info("    %-20s:", reg.name())
+            logger.debug("    %-20s:", reg.name())
             if reg.number_of_slaves() > 1:
-                logger.info("      number_of_slaves=%-3s", str(reg.number_of_slaves()))
-            logger.info("      address_length=%-3s", str(reg.address_length()))
-            logger.info("      fields:")
+                logger.debug("      number_of_slaves=%-3s", str(reg.number_of_slaves()))
+            logger.debug("      address_length=%-3s", str(reg.address_length()))
+            logger.debug("      fields:")
 
             for field in reg.fields:
 
-                logger.info("        %-20s", field.name())
+                logger.debug("        %-20s", field.name())
                 # if field.number_of_fields() > 1:
-                #    logger.info("          number_of_fields=%s", str(field.number_of_fields()))
+                #    logger.debug("          number_of_fields=%s", str(field.number_of_fields()))
 
-                logger.info("          width=%-2s       address_offset=0x%02x  access_mode=%-4s  reset_value=%-4s  radix=%s",
+                logger.debug("          width=%-2s       address_offset=0x%02x  access_mode=%-4s  reset_value=%-4s  radix=%s",
                             str(field.width()), field.address_offset(),
                             field.access_mode(), str(field.reset_value()),
                             field.radix())
-                logger.info("          bit_offset=%-2s  number_of_fields=%-4s  side_effect=%-4s  software_value=%-4s",
+                logger.debug("          bit_offset=%-2s  number_of_fields=%-4s  side_effect=%-4s  software_value=%-4s",
                             str(field.bit_offset()), str(field.number_of_fields()),
                             field.side_effect(), str(field.software_value()))
 
-        logger.info("  parameters:")
+        logger.debug("  parameters:")
         for param_key, param_val in self._parameters.items():
             if isinstance(param_val, dict):
                 for _key, _val in param_val.items():
-                    logger.info("      %-25s  %s", "{}.{}".format(param_key, _key), str(_val))
+                    logger.debug("      %-25s  %s", "{}.{}".format(param_key, _key), str(_val))
             else:
-                logger.info("      %-20s  %s", param_key, str(param_val))
+                logger.debug("      %-20s  %s", param_key, str(param_val))
 
 
 class PeripheralLibrary(object):
@@ -736,7 +736,7 @@ class PeripheralLibrary(object):
 
         # all peripheral files have the same double file extension ".peripheral.yaml"
         self.file_extension  = file_extension
-        self.hdl_library_namerary = collections.OrderedDict()
+        self.library = collections.OrderedDict()
         self.nof_peripherals = 0  # number of peripherals
 
         exclude = set([path_string(os.path.expandvars('$RADIOHDL_BUILD_DIR'))])
@@ -750,11 +750,14 @@ class PeripheralLibrary(object):
                     if self.file_extension in name and name[0] != '.':
                         try :
                             library_config = yaml.load(open(os.path.join(root, name), 'r'))
-                        except:
-                            logger.error('Failed parsing YAML in %s. Check file for YAML syntax errors', name)
-                            print('\nERROR:\n')
-                            print(sys.exc_info()[1])
-                            sys.exit()
+                        except yaml.YAMLError as exc:
+                            logger.error('Failed parsing YAML file "{}". Check file for YAML syntax errors'.format(name))
+                            if hasattr(exc, 'problem_mark'):
+                                mark = exc.problem_mark
+                                logger.error("Error position: (%s:%s)" % (mark.line+1, mark.column+1))
+                            raise ARGSYamlError
+                            continue
+
                         if not isinstance(library_config, dict):
                             logger.warning('File %s is not readable as a dictionary, it will not be'
                                            ' included in the RadioHDL library of ARGS peripherals',
@@ -775,11 +778,11 @@ class PeripheralLibrary(object):
                             logger.error("File %s has mismatching filename '%s' and hdl_library_name '%s'",
                                          os.path.join(root, name), name.split('.')[0], lib_name)
                             sys.exit()
-                        if self.hdl_library_namerary.get(lib_name, None) is None:  # check peripheral library name is unique
-                            self.hdl_library_namerary.update({lib_name: {'file_path': root, 'file_path_name': os.path.join(root, name), 'peripherals': collections.OrderedDict(), 'description': library_config.get('hdl_library_description', "")}})
+                        if self.library.get(lib_name, None) is None:  # check peripheral library name is unique
+                            self.library.update({lib_name: {'file_path': root, 'file_path_name': os.path.join(root, name), 'peripherals': collections.OrderedDict(), 'description': library_config.get('hdl_library_description', "")}})
                         else :
                             logger.error("More than one instance of args peripheral library '%s' found under %s", lib_name, root_dir)
-                            logger.error("\nConflicting files:\n\t%s\n\t%s", self.hdl_library_namerary[lib_name]['file_path_name'], os.path.join(root, name))
+                            logger.error("\nConflicting files:\n\t%s\n\t%s", self.library[lib_name]['file_path_name'], os.path.join(root, name))
                             sys.exit()
 
             # list of peripheral configurations that are read from the available peripheral files
@@ -790,9 +793,9 @@ class PeripheralLibrary(object):
         self.peripherals = {}
         if file_path_names is None:
             # file_path_names = self.file_path_names
-            file_path_names = [lib_dict['file_path_name'] for lib_dict in self.hdl_library_namerary.values()]
+            file_path_names = [lib_dict['file_path_name'] for lib_dict in self.library.values()]
         for fpn in file_path_names:
-            logger.info("Load peripheral(s) from '%s'", fpn)
+            logger.debug("Load peripheral(s) from '%s'", fpn)
             library_config = yaml.load(open(fpn, 'r'))
             lib = library_config['hdl_library_name']
             for peripheral_config in library_config['peripherals']:
@@ -802,8 +805,8 @@ class PeripheralLibrary(object):
                     logger.error("Invalid peripheral_name '%s' in %s.peripheral.yaml",
                                  peripheral_config['peripheral_name'], lib)
                     sys.exit()
-                logger.info("  read peripheral '%s'" % peripheral.component_name())
-                self.hdl_library_namerary[lib]['peripherals'].update({peripheral.component_name(): peripheral})
+                logger.debug("  read peripheral '%s'" % peripheral.component_name())
+                self.library[lib]['peripherals'].update({peripheral.component_name(): peripheral})
                 self.nof_peripherals = self.nof_peripherals + 1
         # self.nof_peripherals = len(self.peripherals)  # number of peripherals
         return
@@ -813,35 +816,36 @@ class PeripheralLibrary(object):
         matching_libs = []
         count = 0
         if peripheral_library is not None:
-            if self.hdl_library_namerary.get(peripheral_library, None) is not None:
-                logger.info("Peripheral %s found under library %s", periph_name, peripheral_library)
-                return self.hdl_library_namerary[peripheral_library]['peripherals'].get(periph_name, None)
+            if peripheral_library in self.library and periph_name in self.library[peripheral_library]['peripherals']:
+                logger.debug("Peripheral %s found under library %s", periph_name, peripheral_library)
+                return self.library[peripheral_library]['peripherals'][periph_name]
             else :
                 logger.error("No peripheral library '%s' found under %s", peripheral_library, self.root_dir)
                 sys.exit()
                 return None
         else :
             # try to find unique instance of peripheral, failing that look for local
-            for lib in self.hdl_library_namerary.keys():
-                # periph_names.extend(list(self.hdl_library_namerary[lib]['peripherals'].keys()))
-                if periph_name in self.hdl_library_namerary[lib]['peripherals'].keys():
+            for lib in self.library:
+                # periph_names.extend(list(self.library[lib]['peripherals'].keys()))
+                if periph_name in self.library[lib]['peripherals']:
                     matching_libs.append(lib)
+            
             # matches = len([name for name in periph_names if name == periph_name])
             matches = len(matching_libs)
             if matches > 1:
                 if fpga_library is not None and fpga_library in matching_libs:
-                    logger.info("Multiple peripherals named %s found under libs %s, limiting peripheral search to local design library",
+                    logger.debug("Multiple peripherals named %s found under libs %s, limiting peripheral search to local design library",
                                 periph_name, ' '.join(matching_libs).upper(), fpga_library)
-                    return self.hdl_library_namerary[fpga_library]['peripherals'].get(periph_name, None)
+                    return self.library[fpga_library]['peripherals'].get(periph_name, None)
                 else:
                     print(' '.join(matching_libs))
                     logger.error("Multiple peripherals named '%s' found under libs %s, please specify peripheral library for peripheral %s in format '<lib_name>/%s'",
                                  periph_name, ' '.join(matching_libs).upper(), periph_name, periph_name)
                     sys.exit()
             elif matches == 1:
-                logger.info("Peripheral %s found under library %s",
+                logger.debug("Peripheral %s found under library %s",
                             periph_name, matching_libs[0])
-                return self.hdl_library_namerary[matching_libs[0]]['peripherals'][periph_name]
+                return self.library[matching_libs[0]]['peripherals'][periph_name]
             else:
                 logger.error("No matching peripherals for '%s' found under %s",
                              periph_name, self.root_dir)
@@ -850,14 +854,14 @@ class PeripheralLibrary(object):
             # return self.peripherals.get(name, None)
         # return peripheral_library.get(name, None)
         return None
-
+    
     def show_overview(self, header=True):
         """ print system overview
         """
         if header:
-            logger.info("---------------------")
-            logger.info("PERIPHERALS OVERVIEW:")
-            logger.info("---------------------")
+            logger.debug("---------------------")
+            logger.debug("PERIPHERALS OVERVIEW:")
+            logger.debug("---------------------")
 
         for peripheral in self.peripherals.values():
             peripheral.show_overview(header=False)
diff --git a/py_args_lib/peripheral_lib/args_errors.py b/py_args_lib/peripheral_lib/args_errors.py
index 4dcfdc980988b0ef595308135222e8594bb3cbe6..10e7a852c87ea8c8f88dffcf77c329a58c9c186f 100644
--- a/py_args_lib/peripheral_lib/args_errors.py
+++ b/py_args_lib/peripheral_lib/args_errors.py
@@ -1,6 +1,32 @@
 
+import logging
+
+logger = logging.getLogger('main.args_errors')
+
+
 class ARGSNameError(Exception):
     pass
-    
+   
+
 class ARGSModeError(Exception):
-    pass
\ No newline at end of file
+    pass
+
+
+class ARGSYamlError(Exception):
+    pass
+
+
+def handle_args_error(error):
+    # print(error)
+    if error == ARGSModeError:
+        logger.error("args mode error")
+        return
+    if error == ARGSNameError:
+        logger.error("args name error, wrong fpga or peripheral name")
+        return
+    if error == ARGSYamlError:
+        logger.error("args yaml error, wrong yaml file format")
+        return
+    
+    logger.error("Unknown error %s", error)
+    raise
diff --git a/py_args_lib/peripheral_lib/constants.py b/py_args_lib/peripheral_lib/constants.py
index 0476b9f5958542b5ef4498e4658f41e719a9b324..483b33682c46b68916ce63358b0f40db1b9b1df6 100644
--- a/py_args_lib/peripheral_lib/constants.py
+++ b/py_args_lib/peripheral_lib/constants.py
@@ -6,6 +6,7 @@
 
 c_byte_w      = 8
 c_word_w      = 32
+c_word_sz     = 4
 c_nof_complex = 2
 
 
diff --git a/py_args_lib/peripheral_lib/fifo.py b/py_args_lib/peripheral_lib/fifo.py
index 0cabf804fe824a3c10dc10e0417a2da89aec9d8b..82ef9e4451381c03aab2250e8a78503ea4732d2c 100644
--- a/py_args_lib/peripheral_lib/fifo.py
+++ b/py_args_lib/peripheral_lib/fifo.py
@@ -46,7 +46,7 @@ class FIFO(Field):
         self.name(name)
         self.description = ""
         # self.number_of_fifos = 1
-        self.fifo_fields = []
+        #self.fifo_fields = []
         if self.access_mode() not in VALID_FIFO_ACCESS_MODES:
             logger.error("'%s' not a valid access mode for slaves of type FIFO. Valid modes include %s", self.access_mode(), VALID_FIFO_ACCESS_MODES)
             raise ARGSModeError
diff --git a/uniboard_rom_system_info.py b/uniboard_rom_system_info.py
index 424fcb0e0fd8ffc69fba3d8a7128d98e0e56c953..bab353589fc4541c4030fdfcf70f35a6bcac3488 100755
--- a/uniboard_rom_system_info.py
+++ b/uniboard_rom_system_info.py
@@ -32,25 +32,25 @@ import argparse
 import traceback
 
 from math import ceil
-from py_args_lib import *
 
-import common as cm
+from args_logger import MyLogger
+from py_args_lib import *
 
 
 def main():
     """ generate rom_system reg and txt file """
-    for systemname in args.system:
-        system_filename = "./systems/{}.system.yaml".format(systemname)
-        qsys_filename   = "./{}.build.reg".format(systemname)
-        rom_system = RomSystem()
-        rom_system.read_system(filename=system_filename)
-        rom_system.read_qsys_reg(filename=qsys_filename)
-        rom_system.map_memory(use_qsys_base_address=args.qsys)
-        rom_system.generate_reg_file(write_file=True)  # make ROM_SYSTEM_INFO old style
-        rom_system.generate_mif_file(write_file=True)  # make ROM_SYSTEM_INFO old style
-        rom_system.generate_reg_file(write_file=True, version=2)  # make ROM_SYSTEM_INFO new style
-        rom_system.generate_mif_file(write_file=True, version=2)  # make ROM_SYSTEM_INFO new style
-        rom_system.generate_txt_file()  # write ROM_SYSTEM_INFO in readable format to a '.txt' file
+    
+    #system_filename = "./systems/{}.system.yaml".format(args.fpga)
+    qsys_filename   = "./{}.build.reg".format(args.fpga)
+    rom_system = RomSystem()
+    rom_system.read_fpga(fpga_name=args.fpga, use_qsys_addr=args.qsys)
+    rom_system.read_qsys_reg(filename=qsys_filename)
+    rom_system.map_memory(use_qsys_base_address=args.qsys)
+    rom_system.generate_reg_file(write_file=True)  # make ROM_SYSTEM_INFO old style
+    rom_system.generate_mif_file(write_file=True)  # make ROM_SYSTEM_INFO old style
+    rom_system.generate_reg_file(write_file=True, version=2)  # make ROM_SYSTEM_INFO new style
+    rom_system.generate_mif_file(write_file=True, version=2)  # make ROM_SYSTEM_INFO new style
+    rom_system.generate_txt_file()  # write ROM_SYSTEM_INFO in readable format to a '.txt' file
 
 
 class MemoryMapper(object):
@@ -79,32 +79,32 @@ class MemoryMapper(object):
 
         if base_address is not None:
             end_address = base_address + (size * nof_instances)
-            self.map.append({'name': name, 
-                             'base_address': base_address, 
-                             'end_address': end_address, 
-                             'size': size * cm.c_word_sz, 
-                             'nof_instances': nof_instances, 
+            self.map.append({'name': name,
+                             'base_address': base_address,
+                             'end_address': end_address,
+                             'size': size * c_word_sz,
+                             'nof_instances': nof_instances,
                              'hide_in_reg_file': hide_in_reg_file})
-            
-            logger.debug("add(): %08x, %08x, %d, %s, %d, %s", 
-                         base_address, end_address, (size * cm.c_word_sz), name, nof_instances, str(hide_in_reg_file))
+
+            logger.debug("add(): %08x, %08x, %d, %s, %d, %s",
+                         base_address, end_address, (size * c_word_sz), name, nof_instances, str(hide_in_reg_file))
         else:
             _base_address = self._find_start_addr(size*nof_instances)
 
             self.map.append({'name': name,
-                             'base_address': _base_address, 
-                             'end_address': _base_address+(size*nof_instances), 
-                             'size': size * cm.c_word_sz, 
-                             'nof_instances': nof_instances, 
+                             'base_address': _base_address,
+                             'end_address': _base_address+(size*nof_instances),
+                             'size': size * c_word_sz,
+                             'nof_instances': nof_instances,
                              'hide_in_reg_file': hide_in_reg_file})
             logger.debug("add(): %08x, %08x, %d, %s, %d, %s",
-                         _base_address, _base_address+(size*nof_instances), size * cm.c_word_sz, name, nof_instances, str(hide_in_reg_file))
+                         _base_address, _base_address+(size*nof_instances), size * c_word_sz, name, nof_instances, str(hide_in_reg_file))
 
     def _find_start_addr(self, size):
         """ look for the next address where the size (in bytes) will fit """
         _size = size  # now size in words
         #logger.debug("trying to fit size = %d", _size)
-        
+
         map = self.get_memory_map('base_address')
 
         map_size = len(map)
@@ -139,7 +139,7 @@ class MemoryMapper(object):
         for reg in self.map:
             sorted_list.append(reg[key])
         sorted_list.sort()
-        return sorted_list 
+        return sorted_list
 
     def get_memory_map(self, sort_on='name'):
         """ return sorted memory map on key
@@ -150,10 +150,10 @@ class MemoryMapper(object):
             for reg in self.map:
                 if reg[sort_on] == key:
                     map.append([reg['name'],
-                                reg['base_address'], 
-                                reg['end_address'], 
-                                reg['size'], 
-                                reg['nof_instances'], 
+                                reg['base_address'],
+                                reg['end_address'],
+                                reg['size'],
+                                reg['nof_instances'],
                                 reg['hide_in_reg_file']])
                     break
         return map
@@ -162,21 +162,18 @@ class RomSystem(object):
     """ RomSystem class """
     def __init__(self):
         self.filename        = None
-        self.system          = None
+        self.fpga          = None
         self.qsys_reg        = {}  # read in rom_system_info from old system key=name, val=[base, span]
         #self.address_list    = []
         self.rom_system_info = []
         self.word_size       = 32  # number of bits
         self.memory_mapper = MemoryMapper()
 
-    def read_system(self, filename):
-        """ read system configuration file """
-        self.filename = filename
-        system = System(self.filename)
-        if system.is_valid():
-            self.system = system
-            return True
-        return False
+    def read_fpga(self, fpga_name, use_qsys_addr):
+        """ read fpga configuration file """
+        self.fpga = FPGALibrary(os.path.expandvars('$ARGS_WORK'), use_qsys_base_addr=use_qsys_addr).library[fpga_name]['fpga']
+        return True
+        #return False
 
     def read_qsys_reg(self, filename=None):
         """ read *.reg file and get register order.
@@ -207,35 +204,43 @@ class RomSystem(object):
     def map_memory(self, use_qsys_base_address=False):
         """ calculate register offsets """
 
-        peripherals = self.system.peripherals
+        print("================")
+        print(self.fpga)
+
+        peripherals = self.fpga.peripherals
 
-        #print("================")
-        #print(peripherals.keys())
+        print("================")
+        print(peripherals.keys())
 
-        peripheral = peripherals['reg_system_info']
+        for peripheral_name in self.fpga.locked_base_addresses:
+            base_address = int(self.fpga.locked_base_addresses[peripheral_name])
+            size         = ceil_pow2(int(peripheral.get_slave('system').fields['field_reg_info'].number_of_fields()))  # TODO: if not available calculate real size
+
+
+        peripheral = peripherals['system']
         #print(peripheral.registers)
         base_address = int(peripheral.parameter('lock_base_address'))
-        size         = cm.ceil_pow2(int(peripheral.get_slave('reg_system_info').fields['field_reg_info'].number_of_fields()))  # TODO: if not available calculate real size
-        name = peripheral.get_slave('reg_system_info').user_defined_name()
+        size         = ceil_pow2(int(peripheral.get_slave('system').fields['field_reg_info'].number_of_fields()))  # TODO: if not available calculate real size
+        name = peripheral.get_slave('system').user_defined_name()
         if name is None:
-            name = "reg_system_info"     
+            name = "system"
         self.memory_mapper.add(name=name, size=size, nof_instances=1, base_address=base_address, hide_in_reg_file=True)
 
-        peripheral = peripherals['rom_system_info']
+        peripheral = peripherals['rom_system']
         base_address    = int(peripheral.parameter('lock_base_address'))
-        size            = cm.ceil_pow2(int(peripheral.get_slave('rom_system_info').fields['field_rom_info'].number_of_fields()))  # TODO: if not available calculate real size
-        name = peripheral.get_slave('rom_system_info').user_defined_name()
+        size            = ceil_pow2(int(peripheral.get_slave('rom_system_info').fields['field_rom_info'].number_of_fields()))  # TODO: if not available calculate real size
+        name = peripheral.get_slave('rom_system').user_defined_name()
         if name is None:
-            name = "rom_system_info"     
+            name = "rom_system"
         self.memory_mapper.add(name=name, size=size, nof_instances=1, base_address=base_address, hide_in_reg_file=True)
 
         size_info = []
         for peripheral in peripherals.values():
             #print(peripheral.component_name())
-            if peripheral.component_name() in ('reg_system_info', 'rom_system_info'):
+            if peripheral.component_name() in ('system', 'rom_system'):
                 #print('skip')
                 continue
-            
+
             nof_peri_inst = peripheral.number_of_peripherals()
             for rkey, rval in peripheral.rams.items():
                 n_addresses = rval.get_kv('address_length')
@@ -252,7 +257,7 @@ class RomSystem(object):
 
             for rkey, rval in peripheral.registers.items():
                 n_addresses = rval.get_kv('address_length')
-                
+
                 nof_inst = rval.number_of_slaves() * peripheral.number_of_peripherals()
                 if rval.user_defined_name() is not None:
                     _name = rval.user_defined_name()
@@ -300,11 +305,11 @@ class RomSystem(object):
             else:
                 base_address = None
             #print(name, base_address, qsys_size, size)
-            self.memory_mapper.add(name=name, 
-                              size=size, 
-                              nof_instances=nof_inst, 
-                              base_address=base_address, 
-                              hide_in_reg_file=hide_in_reg_file)
+            self.memory_mapper.add(name=name,
+                                   size=size,
+                                   nof_instances=nof_inst,
+                                   base_address=base_address,
+                                   hide_in_reg_file=hide_in_reg_file)
 
         #self.address_list = memory_mapper.get_memory_map()
 
@@ -338,9 +343,9 @@ class RomSystem(object):
 
         if write_file:
             if version is None:
-                filename = "{}.reg".format(self.system.fpga_name)
+                filename = "{}.reg".format(self.fpga.fpga_name)
             else:
-                filename = "{}_V{}.reg".format(self.system.fpga_name, version)
+                filename = "{}_V{}.reg".format(self.fpga.fpga_name, version)
             logger.debug("Write 'reg' file '%s'", filename)
             logger.debug("ROM_SYSTEM_INFO= %s", rom_system_info_str)
             with open(filename, 'w') as regfile:
@@ -372,9 +377,9 @@ class RomSystem(object):
 
         if write_file:
             if version is None:
-                filename = "{}.mif".format(self.system.fpga_name)
+                filename = "{}.mif".format(self.fpga.fpga_name)
             else:
-                filename = "{}_V{}.mif".format(self.system.fpga_name, version)
+                filename = "{}_V{}.mif".format(self.fpga.fpga_name, version)
             logger.debug("Write 'mif' file '%s'", filename)
 
             with open(filename, 'w') as miffile:
@@ -395,28 +400,31 @@ class RomSystem(object):
         for line in txt:
             logger.info(line)
 
-        filename = "{}.txt".format(self.system.fpga_name)
+        filename = "{}.txt".format(self.fpga.fpga_name)
         with open(filename, 'w') as f:
             f.write('\n'.join(txt))
 
 
 if __name__ == "__main__":
-    # setup first log system before importing other user libraries
-    PROGRAM_NAME = __file__.split('/')[-1].split('.')[0]
-    unit_logger.set_logfile_name(name=PROGRAM_NAME)
-    unit_logger.set_file_log_level('DEBUG')
-
     # Parse command line arguments
     parser = argparse.ArgumentParser(description="System and peripheral config command line parser arguments")
-    parser.add_argument('-s','--system', nargs='*', default=[], help="system names separated by spaces")
-    parser.add_argument('-q','--qsys', action='store_true', default=False, help="Use start address from QSYS reg file")
-    parser.add_argument('-v','--verbosity', default='INFO', help="verbosity = [INFO | DEBUG]")
+    parser.add_argument('-b', '--board', required=True, type=str, help="board name, [unb2b, ...]")
+    parser.add_argument('-f', '--fpga', type=str, help="fpga system name")
+    parser.add_argument('-q', '--qsys', action='store_true', default=False, help="Use start address from QSYS reg file")
+    parser.add_argument('-v', '--verbosity', default='INFO', help="stdout log level can be [ERROR | WARNING | INFO | DEBUG]")
     args = parser.parse_args()
 
-    if not args.system:
+    if not args.fpga:
         parser.print_help()
 
-    unit_logger.set_stdout_log_level(args.verbosity)
+    # setup first log system before importing other user libraries
+    program_name = __file__.split('/')[-1].split('.')[0]
+    out_dir = os.path.join(os.getenv('ARGS_BUILD_DIR'), args.board, 'args', args.fpga, 'log')
+    my_logger = MyLogger(log_path=out_dir, file_name=program_name)
+    my_logger.set_file_log_level('DEBUG')
+    my_logger.set_stdout_log_level(args.verbosity)
+
+    logger = my_logger.get_logger()
     logger.debug("Used arguments: {}".format(args))
 
     try: