diff --git a/args_demo.py b/args_demo.py index 1c5a6a28c8ebcaff995b88dd0e568d870463b5cc..2955bc20d17eaf2e9fa3d013e71f5e645fcb98d2 100644 --- a/args_demo.py +++ b/args_demo.py @@ -32,7 +32,7 @@ import yaml import traceback from subprocess import CalledProcessError from py_args_lib import * -#from py_args_lib import gen_slave +#from py_args_lib import gen_mm_port def main(): @@ -77,7 +77,7 @@ def generate_fw(filename): try: config = yaml.load(open(filename,"r")) peripherals = config['peripherals'] - # genSlave = gen_slave.Slave() + # genMMPort = gen_mm_port.MMPort() if '.fpga.yaml' in filename: # not supported yet print("not supported yet") @@ -86,12 +86,12 @@ def generate_fw(filename): periph['lib'] = config['hdl_library_name'] peripheral = Peripheral(periph) peripheral.eval_peripheral() - genSlave = gen_slave.Slave(peripheral) - genSlave.generate_regs(peripheral) + genMMPort = gen_mm_port.MMPort(peripheral) + genMMPort.generate_regs(peripheral) for key in peripheral.rams: - genSlave.generate_mem(peripheral.rams[key],'ram') + genMMPort.generate_mem(peripheral.rams[key],'ram') for key in peripheral.fifos: - genSlave.generate_mem(peripheral.fifos[key],'fifo') + genMMPort.generate_mem(peripheral.fifos[key],'fifo') except IOError: logger.error("config file '{}' does not exist" .format(filename)) except CalledProcessError: diff --git a/gen_bus.py b/gen_bus.py index 854d3d396a618e4e3d623d3ed563bc38c61edc55..764e34b9dba0b1b90b51015293ac6a88defa932f 100755 --- a/gen_bus.py +++ b/gen_bus.py @@ -35,7 +35,7 @@ import collections from py_args_lib import * from fpga import FPGA import numpy as np -from gen_slave import tab_aligned +from gen_mm_port import tab_aligned logger = logging.getLogger('main.gen_bus') @@ -59,17 +59,17 @@ class Bus(object): self.tmpl_bus_top = os.path.join(self.root_dir, 'templates/template_bus_top.vhd') self.tmpl_tcl = os.path.join(self.root_dir, 'templates/template_create_bd.tcl') self.bus_config = {'burst': ' 1', 'lock': '1', 'cache': '1', 'prot': '1', 'qos': '0', 'region': '0', 'wstrb': '1'} - self.lite_slaves = [] - self.full_slaves = [] - self.nof_slaves = self.fpga.nof_lite + self.fpga.nof_full + self.lite_mm_ports = [] + self.full_mm_ports = [] + self.nof_mm_ports = self.fpga.nof_lite + self.fpga.nof_full self.output_files = [] - self.vhd_replace_dict = {'<nof_lite_slaves>' : str(self.fpga.nof_lite), - '<nof_full_slaves>' : str(self.fpga.nof_full), + self.vhd_replace_dict = {'<nof_lite_mm_ports>' : str(self.fpga.nof_lite), + '<nof_full_mm_ports>' : str(self.fpga.nof_full), '<fpga_name>': self.fpga.fpga_name} - self.nof_interconnects = int(np.ceil((max(1, self.nof_slaves-1))/15)) + self.nof_interconnects = int(np.ceil((max(1, self.nof_mm_ports-1))/15)) self.indexes = self.calc_indexes() self.tcl_replace_dict = {'<fpga_name>': self.fpga.fpga_name, - '<nof_slaves>' : str(self.nof_slaves)} + '<nof_mm_ports>' : str(self.nof_mm_ports)} def gen_tcl(self): @@ -85,9 +85,9 @@ class Bus(object): if 'create_interconnects' in line: for i in range(self.nof_interconnects): lines.append(get_cmd(line).format(i)) - nof_slaves = 16 if i < (self.nof_interconnects - 1) else (self.nof_slaves - i*15) - lines.append(get_cmd(input[line_num+1]).replace('<i_nof_slaves>', str(nof_slaves))) - lines.extend([get_cmd(input[line_num+2]).replace('<i>', str(i).zfill(2)) for i in range(nof_slaves)]) + nof_mm_ports = 16 if i < (self.nof_interconnects - 1) else (self.nof_mm_ports - i*15) + lines.append(get_cmd(input[line_num+1]).replace('<i_nof_mm_ports>', str(nof_mm_ports))) + lines.extend([get_cmd(input[line_num+2]).replace('<i>', str(i).zfill(2)) for i in range(nof_mm_ports)]) lines.append(get_cmd(input[line_num+3]).format(i)) if 'connect_clock_pins' in line: for i in range(self.nof_interconnects): @@ -95,7 +95,7 @@ class Bus(object): lines.append(get_cmd(line).format(i, 0, 'S')) if i < (self.nof_interconnects-1): lines.append(get_cmd(line).format(i, 15, 'M')) - for i in range(self.nof_slaves): + for i in range(self.nof_mm_ports): lines.append(get_cmd(line).format(self.indexes[i][0], self.indexes[i][1], 'M')) if 'connect_reset_pins' in line: for i in range(self.nof_interconnects): @@ -103,30 +103,30 @@ class Bus(object): lines.append(get_cmd(line).format(i, 0, 'S')) if i < (self.nof_interconnects-1): lines.append(get_cmd(line).format(i, 15, 'M')) - for i in range(self.nof_slaves): + for i in range(self.nof_mm_ports): lines.append(get_cmd(line).format(self.indexes[i][0], self.indexes[i][1], 'M')) if 'create_master_ports' in line: last_port = -1 last_prot = None i = -1 - # for i, slave_attr in enumerate(self.fpga.address_map.values()): - for slave_attr in self.fpga.address_map.values(): - logger.debug('slave_attr=%s', str(slave_attr)) - if slave_attr['port_index'] == last_port and slave_attr['type'] == last_prot: + # for i, mm_port_attr in enumerate(self.fpga.address_map.values()): + for mm_port_attr in self.fpga.address_map.values(): + logger.debug('mm_port_attr=%s', str(mm_port_attr)) + if mm_port_attr['port_index'] == last_port and mm_port_attr['type'] == last_prot: continue # skip port indexes already dealt with i = i+1 - last_port = slave_attr['port_index'] - last_prot = slave_attr['type'] + last_port = mm_port_attr['port_index'] + last_prot = mm_port_attr['type'] logger.debug('indexes=%s', str(self.indexes)) if np.mod(i, 15) == 0 and self.indexes[i][1] == 0 and i != 0: lines.append(get_cmd(input[line_num+4])) # daisy chain interconnects lines.append(get_cmd(input[line_num+5]).format(self.indexes[i][0]-1, self.indexes[i][0])) lines.append(get_cmd(line).replace('<i>', str(i).zfill(2))) - _protocol = 'AXI4LITE' if slave_attr['type'] == 'LITE' else 'AXI4' + _protocol = 'AXI4LITE' if mm_port_attr['type'] == 'LITE' else 'AXI4' lines.append(get_cmd(input[line_num+1]).format(self.indexes[i][0], self.indexes[i][1], i)) _line = get_cmd(input[line_num+2]).replace('<protocol>', _protocol) lines.append(_line.replace('<i>', str(i).zfill(2))) - fifo_access = slave_attr.get('access', None) + fifo_access = mm_port_attr.get('access', None) if fifo_access is not None: _line = get_cmd(input[line_num+6]).replace('<access_mode>', 'READ' if fifo_access == 'RO' else 'WRITE') lines.append(_line.replace('<i>', str(i).zfill(2))) @@ -135,52 +135,52 @@ class Bus(object): last_port = -1 last_prot = None i = -1 - for slave_attr in self.fpga.address_map.values(): - if slave_attr['port_index'] == last_port and slave_attr['type'] == last_prot: + for mm_port_attr in self.fpga.address_map.values(): + if mm_port_attr['port_index'] == last_port and mm_port_attr['type'] == last_prot: continue i = i+1 - last_port = slave_attr['port_index'] - last_prot = slave_attr['type'] - if isinstance(slave_attr['slave'], Register): - if not getattr(slave_attr['slave'], 'isIP', False): - span = ceil_pow2(max(slave_attr['peripheral'].reg_len, 4096)) + last_port = mm_port_attr['port_index'] + last_prot = mm_port_attr['type'] + if isinstance(mm_port_attr['mm_port'], Register): + if not getattr(mm_port_attr['mm_port'], 'isIP', False): + span = ceil_pow2(max(mm_port_attr['peripheral'].reg_len, 4096)) else : - span = ceil_pow2(max(slave_attr['slave'].address_length(), 4096)) + span = ceil_pow2(max(mm_port_attr['mm_port'].address_length(), 4096)) else : - span = slave_attr['span'] + span = mm_port_attr['span'] _line = get_cmd(line).replace('<range>', '4') # 4k is minimum settable size for vivado lines.append(_line.replace('<i>', str(i).zfill(2))) if 'set_address_map' in line: last_port = -1 last_prot = None i = -1 - for slave_attr in self.fpga.address_map.values(): - if slave_attr['port_index'] == last_port and slave_attr['type'] == last_prot: + for mm_port_attr in self.fpga.address_map.values(): + if mm_port_attr['port_index'] == last_port and mm_port_attr['type'] == last_prot: continue i = i+1 - last_port = slave_attr['port_index'] - last_prot = slave_attr['type'] - _line = get_cmd(line).replace('<address>', "{:08x}".format(slave_attr['base'])) + last_port = mm_port_attr['port_index'] + last_prot = mm_port_attr['type'] + _line = get_cmd(line).replace('<address>', "{:08x}".format(mm_port_attr['base'])) lines.append(_line.replace('<i>', str(i).zfill(2))) if 'set_address_range' in line: last_port = -1 last_prot = None i = -1 - for slave_attr in self.fpga.address_map.values(): - if slave_attr['port_index'] == last_port and slave_attr['type'] == last_prot: + for mm_port_attr in self.fpga.address_map.values(): + if mm_port_attr['port_index'] == last_port and mm_port_attr['type'] == last_prot: continue i = i+1 - last_port = slave_attr['port_index'] - last_prot = slave_attr['type'] - if isinstance(slave_attr['slave'], Register): - if not getattr(slave_attr['slave'], 'isIP', False): - span = ceil_pow2(max(slave_attr['peripheral'].reg_len, 4096)) + last_port = mm_port_attr['port_index'] + last_prot = mm_port_attr['type'] + if isinstance(mm_port_attr['mm_port'], Register): + if not getattr(mm_port_attr['mm_port'], 'isIP', False): + span = ceil_pow2(max(mm_port_attr['peripheral'].reg_len, 4096)) else : - span = ceil_pow2(max(slave_attr['slave'].address_length(), 4096)) + span = ceil_pow2(max(mm_port_attr['mm_port'].address_length(), 4096)) else : - span = slave_attr['span'] + span = mm_port_attr['span'] lines.append('# interconnect[{}] <{}> base: 0x{:08x} span: 0x{:06x}\n'.format( - i, slave_attr['peripheral'].name(), slave_attr['base'], span)) + i, mm_port_attr['peripheral'].name(), mm_port_attr['base'], span)) _line = get_cmd(line).replace('<range>', str(int(span/1024))) lines.append(_line.replace('<i>', str(i).zfill(2))) @@ -188,9 +188,9 @@ class Bus(object): def gen_vhdl(self): lines = [] - slave_index = -1 + mm_port_index = -1 add_lines = [] -# if self.fpga.nof_full == 0 or self.nof_slaves == 1 : +# if self.fpga.nof_full == 0 or self.nof_mm_ports == 1 : # self.vhd_replace_dict.update({'<sla_in_vec>':'SLA_IN','<sla_out_vec>':'SLA_OUT','<(0)>':' '}) # else : # self.vhd_replace_dict.update({'<sla_in_vec>':'sla_in_vec','<sla_out_vec>':'sla_out_vec','<(0)>':'(0) '}) @@ -200,25 +200,25 @@ class Bus(object): # input = list(open(self.tmpl_mstr_port_cast,'r')) # last_port = -1 # last_prot = None -# for slave_port, slave_dict in self.fpga.address_map.items(): -# if slave_dict['port_index'] == last_port and slave_dict['type'] == last_prot: +# for mmport, mm_port_dict in self.fpga.address_map.items(): +# if mm_port_dict['port_index'] == last_port and mm_port_dict['type'] == last_prot: # continue -# last_port = slave_dict['port_index'] -# last_prot = slave_dict['type'] -# if self.fpga.nof_full == 0 or slave_dict['type'] == 'FULL': -# bad_tags = ['lock','last'] if slave_dict['type'] == 'LITE' else [] +# last_port = mm_port_dict['port_index'] +# last_prot = mm_port_dict['type'] +# if self.fpga.nof_full == 0 or mm_port_dict['type'] == 'FULL': +# bad_tags = ['lock','last'] if mm_port_dict['type'] == 'LITE' else [] # _input = [_line for _line in input if not any([bad_tag in _line for bad_tag in bad_tags])] -# add_lines = [line.format(slave_dict['type'],slave_dict['port_index'], slave_dict['type'].lower()) for line in _input] +# add_lines = [line.format(mm_port_dict['type'],mm_port_dict['port_index'], mm_port_dict['type'].lower()) for line in _input] # lines.extend(add_lines) if '<{master_interfaces}>' in line: last_port = -1 last_prot = None - for slave_port, slave_dict in self.fpga.address_map.items(): - if slave_dict['port_index'] == last_port and slave_dict['type'] == last_prot: + for mmport, mm_port_dict in self.fpga.address_map.items(): + if mm_port_dict['port_index'] == last_port and mm_port_dict['type'] == last_prot: continue - last_port = slave_dict['port_index'] - last_prot = slave_dict['type'] - slave_index = slave_index + 1 + last_port = mm_port_dict['port_index'] + last_prot = mm_port_dict['type'] + mm_port_index = mm_port_index + 1 if self.fpga.nof_full == 0 and self.fpga.nof_lite > 1 : zero_index = '(0)' # sig_out = 'mstr_out_lite_vec' @@ -227,16 +227,16 @@ class Bus(object): zero_index = '' # sig_out = 'MSTR_OUT_LITE' # sig_in = 'MSTR_IN_LITE' - template_file = self.tmpl_mstr_port_lite if slave_dict['type'] == 'LITE' else self.tmpl_mstr_port_full + template_file = self.tmpl_mstr_port_lite if mm_port_dict['type'] == 'LITE' else self.tmpl_mstr_port_full input = list(open(template_file, 'r')) -# # If we have more than 16 slaves, lite interfaces >= 15 use vector for std_logic +# # If we have more than 16 MM ports, lite interfaces >= 15 use vector for std_logic # if (self.fpga.nof_full + self.fpga.nof_lite) > 16: -# if slave_index > 14 and slave_dict['type'] == 'LITE': +# if mm_port_index > 14 and mm_port_dict['type'] == 'LITE': # zero_index = '(0)' - add_lines = [line.format(slave_index, slave_dict['port_index'], zero_index) for line in input] - if slave_index == (self.nof_slaves-1): # remove last comma to avoid vhdl syntax error + add_lines = [line.format(mm_port_index, mm_port_dict['port_index'], zero_index) for line in input] + if mm_port_index == (self.nof_mm_ports-1): # remove last comma to avoid vhdl syntax error for line_no, line in enumerate(add_lines[::-1]): if ',' in line and '--' not in line: add_lines[len(add_lines)-line_no-1] = line.replace(',', '') @@ -276,13 +276,13 @@ class Bus(object): line = line.split('<{')[-1].split('}>')[-1] last_port = -1 last_prot = None - for slave_port, slave_dict in self.fpga.address_map.items(): - if slave_dict['port_index'] == last_port and slave_dict['type'] == last_prot: + for mmport, mm_port_dict in self.fpga.address_map.items(): + if mm_port_dict['port_index'] == last_port and mm_port_dict['type'] == last_prot: continue - last_port = slave_dict['port_index'] - last_prot = slave_dict['type'] - if slave_dict['type'] == type: - sublines.append(line.format(slave_dict['peripheral'].name(), slave_dict['port_index'])) + last_port = mm_port_dict['port_index'] + last_prot = mm_port_dict['type'] + if mm_port_dict['type'] == type: + sublines.append(line.format(mm_port_dict['peripheral'].name(), mm_port_dict['port_index'])) lines.extend(tab_aligned(sublines)) return lines @@ -317,24 +317,24 @@ class Bus(object): def calc_indexes(self): """ - Calculate interconnects and local slave port numbers for all slaves + Calculate interconnects and local MM port port numbers for all MM ports """ logger.debug("enter calc_indexes()") - logger.debug("nof_slaves=%d", self.nof_slaves) + logger.debug("nof_mm_ports=%d", self.nof_mm_ports) index_list = [] - for i in range(self.nof_slaves): + for i in range(self.nof_mm_ports): if np.floor(i/15) < self.nof_interconnects: interconnect_num = int(np.floor(i/15)) else : interconnect_num = int(np.floor(i/15)-1) - if np.mod(i, 15) == 0 and i == (self.nof_slaves-1) and self.nof_interconnects > 1 : - local_slave_num = 15 + if np.mod(i, 15) == 0 and i == (self.nof_mm_ports-1) and self.nof_interconnects > 1 : + local_mm_port_num = 15 else : - local_slave_num = np.mod(i, 15) - logger.debug("slave_{} on interconnect {} with local port {} nof_interconnects {}".format( - i, interconnect_num, local_slave_num, self.nof_interconnects)) + local_mm_port_num = np.mod(i, 15) + logger.debug("MM port_{} on interconnect {} with local port {} nof_interconnects {}".format( + i, interconnect_num, local_mm_port_num, self.nof_interconnects)) - index_list.append((interconnect_num, local_slave_num)) + index_list.append((interconnect_num, local_mm_port_num)) return index_list diff --git a/gen_c_config.py b/gen_c_config.py index 441e4a4347de86983f69ad8a0e8dc3a9aafd34b4..96ce0a5ff551e7c22a1afcd1c3ea7a1514901186 100755 --- a/gen_c_config.py +++ b/gen_c_config.py @@ -69,21 +69,21 @@ def gen_c_config(fpga, fpga_name, out_dir): out.append(txt) - slave = periph_info['slave'] - num_slaves = slave.number_of_slaves() - slave_name = slave.name() - if isinstance(slave, RAM): - if slave.user_defined_name(): - out.append('# RAM-SLAVE={:20}'.format(slave.user_defined_name())) + mmport = periph_info['mmport'] + num_mm_ports = mmport.number_of_mm_ports() + mm_port_name = mmport.name() + if isinstance(mmport, RAM): + if mmport.user_defined_name(): + out.append('# RAM-SLAVE={:20}'.format(mmport.user_defined_name())) else: - out.append('# RAM-SLAVE={:20}'.format(slave.name())) + out.append('# RAM-SLAVE={:20}'.format(mmport.name())) ram_base = base - ram_len = int(slave.address_length() / WORD_SIZE) + ram_len = int(mmport.address_length() / WORD_SIZE) ram_name = 'data' - access = slave.access_mode() -# width = slave.width() # Should be slave.user_width() ?? - for i in range(0, num_slaves): + access = mmport.access_mode() +# width = mmport.width() # Should be mmport.user_width() ?? + for i in range(0, num_mm_ports): txt = [' BlockRAM 0x{:08X} len={} {}'.format( ram_base + i * ram_len, ram_len, access)] @@ -92,89 +92,89 @@ def gen_c_config(fpga, fpga_name, out_dir): else: txt.append('{}[{}]'.format(pname, p_num)) - if num_slaves == 1: - txt.append('{} {}'.format(slave_name, ram_name)) + if num_mm_ports == 1: + txt.append('{} {}'.format(mm_port_name, ram_name)) else: - txt.append('{}[{}] {}'.format(slave_name, i, ram_name)) + txt.append('{}[{}] {}'.format(mm_port_name, i, ram_name)) out.append(' '.join(txt)) field_count += 1 - elif isinstance(slave, FIFO): - if slave.user_defined_name(): - out.append('# FIFO-SLAVE={:20}'.format(slave.user_defined_name())) + elif isinstance(mmport, FIFO): + if mmport.user_defined_name(): + out.append('# FIFO-SLAVE={:20}'.format(mmport.user_defined_name())) else: - out.append('# FIFO-SLAVE={:20}'.format(slave.name())) + out.append('# FIFO-SLAVE={:20}'.format(mmport.name())) fifo_base = base - fifo_len = int(slave.address_length() / WORD_SIZE) + fifo_len = int(mmport.address_length() / WORD_SIZE) fifo_name = 'data' - access = slave.access_mode() -# width = slave.width() # Should be slave.user_width() ?? - for i in range(0, num_slaves): + access = mmport.access_mode() +# width = mmport.width() # Should be mmport.user_width() ?? + for i in range(0, num_mm_ports): txt = [' FIFO 0x{:08X} len={} {}'.format( fifo_base + i * fifo_len, fifo_len, access)] if p_num == 0: txt.append('{}'.format(pname)) else: txt.append('{}[{}]'.format(pname, p_num)) - if num_slaves == 1: - txt.append('{} {}'.format(slave_name, fifo_name)) + if num_mm_ports == 1: + txt.append('{} {}'.format(mm_port_name, fifo_name)) else: - txt.append('{}[{}] {}'.format(slave_name, i, fifo_name)) + txt.append('{}[{}] {}'.format(mm_port_name, i, fifo_name)) out.append(' '.join(txt)) field_count += 1 - elif isinstance(slave, Register): + elif isinstance(mmport, Register): - if slave.user_defined_name(): - out.append('# REG-SLAVE={} no.slaves={} len={} (base=0x{:X})'.format( - slave.user_defined_name(), - slave.number_of_slaves(), - int(slave.address_length() / WORD_SIZE), - int(slave.base_address() / WORD_SIZE))) - #int(slave.base_address() / WORD_SIZE))) + if mmport.user_defined_name(): + out.append('# REG-SLAVE={} no.mm_ports={} len={} (base=0x{:X})'.format( + mmport.user_defined_name(), + mmport.number_of_mm_ports(), + int(mmport.address_length() / WORD_SIZE), + int(mmport.base_address() / WORD_SIZE))) + #int(mmport.base_address() / WORD_SIZE))) else: - out.append('# REG-SLAVE={} no.slaves={} len={} (base=0x{:X})'.format( - slave.name(), slave.number_of_slaves(), - int(slave.address_length() / WORD_SIZE), - int(slave.base_address() / WORD_SIZE))) - #int(slave.base_address() / WORD_SIZE))) + out.append('# REG-SLAVE={} no.mm_ports={} len={} (base=0x{:X})'.format( + mmport.name(), mmport.number_of_mm_ports(), + int(mmport.address_length() / WORD_SIZE), + int(mmport.base_address() / WORD_SIZE))) + #int(mmport.base_address() / WORD_SIZE))) # Fields that have a non-unity 'number_of_fields' specifier may - # become RAM at the start of the slave instances - for ram in slave.rams: + # become RAM at the start of the MM port instances + for ram in mmport.rams: ram_base = int(ram.base_address() / WORD_SIZE) + base ram_len = int(ram.number_of_fields()) ram_name = ram.name() access = ram.access_mode() - for i in range(0, num_slaves): + for i in range(0, num_mm_ports): txt = [' DistrRAM 0x{:08X} len={} {}'.format( ram_base + i * ram_len, ram_len, access)] if p_num == 0: txt.append('{}'.format(pname)) else: txt.append('{}[{}]'.format(pname, p_num)) - if num_slaves == 1: - txt.append('{} {}'.format(slave_name, ram_name)) + if num_mm_ports == 1: + txt.append('{} {}'.format(mm_port_name, ram_name)) else: - txt.append('{}[{}] {}'.format(slave_name, i, ram_name)) + txt.append('{}[{}] {}'.format(mm_port_name, i, ram_name)) out.append(' '.join(txt)) field_count += 1 -# if num_slaves == 1: +# if num_mm_ports == 1: # out.append(' DistrRAM 0x{:08X} len={} {} {} {} {}'.format( -# ram_base, ram_len,access,pname,slave_name, ram_name)) +# ram_base, ram_len,access,pname,mm_port_name, ram_name)) # else: -# for i in range(0,num_slaves): +# for i in range(0,num_mm_ports): # out.append(' DistrRAM 0x{:08X} len={} {} {} {} {}[{}]'.format( -# ram_base+i*ram_len, ram_len,access,pname, slave_name, ram_name, i)) +# ram_base+i*ram_len, ram_len,access,pname, mm_port_name, ram_name, i)) field_base = base - if slave.rams: - field_base += int(slave.base_address() / WORD_SIZE) + if mmport.rams: + field_base += int(mmport.base_address() / WORD_SIZE) # All other fields (with unity 'number_of_fields' attribute) - slave_length = int(slave.address_length() / WORD_SIZE) - for i in range(0, num_slaves): - for fld in slave.fields: + mm_port_length = int(mmport.address_length() / WORD_SIZE) + for i in range(0, num_mm_ports): + for fld in mmport.fields: bit_lo = fld.bit_offset() bit_hi = bit_lo + fld.width() - 1 # field_base = f.base_address @@ -183,15 +183,15 @@ def gen_c_config(fpga, fpga_name, out_dir): access = fld.access_mode() txt = [' BitField 0x{:08X} b[{}:{}] {}'.format( - field_offset + field_base + i * slave_length, bit_hi, bit_lo, access)] + field_offset + field_base + i * mm_port_length, bit_hi, bit_lo, access)] if p_num == 0: txt.append('{}'.format(pname)) else: txt.append('{}[{}]'.format(pname, p_num)) - if num_slaves == 1: - txt.append('{} {}'.format(slave_name, field_name)) + if num_mm_ports == 1: + txt.append('{} {}'.format(mm_port_name, field_name)) else: - txt.append('{}[{}] {}'.format(slave_name, i, field_name)) + txt.append('{}[{}] {}'.format(mm_port_name, i, field_name)) out.append(' '.join(txt)) field_count += 1 diff --git a/gen_doc.py b/gen_doc.py index 00399aba24af0122dbab153474618342219015d4..b0b65ed75777f76324bd1cd1af9325fd535d1eaf 100755 --- a/gen_doc.py +++ b/gen_doc.py @@ -219,16 +219,16 @@ class FPGADocumentation(object): self.doc.append(self.fpga.fpga_description) self.doc.append(NewLine()) self.doc.append(NewLine()) - self.doc.append(MediumText(bold('Slave Port Map'))) + self.doc.append(MediumText(bold('MM Port Map'))) self.doc.append(NewLine()) self.doc.append(NewLine()) fpga_system_table = Tabular('|r|r|l|c|r|') fpga_system_table.add_hline() - fpga_system_table.add_row(('Base byte address', 'Range (Bytes)', 'Slave Port', 'Protocol', 'Port No.')) + fpga_system_table.add_row(('Base byte address', 'Range (Bytes)', 'MM Port', 'Protocol', 'Port No.')) fpga_system_table.add_hline() - for slave_port, slave_dict in self.fpga.address_map.items(): - fpga_system_table.add_row(('0x{:08x}'.format(slave_dict['base']), slave_dict['span'], slave_port, slave_dict['type'], slave_dict['port_index'])) + for mm_port, mm_port_dict in self.fpga.address_map.items(): + fpga_system_table.add_row(('0x{:08x}'.format(mm_port_dict['base']), mm_port_dict['span'], mm_port, mm_port_dict['type'], mm_port_dict['port_index'])) fpga_system_table.add_hline() self.doc.append(fpga_system_table) @@ -250,46 +250,46 @@ class FPGADocumentation(object): self.doc.append(NewPage()) periph_subsection = Section(periph_name, numbering=True) periph_subsection.append(periph.get_description().replace('""', '')) - periph_reg_section = Subsection("{} register slave".format(periph_name), numbering=False) + periph_reg_section = Subsection("{} register MM port".format(periph_name), numbering=False) periph_reg_table = Tabular('|r|r|r|l|c|') periph_reg_table.add_hline() - periph_reg_table.add_row(('Base-addr', 'Addr-offset', 'Range', 'Reg-group', 'N-Slaves')) + periph_reg_table.add_row(('Base-addr', 'Addr-offset', 'Range', 'Reg-group', 'N-MM ports')) periph_reg_table.add_hline() - slave_subsections = Subsection("Slave Ports for peripheral \'{}\'".format(periph_name), numbering=False) - for slave in periph.slaves: - slave_type = 'Register block' if isinstance(slave, Register) else 'RAM' if isinstance(slave, RAM) else 'FIFO' - slave_subsection = Subsection("Slave Port: {} ({})".format(slave.name(), slave_type), numbering=True) - slave_subsection.append(slave.get_kv('slave_description')) - slave_subsection.append(NewLine()) - slave_subsection.append(NewLine()) - slave_subsection.append("Address Length: {} bytes".format(str(slave.address_length()))) - slave_subsection.append(NewLine()) - slave_subsection.append("Number of Slaves: {}".format(str(slave.number_of_slaves()))) - slave_subsection.append(NewLine()) - slave_subsection.append(NewLine()) - - if isinstance(slave, Register): # expand registers and fields - periph_reg_table.add_row((slave.base_address(), '', slave.address_length(), slave.name(), slave.number_of_slaves())) + mm_port_subsections = Subsection("MM port Ports for peripheral \'{}\'".format(periph_name), numbering=False) + for mmport in periph.mm_ports: + mm_port_type = 'Register block' if isinstance(mmport, Register) else 'RAM' if isinstance(mmport, RAM) else 'FIFO' + mm_port_subsection = Subsection("MM port Port: {} ({})".format(mmport.name(), mm_port_type), numbering=True) + mm_port_subsection.append(mmport.get_kv('mm_port_description')) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append("Address Length: {} bytes".format(str(mmport.address_length()))) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append("Number of MM ports: {}".format(str(mmport.number_of_mm_ports()))) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append(NewLine()) + + if isinstance(mmport, Register): # expand registers and fields + periph_reg_table.add_row((mmport.base_address(), '', mmport.address_length(), mmport.name(), mmport.number_of_mm_ports())) periph_reg_table.add_hline() - for ram in slave.rams: - periph_reg_table.add_row(('', ram.address_offset(), ram.number_of_fields() * WORD_SIZE, '>> {} (RAM)'.format(ram.name()), slave.number_of_slaves())) + for ram in mmport.rams: + periph_reg_table.add_row(('', ram.address_offset(), ram.number_of_fields() * WORD_SIZE, '>> {} (RAM)'.format(ram.name()), mmport.number_of_mm_ports())) periph_reg_table.add_hline() added_field_groups = [] # generate register table i.e. by word group_address = -1 group_list = [] - for field in slave.fields: + for field in mmport.fields: if field.address_offset() != group_address: group_address = field.address_offset() group_list.append(field) c_max_rows = 30 nof_cols = ceil(len(group_list) / c_max_rows) # register table has max length of 40 nof_rows = min(len(group_list), c_max_rows) - slave_table = Tabular('|c|c|' * nof_cols) - slave_table.add_hline() - slave_table.add_row(['Hex', 'Field Group'] * nof_cols) - slave_table.add_hline() + mm_port_table = Tabular('|c|c|' * nof_cols) + mm_port_table.add_hline() + mm_port_table.add_row(['Hex', 'Field Group'] * nof_cols) + mm_port_table.add_hline() for i in range(nof_rows): row = [] for j in range(nof_cols): @@ -298,20 +298,20 @@ class FPGADocumentation(object): row.extend([str(hex(group_list[i + c_max_rows * j].address_offset())), group_list[i + c_max_rows * j].name()]) else : row.extend(['', '']) - slave_table.add_row(row) - slave_table.add_hline() + mm_port_table.add_row(row) + mm_port_table.add_hline() - slave_subsection.append(slave_table) - slave_subsection.append(NewPage()) + mm_port_subsection.append(mm_port_table) + mm_port_subsection.append(NewPage()) group_address = -1 - for field in slave.fields: + for field in mmport.fields: if field.address_offset() != group_address: group_address = field.address_offset() group_subsection = Subsection('{} {}'.format(str(hex(field.address_offset())), field.name() if field.group_name() is None else field.group_name()), numbering=False) - group_fields = [field for field in slave.fields if field.address_offset() == group_address] + group_fields = [field for field in mmport.fields if field.address_offset() == group_address] if len(group_fields) > 10: - slave_subsection.append(NewPage()) + mm_port_subsection.append(NewPage()) group_subsection = gen_reg_tables(group_subsection, group_fields) for field in group_fields[::-1]: field_name = field.name() if field.group_name() is None else field.name().split(field.group_name() + '_')[-1] @@ -320,19 +320,19 @@ class FPGADocumentation(object): group_subsection.append("\t\t{}".format(field.field_description())) group_subsection.append(NewLine()) group_subsection.append(NewLine()) - slave_subsection.append(group_subsection) + mm_port_subsection.append(group_subsection) else: # RAM or FIFO - slave_subsection.append("Data width: {}".format(slave.width())) - slave_subsection.append(NewLine()) - if isinstance(slave, RAM): - slave_subsection.append("User data width: {}".format(slave.user_width())) + mm_port_subsection.append("Data width: {}".format(mmport.width())) + mm_port_subsection.append(NewLine()) + if isinstance(mmport, RAM): + mm_port_subsection.append("User data width: {}".format(mmport.user_width())) - slave_subsections.append(slave_subsection) + mm_port_subsections.append(mm_port_subsection) periph_reg_section.append(periph_reg_table) self.doc.append(periph_subsection) - if any([isinstance(slave, Register) for slave in periph.slaves]): + if any([isinstance(mmport, Register) for mmport in periph.mm_ports]): self.doc.append(periph_reg_section) - self.doc.append(slave_subsections) + self.doc.append(mm_port_subsections) self.doc.append(NewPage()) @@ -385,52 +385,52 @@ class PeripheralDocumentation(object): # Peripheral System Map Table periph_subsection.append(NewLine()) periph_subsection.append(NewLine()) - periph_subsection.append(MediumText(bold('Local Slave Port Map'))) + periph_subsection.append(MediumText(bold('Local MM port Port Map'))) periph_subsection.append(NewLine()) periph_subsection.append(NewLine()) periph_system_table = Tabular('|c|c|c|c|') periph_system_table.add_hline() - periph_system_table.add_row(('Hex', 'Range (Bytes)', 'Slave Port', 'Protocol')) + periph_system_table.add_row(('Hex', 'Range (Bytes)', 'MM port Port', 'Protocol')) periph_system_table.add_hline() # peripheral system address map dummyFPGA = FPGA(None) dummyFPGA.peripherals.update({periph_name: periph}) dummyFPGA.create_address_map() - for slave_port, slave_dict in dummyFPGA.address_map.items(): - periph_system_table.add_row((str(hex(slave_dict['base'])), str(slave_dict['span']), slave_port, slave_dict['type'])) + for mm_port, mm_port_dict in dummyFPGA.address_map.items(): + periph_system_table.add_row((str(hex(mm_port_dict['base'])), str(mm_port_dict['span']), mm_port, mm_port_dict['type'])) periph_system_table.add_hline() periph_subsection.append(periph_system_table) - periph_reg_section = Subsection("{} register slave".format(periph_name), numbering=False) + periph_reg_section = Subsection("{} register MM port".format(periph_name), numbering=False) periph_reg_table = Tabular('|c|c|c|c|') periph_reg_table.add_hline() - periph_reg_table.add_row(('Base Address', 'Range', 'Register group', 'Number of Slaves')) + periph_reg_table.add_row(('Base Address', 'Range', 'Register group', 'Number of MM ports')) periph_reg_table.add_hline() - slave_subsections = Subsection("Slave Ports for peripheral \'{}\'".format(periph_name), numbering=False) - for slave in periph.slaves: - slave_subsection = Subsection("Slave Port: {} ({})".format(slave.name(), 'Register block' if isinstance(slave, Register) else 'RAM' if isinstance(slave, RAM) else 'FIFO'), numbering=True) - slave_subsection.append(slave.get_kv('slave_description')) - slave_subsection.append(NewLine()) - slave_subsection.append(NewLine()) - slave_subsection.append("Address Length: {}".format(str(slave.address_length()))) - slave_subsection.append(NewLine()) - slave_subsection.append("Number of Slaves: {}".format(str(slave.number_of_slaves()))) - slave_subsection.append(NewLine()) - slave_subsection.append(NewLine()) - - if isinstance(slave, Register): # expand registers and fields - for ram in slave.rams: - periph_reg_table.add_row((str(ram.base_address()), str(ram.number_of_fields() * WORD_SIZE), ram.name() + ' (RAM)', str(slave.number_of_slaves()))) + mm_port_subsections = Subsection("MM port Ports for peripheral \'{}\'".format(periph_name), numbering=False) + for mmport in periph.mm_ports: + mm_port_subsection = Subsection("MM port Port: {} ({})".format(mmport.name(), 'Register block' if isinstance(mmport, Register) else 'RAM' if isinstance(mmport, RAM) else 'FIFO'), numbering=True) + mm_port_subsection.append(mmport.get_kv('mm_port_description')) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append("Address Length: {}".format(str(mmport.address_length()))) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append("Number of MM ports: {}".format(str(mmport.number_of_mm_ports()))) + mm_port_subsection.append(NewLine()) + mm_port_subsection.append(NewLine()) + + if isinstance(mmport, Register): # expand registers and fields + for ram in mmport.rams: + periph_reg_table.add_row((str(ram.base_address()), str(ram.number_of_fields() * WORD_SIZE), ram.name() + ' (RAM)', str(mmport.number_of_mm_ports()))) periph_reg_table.add_hline() - periph_reg_table.add_row((str(slave.base_address()), str(slave.address_length()), slave.name(), str(slave.number_of_slaves()))) + periph_reg_table.add_row((str(mmport.base_address()), str(mmport.address_length()), mmport.name(), str(mmport.number_of_mm_ports()))) periph_reg_table.add_hline() added_field_groups = [] # generate register table i.e. by word group_address = -1 group_list = [] - for field in slave.fields: + for field in mmport.fields: if field.address_offset() != group_address: group_address = field.address_offset() group_list.append(field) @@ -438,10 +438,10 @@ class PeripheralDocumentation(object): c_max_rows = 30 nof_cols = ceil(len(group_list) / c_max_rows) # register table has max length of c_max_rows nof_rows = min(len(group_list), c_max_rows) - slave_table = Tabular('|c|c|' * nof_cols) - slave_table.add_hline() - slave_table.add_row(['Hex', 'Field Group'] * nof_cols) - slave_table.add_hline() + mm_port_table = Tabular('|c|c|' * nof_cols) + mm_port_table.add_hline() + mm_port_table.add_row(['Hex', 'Field Group'] * nof_cols) + mm_port_table.add_hline() for i in range(nof_rows): row = [] for j in range(nof_cols): @@ -450,20 +450,20 @@ class PeripheralDocumentation(object): row.extend([str(hex(group_list[i + c_max_rows * j].address_offset())), group_list[i + c_max_rows * j].name()]) else : row.extend(['', '']) - slave_table.add_row(row) - slave_table.add_hline() + mm_port_table.add_row(row) + mm_port_table.add_hline() - slave_subsection.append(slave_table) - slave_subsection.append(NewPage()) + mm_port_subsection.append(mm_port_table) + mm_port_subsection.append(NewPage()) group_address = -1 - for field in slave.fields: + for field in mmport.fields: if field.address_offset() != group_address: group_address = field.address_offset() group_subsection = Subsection('{} {}'.format(str(hex(field.address_offset())), field.name() if field.group_name() is None else field.group_name()), numbering=False) - group_fields = [field for field in slave.fields if field.address_offset() == group_address] + group_fields = [field for field in mmport.fields if field.address_offset() == group_address] if len(group_fields) > 10: - slave_subsection.append(NewPage()) + mm_port_subsection.append(NewPage()) group_subsection = gen_reg_tables(group_subsection, group_fields) for field in group_fields[::-1]: field_name = field.name() if field.group_name() is None else field.name().split(field.group_name() + '_')[-1] @@ -472,19 +472,19 @@ class PeripheralDocumentation(object): group_subsection.append("\t\t{}".format(field.field_description())) group_subsection.append(NewLine()) group_subsection.append(NewLine()) - slave_subsection.append(group_subsection) + mm_port_subsection.append(group_subsection) else: # RAM or FIFO - slave_subsection.append("Data width: {}".format(slave.width())) - slave_subsection.append(NewLine()) - if isinstance(slave, RAM): - slave_subsection.append("User data width: {}".format(slave.user_width())) + mm_port_subsection.append("Data width: {}".format(mmport.width())) + mm_port_subsection.append(NewLine()) + if isinstance(mmport, RAM): + mm_port_subsection.append("User data width: {}".format(mmport.user_width())) - slave_subsections.append(slave_subsection) + mm_port_subsections.append(mm_port_subsection) periph_reg_section.append(periph_reg_table) self.doc.append(periph_subsection) - if any([isinstance(slave, Register) for slave in periph.slaves]): + if any([isinstance(mmport, Register) for mmport in periph.mm_ports]): self.doc.append(periph_reg_section) - self.doc.append(slave_subsections) + self.doc.append(mm_port_subsections) self.doc.append(NewPage()) diff --git a/gen_fpgamap_py.py b/gen_fpgamap_py.py index bc6c40dae8a9fcc31396929548708378cafd3941..23eb163580448544e5368b25f2d7dd745c9affad 100755 --- a/gen_fpgamap_py.py +++ b/gen_fpgamap_py.py @@ -39,66 +39,66 @@ import pprint def genPython(fpga, fpgaName, addr_size=4, readable=False): - slavePorts = {} - print("Including slave ports for {}:".format(fpgaName)) - for slavePortName, slavePortInfo in fpga.address_map.items(): - if slavePortInfo['periph_num'] > 0: + mmPorts = {} + print("Including MM ports for {}:".format(fpgaName)) + for mmPortName, mmPortInfo in fpga.address_map.items(): + if mmPortInfo['periph_num'] > 0: continue - peripheral = slavePortInfo['peripheral'] - slave = slavePortInfo['slave'] - base = int(slavePortInfo['base'] / addr_size) # Convert from AXI byte address to register address - if peripheral.name() not in slavePorts: - slavePorts[peripheral.name()] = {'slaves': {}, 'start': base, 'span': int(slavePortInfo['span'] / addr_size), 'count': peripheral.number_of_peripherals()} + peripheral = mmPortInfo['peripheral'] + mmport = mmPortInfo['mm_port'] + base = int(mmPortInfo['base'] / addr_size) # Convert from AXI byte address to register address + if peripheral.name() not in mmPorts: + mmPorts[peripheral.name()] = {'mm_ports': {}, 'start': base, 'span': int(mmPortInfo['span'] / addr_size), 'count': peripheral.number_of_peripherals()} else: - slavePorts[peripheral.name()]['span'] += int(slavePortInfo['span'] / addr_size) - slaves = slavePorts[peripheral.name()]['slaves'] - slaveOffset = base - slavePorts[peripheral.name()]['start'] - if isinstance(slave, RAM): - print(' {} at 0x{:X}'.format(slavePortName, base)) - # Note py_args_lib quirk. RAM slaves include a single named field. There doesn't seem to be any way to recover this + mmPorts[peripheral.name()]['span'] += int(mmPortInfo['span'] / addr_size) + mm_ports = mmPorts[peripheral.name()]['mm_ports'] + mmPortOffset = base - mmPorts[peripheral.name()]['start'] + if isinstance(mmport, RAM): + print(' {} at 0x{:X}'.format(mmPortName, base)) + # Note py_args_lib quirk. RAM mm_ports include a single named field. There doesn't seem to be any way to recover this # from py_args_lib at present. I shall assume that this field is always called "data" - slaves[slave.name()] = {'type': 'RAM', - 'start': slaveOffset, - 'step': slave.number_of_fields(), - 'stop': slaveOffset+slave.number_of_fields()*slave.number_of_slaves(), + mm_ports[mmport.name()] = {'type': 'RAM', + 'start': mmPortOffset, + 'step': mmport.number_of_fields(), + 'stop': mmPortOffset+mmport.number_of_fields()*mmport.number_of_mm_ports(), 'fields': {'data': {'start': 0, 'step': 1, - 'stop': slave.number_of_fields(), - 'access_mode': slave.access_mode(), - 'width': slave.width(), - 'default': slave.reset_value(), - 'description': slave.field_description(), - 'bit_offset': slave.bit_offset()} + 'stop': mmport.number_of_fields(), + 'access_mode': mmport.access_mode(), + 'width': mmport.width(), + 'default': mmport.reset_value(), + 'description': mmport.field_description(), + 'bit_offset': mmport.bit_offset()} } } # code.interact(local=locals()) - elif isinstance(slave, FIFO): - print(' {} at 0x{:X}'.format(slavePortName, base)) - # Assume one field per FIFO slave + elif isinstance(mmport, FIFO): + print(' {} at 0x{:X}'.format(mmPortName, base)) + # Assume one field per FIFO MM port # Assume one field per word - slaves[slave.name()] = {'type': 'FIFO', - 'start': slaveOffset, + mm_ports[mmport.name()] = {'type': 'FIFO', + 'start': mmPortOffset, 'step': 1, - 'stop': slaveOffset+slave.number_of_slaves(), + 'stop': mmPortOffset+mmport.number_of_mm_ports(), 'fields': {'data': {'start': 0, 'step': 1, 'stop': 1, - 'access_mode': slave.access_mode(), - 'width': slave.width(), - 'default': slave.reset_value(), - 'description': slave.field_description(), - 'bit_offset': slave.bit_offset(), - 'depth': slave.number_of_fields()} + 'access_mode': mmport.access_mode(), + 'width': mmport.width(), + 'default': mmport.reset_value(), + 'description': mmport.field_description(), + 'bit_offset': mmport.bit_offset(), + 'depth': mmport.number_of_fields()} } } - elif isinstance(slave, Register): - print(' {} at 0x{:X}'.format(slavePortName, base)) + elif isinstance(mmport, Register): + print(' {} at 0x{:X}'.format(mmPortName, base)) fields = {} minOffset = 2**32 maxOffset = 0 - for r in slave.rams: - offset = int(r.base_address()/addr_size) - slaveOffset - stop_address = offset + (slave.number_of_slaves()-1)*ceil_pow2(r.number_of_fields())+r.number_of_fields() + for r in mmport.rams: + offset = int(r.base_address()/addr_size) - mmPortOffset + stop_address = offset + (mmport.number_of_mm_ports()-1)*ceil_pow2(r.number_of_fields())+r.number_of_fields() fields[r.name()] = {'start': offset, 'step': 1, 'stop': stop_address, @@ -109,9 +109,9 @@ def genPython(fpga, fpgaName, addr_size=4, readable=False): 'bit_offset': 0} minOffset = min(minOffset, offset) maxOffset = max(maxOffset, stop_address) - for f in slave.fields: + for f in mmport.fields: # Note py_args_lib quirk. When number_of_fields > 1 then numeric field id is added to string field name - offset = int(f.address_offset()/addr_size) + int(slave.base_address()/addr_size) - slaveOffset + offset = int(f.address_offset()/addr_size) + int(mmport.base_address()/addr_size) - mmPortOffset fields[f.name()] = {'start': offset, 'step': 1, @@ -123,15 +123,15 @@ def genPython(fpga, fpgaName, addr_size=4, readable=False): 'bit_offset': f.bit_offset()} minOffset = min(minOffset, offset) maxOffset = max(maxOffset, offset+1) - slaves[slave.name()] = {'type': 'REG', - 'start': slaveOffset, + mm_ports[mmport.name()] = {'type': 'REG', + 'start': mmPortOffset, 'step': maxOffset, - 'stop': slaveOffset+slave.number_of_slaves()*(maxOffset), + 'stop': mmPortOffset+mmport.number_of_mm_ports()*(maxOffset), 'fields': fields} map = {} - for k, v in slavePorts.items(): - map[k] = {'start': v['start'], 'step': v['span'], 'stop': v['start']+v['count']*v['span'], 'slaves': v['slaves']} + for k, v in mmPorts.items(): + map[k] = {'start': v['start'], 'step': v['span'], 'stop': v['start']+v['count']*v['span'], 'mm_ports': v['mm_ports']} pp = pprint.PrettyPrinter(width=300) mapStr = pp.pformat(map) if readable else str(map) diff --git a/gen_hdl.py b/gen_hdl.py index 8149df7eb9fec07b54e5f331d573689ce0010d4f..15259e385d1083fa941ad3de34c2d105c16af695 100755 --- a/gen_hdl.py +++ b/gen_hdl.py @@ -34,7 +34,7 @@ from args_logger import MyLogger from py_args_lib import * -import gen_slave +import gen_mm_port import gen_bus import gen_doc import gen_fpgamap_py @@ -121,12 +121,12 @@ class HDLGen(object): continue if peripheral.evaluated is False: peripheral.eval_peripheral() - periph_slave = gen_slave.Slave(peripheral, self.hdl_lib_name, args_lib_name if is_fpga else None) - periph_slave.generate_regs(out_dir) + periph_mm_port = gen_mm_port.MMPort(peripheral, self.hdl_lib_name, args_lib_name if is_fpga else None) + periph_mm_port.generate_regs(out_dir) for key in peripheral.rams: - periph_slave.generate_mem(out_dir, peripheral.rams[key], 'ram') + periph_mm_port.generate_mem(out_dir, peripheral.rams[key], 'ram') for key in peripheral.fifos: - periph_slave.generate_mem(out_dir, peripheral.fifos[key], 'fifo') + periph_mm_port.generate_mem(out_dir, peripheral.fifos[key], 'fifo') self.args_gen_doc(final_name, is_fpga) if periph_select is None: diff --git a/gen_rom_mmap.py b/gen_rom_mmap.py index d3a6c823ea62ecc67d765b4fc90ea118521c66d7..8abe78687c9b56995687657673cbdfd2f7995929 100755 --- a/gen_rom_mmap.py +++ b/gen_rom_mmap.py @@ -62,31 +62,31 @@ def gen_fpga_map(fpga, fpga_name): _map_str = [] # pprint.pprint(fpga.address_map) - print("Including slave ports for {}:".format(fpga_name)) - map_nof_columns = 9 + print("Including MM ports for {}:".format(fpga_name)) map_format_str = ' {:24s} {:4s} {:4s} {:5s} {:40s} 0x{:08x} {:6d} {:>5s} {:>11s} {:>5s} {:>10s}' - for slave_port_name, slave_port_info in fpga.address_map.items(): + map_nof_columns = len(map_format_str.split('{')) - 1 + for mm_port_name, mm_port_info in fpga.address_map.items(): # All elements in array have same info, so only need info from first element - if slave_port_info['periph_num'] > 0: + if mm_port_info['periph_num'] > 0: continue - #print("slave_port_info = {}".format(slave_port_info)) - slave = slave_port_info['slave'] - user_def_name = slave.user_defined_name().upper() + #print("mm_port_info = {}".format(mm_port_info)) + mm_port = mm_port_info['mm_port'] + user_def_name = mm_port.user_defined_name().upper() #print("number_of_peripherals = {}".format(fpga.peripherals)) number_of_peripherals = str(1) # EK TODO: get number_of_peripherals from the peripheral instance in fpga.yaml if user_def_name in ('RAM_SS_SS_WIDE', 'RAM_BF_WEIGHTS', 'REG_BF_SCALE', 'REG_HDR_DAT', 'REG_DP_XONOFF', 'RAM_ST_BST'): number_of_peripherals = str(2) # EK: FIXME temporary work around - number_of_slaves = str(slave.number_of_slaves()) - base = int(slave_port_info['base']) - base_word = int(base / WORD_SIZE) + number_of_mm_ports = str(mm_port.number_of_mm_ports()) + base = int(mm_port_info['base']) + base_word = int(base / WORD_SIZE) - # EK TODO: new structured naming: slave_port_name = slave_name + peripheral_group ~= user_def_name - if isinstance(slave, RAM): - print(' RAM {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name)) + # EK TODO: new structured naming: mm_port_name = mm_port_name + peripheral_group ~= user_def_name + if isinstance(mm_port, RAM): + print(' RAM {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(mm_port_name, base, base_word, user_def_name)) # EK: TODO should get radix info from field and use _make_mask(). radix = '-' @@ -96,19 +96,19 @@ def gen_fpga_map(fpga, fpga_name): _map_str.append(map_format_str.format( user_def_name, number_of_peripherals, - number_of_slaves, + number_of_mm_ports, 'RAM', 'data', # EK: TODO should come from yaml field_name base_word, - slave.number_of_fields(), - slave.access_mode(), + mm_port.number_of_fields(), + mm_port.access_mode(), radix, radix_packing, radix_bit_mask )) - elif isinstance(slave, FIFO): - print(' FIFO {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name)) + elif isinstance(mm_port, FIFO): + print(' FIFO {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(mm_port_name, base, base_word, user_def_name)) # EK: TODO should get radix info from field and use _make_mask(). radix = '-' @@ -118,27 +118,27 @@ def gen_fpga_map(fpga, fpga_name): _map_str.append(map_format_str.format( user_def_name, number_of_peripherals, - number_of_slaves, + number_of_mm_ports, 'FIFO', 'data', # EK: TODO should come from yaml field_name base_word, - slave.number_of_fields(), - slave.access_mode(), + mm_port.number_of_fields(), + mm_port.access_mode(), radix, radix_packing, radix_bit_mask )) - elif isinstance(slave, Register): - slave_type = "REG" # EK: TODO get slave_type from slave ? - print(' REG {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(slave_port_name, base, base_word, user_def_name)) + elif isinstance(mm_port, Register): + mm_port_type = "REG" # EK: TODO get mm_port_type from mm_port ? + print(' REG {:80s} at 0x{:08x}(bytes) 0x{:04x}(words) "{}"'.format(mm_port_name, base, base_word, user_def_name)) done = [] - for f in slave.fields: + for f in mm_port.fields: field_name = f.name() #print('{}: {}, {}, {}'.format(field_name, f.radix().lower(), f.radix_width(), f.radix_resolution())) - # EK: TODO the check on f.number_of_fields() and on done should not be necessary, because the array of fields should only have one element in slave.fields. The slave.number_of_fields() should not have been expanded in slave. + # EK: TODO the check on f.number_of_fields() and on done should not be necessary, because the array of fields should only have one element in mm_port.fields. The mm_port.number_of_fields() should not have been expanded in mm_port. if f.number_of_fields() > 1: field_name = f.name().strip('0123456789') # strip field array index if field_name in done: @@ -159,8 +159,8 @@ def gen_fpga_map(fpga, fpga_name): _map_str.append(map_format_str.format( user_def_name, number_of_peripherals, - number_of_slaves, - slave_type, + number_of_mm_ports, + mm_port_type, field_name, f_base, f.number_of_fields(), @@ -170,19 +170,19 @@ def gen_fpga_map(fpga, fpga_name): radix_bit_mask )) - # only log table entry for first field of slave + # only log table entry for first field of MM port user_def_name = '-' number_of_peripherals = '-' - number_of_slaves = '-' - slave_type = '-' + number_of_mm_ports = '-' + mm_port_type = '-' _map_info = [] _map_info.append('fpga_name = {}'.format(fpga_name)) # identifies <fpga_name>.fpga.yaml _map_info.append('number_of_columns = {}'.format(map_nof_columns)) # to support mmap with more columns in future - _map_info.append('# col 1: slave_port_name # = user defined QSYS name, if - then it is part of previous slave port.') + _map_info.append('# col 1: mm_port_name # = user defined QSYS name, if - then it is part of previous MM port.') _map_info.append('# col 2: number of peripherals, if - then it is part of previous peripheral.') - _map_info.append('# col 3: number of slaves, if - then it is part of previous slave.') - _map_info.append('# col 4: slave_type, if - then it is part of previous slave.') + _map_info.append('# col 3: number of mm_ports, if - then it is part of previous MM port.') + _map_info.append('# col 4: mm_port_type, if - then it is part of previous MM port.') _map_info.append('# col 5: field_name') _map_info.append('# col 6: field start address (in words)') _map_info.append('# col 7: field address span (in words)') diff --git a/gen_slave.py b/gen_slave.py index 2a048f7747c761387db0e3c6d2ac0b999af3503f..c3f746b776a8f1aa38abfb27f634a50efa6b48a1 100755 --- a/gen_slave.py +++ b/gen_slave.py @@ -39,7 +39,7 @@ import peripheral # - VHDL wrapper files # - IP creation TCL files -logger = logging.getLogger('main.gen_slave') +logger = logging.getLogger('main.gen_mm_port') def word_wise(byte_address): @@ -88,8 +88,8 @@ def vector_len(width): return '' if width == 1 else '_VECTOR(' + str(width-1) + ' downto 0)' -class Slave(object): - """Generate VHDL and IP source for memory mapped slaves""" +class MMPort(object): + """Generate VHDL and IP source for memory mapped (MM) ports""" def __init__(self, peripheral, hdl_lib_name, fpga_name=None): self.tmpl_dir = os.path.join(os.getenv('ARGS_GEAR'), 'templates') @@ -98,34 +98,34 @@ class Slave(object): self.replaceDict = {} self.periph_name = peripheral.name() self.periph_lib = hdl_lib_name - self.slaves = peripheral.slaves + self.mm_ports = peripheral.mm_ports self.prefix = ((hdl_lib_name + '_') if hdl_lib_name != peripheral.name() else '') + peripheral.name() self.output_files = [] self.fpga_name = fpga_name - def generate_mem(self, outdir, settings, slave_type): + def generate_mem(self, outdir, settings, mm_port_type): """ Generate a VHDL instantiation file and a TCL file to create and customise the IP """ self.out_dir = outdir lines = [] # fix memory to fit Xilinx IP width/depth combinations # self.xilinxConstraints() - # self.fix_mem_size(settings, slave_type) - self.gen_file(settings, slave_type, 'vhd') - self.gen_file(settings, slave_type, 'tcl') + # self.fix_mem_size(settings, mm_port_type) + self.gen_file(settings, mm_port_type, 'vhd') + self.gen_file(settings, mm_port_type, 'tcl') def generate_regs(self, outdir): - """ Generate a set of entity, pkg and instantiation files for all reg slaves """ + """ Generate a set of entity, pkg and instantiation files for all reg MM ports """ self.out_dir = outdir self.nof_dat = 0 - for slave in self.slaves: - if not isinstance(slave, Register) or (isinstance(slave, Register) and getattr(slave, 'isIP', False)): + for mmport in self.mm_ports: + if not isinstance(mmport, Register) or (isinstance(mmport, Register) and getattr(mmport, 'isIP', False)): continue - self.nof_dat = int(slave.base_address()/WORD_SIZE + slave.address_length()/WORD_SIZE*slave.number_of_slaves()) + self.nof_dat = int(mmport.base_address()/WORD_SIZE + mmport.address_length()/WORD_SIZE*mmport.number_of_mm_ports()) if self.nof_dat > 1: self.dat_w = DEFAULT_WIDTH # parameterize self.adr_w = ceil_log2(self.nof_dat) # makes addressing word wise - # self.slaves = peripheral.slaves + # self.mm_ports = peripheral.mm_ports self.gen_pkg() self.gen_file(None, 'reg', 'vhd') self.gen_file(None, 'reg', 'vho') @@ -164,10 +164,10 @@ class Slave(object): # addlines = ['USE axi4_lib.axi4_lite_pkg.ALL;\n'] line = '' if '<{constant_statements}>' in line: - for slave in self.slaves: - if not isinstance(slave, Register) or (isinstance(slave, Register) and getattr(slave, 'isIP', False)): + for mmport in self.mm_ports: + if not isinstance(mmport, Register) or (isinstance(mmport, Register) and getattr(mmport, 'isIP', False)): continue - regGroup = slave + regGroup = mmport # reg_name = regGroup.name() # fields_dict = regGroup.fields # fields_dict = registers[reg_name].fields @@ -176,10 +176,10 @@ class Slave(object): line = '' if '<{type_statements}>' in line: record_lines = [] - for slave in self.slaves: - if not isinstance(slave, Register): + for mmport in self.mm_ports: + if not isinstance(mmport, Register): continue - regGroup = slave + regGroup = mmport reg_name = regGroup.name() record_lines.extend(self.ram_records(regGroup)) record_lines.extend(self.fields_records(reg_name, regGroup, 'RW')) @@ -193,10 +193,10 @@ class Slave(object): lines.extend(addlines) self.write_file(lines, file_name) - def gen_vho(self, slaveSettings, slave_type): + def gen_vho(self, mmPortSettings, mm_port_type): lines = [] tmplFile = os.path.join(self.tmpl_dir, "template_reg_axi4.vho") - # fields_dict = slaveSettings.fields + # fields_dict = mmPortSettings.fields with open(tmplFile, 'r') as infile: for line in infile: addlines = [] @@ -204,19 +204,19 @@ class Slave(object): line = line.replace('<lib_name>', self.periph_lib if self.periph_lib == self.periph_name else self.periph_lib + '_' + self.periph_name) if '<lib>' in line: line = line.replace('<lib>', self.periph_lib) - if '<{slave_ports}>' in line: + if '<{mm_ports}>' in line: sublines = [] - for slave in self.slaves: - if not isinstance(slave, Register): + for mmport in self.mm_ports: + if not isinstance(mmport, Register): continue - for field in slave.fields: + for field in mmport.fields: if field.access_mode() == 'RW': - sublines.append('\t\t' + slave.name().upper() + '_FIELDS_RW.' + field.name() + '<tabs>=>\n') + sublines.append('\t\t' + mmport.name().upper() + '_FIELDS_RW.' + field.name() + '<tabs>=>\n') # sublines.extend(' ,\t\t -- '+ 'STD_LOGIC' + vector_len(field.width()) +'\n') if field.access_mode() == 'RO': - sublines.append('\t\t' + slave.name().upper() + '_FIELDS_RO.' + field.name() + '<tabs>=>\n') + sublines.append('\t\t' + mmport.name().upper() + '_FIELDS_RO.' + field.name() + '<tabs>=>\n') # sublines.extend(' ,\t\t -- '+ 'STD_LOGIC' + vector_len(field.width()) +'\n') - sublines.extend(self.ram_records(slave, False)) + sublines.extend(self.ram_records(mmport, False)) # lines.extend(tab_aligned(sublines)) lines.extend(sublines) line = '' @@ -225,49 +225,49 @@ class Slave(object): lines.append(');') return(tab_aligned(lines)) - def gen_vhdl(self, slaveSettings, slave_type): + def gen_vhdl(self, mmPortSettings, mm_port_type): lines = [] - slave_type = slave_type.lower() - tmplFile = os.path.join(self.tmpl_dir, "template_{}_axi4.vhd".format(slave_type)) + mm_port_type = mm_port_type.lower() + tmplFile = os.path.join(self.tmpl_dir, "template_{}_axi4.vhd".format(mm_port_type)) removePort = {} replace_dicts = {} - if slave_type == 'reg': + if mm_port_type == 'reg': self.replaceDict = {'<lib>' : self.periph_lib, '<lib_name>' : self.periph_lib if self.periph_lib == self.periph_name else self.periph_lib + '_' + self.periph_name, '<adr_w>' : self.adr_w , '<dat_w>' : self.dat_w} - for slave in self.slaves: - if not isinstance(slave, Register): + for mmport in self.mm_ports: + if not isinstance(mmport, Register): continue - regGroup = slave + regGroup = mmport # regGroup = self.registers[key] fields_dict = regGroup.fields replace_dicts.update({regGroup.name(): {'<name>': self.periph_name, '<reg_ram>': 'reg', '<reg_name>': regGroup.name(), '<adr_w>': 'c_addr_w', '<dat_w>': 'c_dat_w','<nof_dat>' : int(regGroup.address_length()/WORD_SIZE), - '<c_init_reg>': self.set_init_string(regGroup)[0], '<nof_slaves>' : regGroup.number_of_slaves(), '<addr_base>' : int(regGroup.base_address() / WORD_SIZE), + '<c_init_reg>': self.set_init_string(regGroup)[0], '<nof_mm_ports>' : regGroup.number_of_mm_ports(), '<addr_base>' : int(regGroup.base_address() / WORD_SIZE), '<c_clr_mask>': self.set_clr_mask(regGroup)[0]}}) else : - self.replaceDict = {'<name>': slaveSettings.name(), '<lib>': self.prefix, '<adr_w>': ceil_log2(slaveSettings.address_length()), - '<dat_w>': slaveSettings.width(), '<nof_dat>': slaveSettings.address_length(), '<nof_dat_by_slaves>': slaveSettings.address_length()*ceil_pow2(slaveSettings.number_of_slaves()), '<init_sl>':str(0),#slaveSettings.default() if '.coe' not in str(slaveSettings.default()) else str(0), - '<RO>' : slaveSettings.access_mode() == 'RO', '<WO>' : slaveSettings.access_mode() == 'WO', '<FTHRESHOLD>' : slaveSettings.address_length()-5, '<ETHRESHOLD>' : 2 , '<nof_slaves>':slaveSettings.number_of_slaves(), - '<t_we_arr>': 't_we_arr' if slaveSettings.number_of_slaves() > 1 else 'std_logic_vector', '<web_range>': 'c_ram_b.nof_slaves' if slaveSettings.number_of_slaves() > 1 else 'c_ram_b.dat_w/8'} - if slave_type == 'ram': - self.replaceDict.update({'<dat_wb>': slaveSettings.user_width(), '<nof_datb>': slaveSettings.user_depth(), '<adr_wb>': ceil_log2(slaveSettings.user_depth()), - '<sig_wea>': 'sig_wea' if slaveSettings.access_mode() == 'RW' else '(others => \'0\')', '<user_upper>': str(ceil_log2(slaveSettings.user_width()/8)-1), - '<user_lower>': str(ceil_log2(slaveSettings.user_width()/8))}) - if slaveSettings.number_of_slaves() == 1: + self.replaceDict = {'<name>': mmPortSettings.name(), '<lib>': self.prefix, '<adr_w>': ceil_log2(mmPortSettings.address_length()), + '<dat_w>': mmPortSettings.width(), '<nof_dat>': mmPortSettings.address_length(), '<nof_dat_by_mm_ports>': mmPortSettings.address_length()*ceil_pow2(mmPortSettings.number_of_mm_ports()), '<init_sl>':str(0),#mmPortSettings.default() if '.coe' not in str(mmPortSettings.default()) else str(0), + '<RO>' : mmPortSettings.access_mode() == 'RO', '<WO>' : mmPortSettings.access_mode() == 'WO', '<FTHRESHOLD>' : mmPortSettings.address_length()-5, '<ETHRESHOLD>' : 2 , '<nof_mm_ports>':mmPortSettings.number_of_mm_ports(), + '<t_we_arr>': 't_we_arr' if mmPortSettings.number_of_mm_ports() > 1 else 'std_logic_vector', '<web_range>': 'c_ram_b.nof_mm_ports' if mmPortSettings.number_of_mm_ports() > 1 else 'c_ram_b.dat_w/8'} + if mm_port_type == 'ram': + self.replaceDict.update({'<dat_wb>': mmPortSettings.user_width(), '<nof_datb>': mmPortSettings.user_depth(), '<adr_wb>': ceil_log2(mmPortSettings.user_depth()), + '<sig_wea>': 'sig_wea' if mmPortSettings.access_mode() == 'RW' else '(others => \'0\')', '<user_upper>': str(ceil_log2(mmPortSettings.user_width()/8)-1), + '<user_lower>': str(ceil_log2(mmPortSettings.user_width()/8))}) + if mmPortSettings.number_of_mm_ports() == 1: appendDict = {'<sig_addra>': 'sig_addra', '<sig_dina>': 'sig_dina', '<sig_douta>': 'sig_douta','<tab>': '', '<sig_addrb>': 'sig_addrb', '<sig_dinb>': 'sig_dinb', '<sig_doutb>': 'sig_doutb', '<(i)>': '', '<array>': '', '<vector>': ''} else: appendDict = {'<sig_addra>': 'mem_mosi_arr_a(i).address', '<sig_dina>': 'mem_mosi_arr_a(i).wrdata', '<tab>': '\t', '<sig_douta>': 'mem_miso_arr_a(i).rddata', '<sig_addrb>': 'mem_mosi_arr_b(i).address', - '<sig_dinb>': 'mem_mosi_arr_b(i).wrdata', '<sig_doutb>': 'mem_miso_arr_b(i).rddata', '<(i)>': '(i)', '<array>': '_arr(g_ram_b.nof_slaves-1 downto 0)', - '<vector>': '_vector(c_ram_b.nof_slaves-1 downto 0)'} + '<sig_dinb>': 'mem_mosi_arr_b(i).wrdata', '<sig_doutb>': 'mem_miso_arr_b(i).rddata', '<(i)>': '(i)', '<array>': '_arr(g_ram_b.nof_mm_ports-1 downto 0)', + '<vector>': '_vector(c_ram_b.nof_mm_ports-1 downto 0)'} self.replaceDict.update(appendDict) portTags = {'WO' : ['RXD', 'axi4_ar', 'axi4_r', 'rxd'], 'RO' : ['TXD', 'axi4_aw', 'axi4_w', 'txd']} # change to read - if slave_type == 'fifo': - removePort[slaveSettings.access_mode()] = portTags[slaveSettings.access_mode()] - if slaveSettings.number_of_slaves() > 1 : - self.replaceDict.update({'<_arr>': '_arr(g_fifo.nof_slaves-1 downto 0)', '<_VECTOR>': '_VECTOR(g_fifo.nof_slaves-1 downto 0)', '<(i)>': '(i)'}) + if mm_port_type == 'fifo': + removePort[mmPortSettings.access_mode()] = portTags[mmPortSettings.access_mode()] + if mmPortSettings.number_of_mm_ports() > 1 : + self.replaceDict.update({'<_arr>': '_arr(g_fifo.nof_mm_ports-1 downto 0)', '<_VECTOR>': '_VECTOR(g_fifo.nof_mm_ports-1 downto 0)', '<(i)>': '(i)'}) else: self.replaceDict.update({'<_arr>': '', '<_VECTOR>': '', '<(i)>': ''}) # self.removePort['fifo_gen':['<{fifo_gen}>']] @@ -279,25 +279,25 @@ class Slave(object): if tag in line: line = line.replace(tag, str(self.replaceDict[tag])) # elif '<{' in line: - if slave_type == 'reg': + if mm_port_type == 'reg': if '<{user_clocks}>' in line: - # If any slave is a dual clock slave we need to set all up as dual clock but only once - for slave in self.slaves: - if slave.get_kv("dual_clock"): - lines.extend('st_clk_{} \t\t\t\t : IN STD_LOGIC_VECTOR(0 TO {});\n'.format(slave.name(), slave.number_of_slaves()-1)) - lines.extend('st_rst_{} \t\t\t\t : IN STD_LOGIC_VECTOR(0 TO {});\n'.format(slave.name(), slave.number_of_slaves()-1)) + # If any MM port is a dual clock MM port we need to set all up as dual clock but only once + for mmport in self.mm_ports: + if mmport.get_kv("dual_clock"): + lines.extend('st_clk_{} \t\t\t\t : IN STD_LOGIC_VECTOR(0 TO {});\n'.format(mmport.name(), mmport.number_of_mm_ports()-1)) + lines.extend('st_rst_{} \t\t\t\t : IN STD_LOGIC_VECTOR(0 TO {});\n'.format(mmport.name(), mmport.number_of_mm_ports()-1)) - nof_regs = sum([(isinstance(slave, Register) and not getattr(slave, 'isIP', False)) for slave in self.slaves]) + nof_regs = sum([(isinstance(mmport, Register) and not getattr(mmport, 'isIP', False)) for mmport in self.mm_ports]) i = 0 - for slave in self.slaves: - if not isinstance(slave, Register) or (isinstance(slave,Register) and getattr(slave, 'isIP', False)): + for mmport in self.mm_ports: + if not isinstance(mmport, Register) or (isinstance(mmport,Register) and getattr(mmport, 'isIP', False)): continue - self.regGroup = slave - regGroup = slave + self.regGroup = mmport + regGroup = mmport fields_dict = regGroup.fields - if '<{slave_ports}>' in line: - sublines = self.slave_ports() + if '<{mm_ports}>' in line: + sublines = self.mm_ports() if i == nof_regs-1: sublines[-1] = sublines[-1].replace(';', '') lines.extend(sublines) @@ -305,7 +305,7 @@ class Slave(object): lines.extend(self.c_mm_reg(replace_dicts)) if '<{signal_declarations}>' in line: for ram in regGroup.rams: - lines.extend(self.signal_declarations(ram, True, regGroup.number_of_slaves(), regGroup.name())) + lines.extend(self.signal_declarations(ram, True, regGroup.number_of_mm_ports(), regGroup.name())) lines.extend(self.signal_declarations(regGroup)) if '<{wr_val}>' in line: lines.extend(self.read_write_vals(i, nof_regs, 'wr')) @@ -324,9 +324,9 @@ class Slave(object): if '<{common_reg_inst}>' in line : # or common_reg_inst == 1: lines.extend(self.instantiate_rams()) sublines = [] - if slave.get_kv("dual_clock"): + if mmport.get_kv("dual_clock"): tmpl_file = os.path.join(self.tmpl_dir, 'template_common_reg_r_w_dc.vho') - # Need to add support for peripherals with different kinds of dual clock slaves + # Need to add support for peripherals with different kinds of dual clock mm_ports else: tmpl_file = os.path.join(self.tmpl_dir, 'template_common_reg_r_w.vho') @@ -337,12 +337,12 @@ class Slave(object): line = '' i = i + 1 else : - if slaveSettings.number_of_slaves() == 1: - generate_tags = ['SIGNAL mem', '<{multiple_slaves}>', 'GENERATE'] + if mmPortSettings.number_of_mm_ports() == 1: + generate_tags = ['SIGNAL mem', '<{multiple_mm_ports}>', 'GENERATE'] if any([tag in line for tag in generate_tags]): line = '' else : # insert mux and add generates - if '<{multiple_slaves}>' in line: + if '<{multiple_mm_ports}>' in line: tmpl_file = os.path.join(self.rootDir, 'templates/template_common_mem_mux.vho') with open(tmpl_file, 'r') as inst_file: lines.extend(inst_file) @@ -355,9 +355,9 @@ class Slave(object): lines.append(line) return(lines) - def gen_tcl(self, settings, slave_type): + def gen_tcl(self, settings, mm_port_type): lines = [] - tmplFile = os.path.join(self.tmpl_dir, "template_{}_axi4.tcl".format(slave_type)) + tmplFile = os.path.join(self.tmpl_dir, "template_{}_axi4.tcl".format(mm_port_type)) # replaceDict = {'<entity>': settings.name, '<FW>' : settings.access_mode() == 'FW', '<init_sl>' : settings.default(), '<bDefault>':settings.default() is not None, # '<dat_w>' : settings.width(), '<FR>' : settings.access_mode() == 'FR', '<nof_dat>' : settings.address_length(), '<FTHRESHOLD>' : settings.address_length() - 5, '<ETHRESHOLD>' : 2 } default = settings.reset_value() if settings.reset_value() is not None else 0 @@ -365,7 +365,7 @@ class Slave(object): removeDict = {'<coe_file>': '', 'Load_Init_File' : '', '<default>': str(hex(default)).replace('0x', '')} else : removeDict = {'<coe_file>': default, '<default>': 0} - # if slave_type == "fifo": + # if mm_port_type == "fifo": # removeDict.update({'RX': ''}) if settings.access_mode() == 'WO' else removeDict.update({'TX': ''}); with open(tmplFile, 'r') as infile: for line in infile: @@ -382,18 +382,18 @@ class Slave(object): lines.append(line) return(lines) - def gen_file(self, settings, slave_type, file_type): + def gen_file(self, settings, mm_port_type, file_type): lines = [] if file_type == 'tcl': - lines = self.gen_tcl(settings, slave_type) + lines = self.gen_tcl(settings, mm_port_type) elif file_type == 'vho': - lines = self.gen_vho(settings, slave_type) + lines = self.gen_vho(settings, mm_port_type) else : - lines = self.gen_vhdl(settings, slave_type) + lines = self.gen_vhdl(settings, mm_port_type) # outDir = os.path.join(self.rootDir, 'outputs') - out_file = ('ip_' if file_type == 'tcl' else '') + (self.prefix + '_' + settings.name() if slave_type != 'reg' else self.prefix) + '_' + slave_type + '.' + file_type - # outFile = os.path.join(outDir, prefix + settings.lib + '_' + (self.periph_name if slave_type == 'reg' else settings.name) + '_' + slave_type + '_axi4.' + file_type) + out_file = ('ip_' if file_type == 'tcl' else '') + (self.prefix + '_' + settings.name() if mm_port_type != 'reg' else self.prefix) + '_' + mm_port_type + '.' + file_type + # outFile = os.path.join(outDir, prefix + settings.lib + '_' + (self.periph_name if mm_port_type == 'reg' else settings.name) + '_' + mm_port_type + '_axi4.' + file_type) self.write_file(lines, out_file) def set_init_string(self, regGroup): @@ -442,7 +442,7 @@ class Slave(object): lines = [] bPulseFields = 0 field_list = regGroup.fields - nof_inst = regGroup.number_of_slaves() + nof_inst = regGroup.number_of_mm_ports() for field in field_list: if field.side_effect() == pulse_type: bPulseFields = 1 @@ -465,18 +465,18 @@ class Slave(object): lines = [] reg_name = regGroup.name() for ram in regGroup.rams: - for i in range(regGroup.number_of_slaves()): - lines.append('\tCONSTANT c_' + reg_name + '_' + ram.name() + (str(i) if regGroup.number_of_slaves() > 1 else '') + '_address<tabs>: t_register_address := ('+ 'base_address => ' + str(word_wise(ram.base_address()) + (i)*(ceil_pow2(ram.number_of_fields()))) +', address => 0, offset => 0, width => ' + str(ram.width()) + ', name => pad("' + reg_name + '_' + ram.name() + '"));\n' ) - for i in range(regGroup.number_of_slaves()): - slave_index = '_' + str(i) if regGroup.number_of_slaves() > 1 else '' + for i in range(regGroup.number_of_mm_ports()): + lines.append('\tCONSTANT c_' + reg_name + '_' + ram.name() + (str(i) if regGroup.number_of_mm_ports() > 1 else '') + '_address<tabs>: t_register_address := ('+ 'base_address => ' + str(word_wise(ram.base_address()) + (i)*(ceil_pow2(ram.number_of_fields()))) +', address => 0, offset => 0, width => ' + str(ram.width()) + ', name => pad("' + reg_name + '_' + ram.name() + '"));\n' ) + for i in range(regGroup.number_of_mm_ports()): + mm_port_index = '_' + str(i) if regGroup.number_of_mm_ports() > 1 else '' for field in regGroup.fields: - lines.append('\tCONSTANT c_' + reg_name + '_' + field.name() + '_address'+slave_index+'<tabs>: t_register_address := (' + 'base_address => ' + str(word_wise(regGroup.base_address())+i*word_wise(regGroup.address_length())) +', address => ' + str(word_wise(field.address_offset())) + ', offset => ' + str(field.bit_offset()) + ', width => ' + str(field.width()) + ', name => pad("' + reg_name + '_' + field.name() + '"));\n' ) - if regGroup.number_of_slaves() > 1 : + lines.append('\tCONSTANT c_' + reg_name + '_' + field.name() + '_address'+mm_port_index+'<tabs>: t_register_address := (' + 'base_address => ' + str(word_wise(regGroup.base_address())+i*word_wise(regGroup.address_length())) +', address => ' + str(word_wise(field.address_offset())) + ', offset => ' + str(field.bit_offset()) + ', width => ' + str(field.width()) + ', name => pad("' + reg_name + '_' + field.name() + '"));\n' ) + if regGroup.number_of_mm_ports() > 1 : for field in regGroup.fields: fields_string = "" - for i in range(regGroup.number_of_slaves()): - fields_string = fields_string + ("c_{0}_{1}_address_{2}{3} ".format(reg_name, field.name(), i, '' if i == (regGroup.number_of_slaves()-1) else ',')) - lines.append("\tCONSTANT c_{0}_{1}_address<tabs>: t_register_address_array(0 to {2}) := ({3});\n".format(reg_name, field.name(), str(regGroup.number_of_slaves()-1),fields_string)) + for i in range(regGroup.number_of_mm_ports()): + fields_string = fields_string + ("c_{0}_{1}_address_{2}{3} ".format(reg_name, field.name(), i, '' if i == (regGroup.number_of_mm_ports()-1) else ',')) + lines.append("\tCONSTANT c_{0}_{1}_address<tabs>: t_register_address_array(0 to {2}) := ({3});\n".format(reg_name, field.name(), str(regGroup.number_of_mm_ports()-1),fields_string)) # for field in field_list: # lowerBit = self.dat_w*field.address_offset() + field.bit_offset() @@ -487,9 +487,9 @@ class Slave(object): def ram_records(self, regGroup, bRecords=True): lines = [] - nof_inst = regGroup.number_of_slaves() + nof_inst = regGroup.number_of_mm_ports() for ram in regGroup.rams: - slave_ram_name = regGroup.name() + '_' + ram.name() + mm_port_ram_name = regGroup.name() + '_' + ram.name() bit_type = 'STD_LOGIC' if nof_inst == 1 else ('STD_LOGIC_VECTOR(0 to ' + str(nof_inst-1) + ')') adr_type = ('STD_LOGIC_VECTOR('+str(ceil_log2(ram.number_of_fields())-1)+' downto 0)' if nof_inst == 1 else ('t_slv_<>_arr(0 to ' + str(nof_inst-1) + ')')).replace('<>', str(ceil_log2(ram.number_of_fields()))) rd_type = 'STD_LOGIC_VECTOR('+str(ram.width()-1)+' downto 0)' if nof_inst == 1 else ('t_slv_'+str(ram.width())+'_arr(0 to ' + str(nof_inst-1) + ')') @@ -497,20 +497,20 @@ class Slave(object): in_ports = {'adr' : adr_type, 'wr_dat' : rd_type, 'wr_en' : bit_type, 'rd_en' : bit_type, 'clk' : bit_type, 'rst': bit_type} out_ports = {'rd_dat' : rd_type, 'rd_val': bit_type} if bRecords: - lines.append('\tTYPE t_' + slave_ram_name + '_ram_out' + ' is RECORD\n') + lines.append('\tTYPE t_' + mm_port_ram_name + '_ram_out' + ' is RECORD\n') for port, type in out_ports.items(): lines.append('\t'*2 + port + '<tabs>: ' + type + ';\n') lines.append('\tEND RECORD;\n\n') # write user_in record - lines.append('\tTYPE t_' + slave_ram_name + '_ram_in' + ' is RECORD\n') + lines.append('\tTYPE t_' + mm_port_ram_name + '_ram_in' + ' is RECORD\n') for port, type in in_ports.items(): lines.append('\t'*2 + port + '<tabs>: ' + type + ';\n') lines.append('\tEND RECORD;\n\n') else : for port, type in out_ports.items(): - lines.append('\t\t' + slave_ram_name.upper() + '_OUT.' + port + '<tabs>=>\n') + lines.append('\t\t' + mm_port_ram_name.upper() + '_OUT.' + port + '<tabs>=>\n') for port, type in in_ports.items(): - lines.append('\t\t' + slave_ram_name.upper() + '_IN.' + port + '<tabs>=>\n') + lines.append('\t\t' + mm_port_ram_name.upper() + '_IN.' + port + '<tabs>=>\n') return(lines) @@ -518,7 +518,7 @@ class Slave(object): lines = [] write_record = 0 field_list = regGroup.fields - nof_inst = regGroup.number_of_slaves() + nof_inst = regGroup.number_of_mm_ports() for field in field_list: if field.access_mode() == mode: write_record = 1 @@ -544,7 +544,7 @@ class Slave(object): return(lines) - def slave_ports(self): + def mm_ports(self): lines = [] # for field in field_list: reg_name = self.regGroup.name() @@ -565,33 +565,33 @@ class Slave(object): lines = tab_aligned(lines) return(lines) - def signal_declarations(self, regGroup, ram=False, nof_slaves=1, regGroup_name=None): + def signal_declarations(self, regGroup, ram=False, nof_mm_ports=1, regGroup_name=None): lines = [] reg_name = regGroup.name() - ro_dict = {'postfix' : 'in_reg', 'type': ': STD_LOGIC_VECTOR(<>.nof_slaves*<>.dat_w*<>.nof_dat-1 downto 0);\n'} - rw_dict = {'postfix' : 'out_reg', 'type': ': STD_LOGIC_VECTOR(<>.nof_slaves*<>.dat_w*<>.nof_dat-1 downto 0);\n'} - pw_dict = {'postfix' : 'pulse_write', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves*<>.nof_dat-1 downto 0);\n'} - pr_dict = {'postfix' : 'pulse_read', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves*<>.nof_dat-1 downto 0);\n'} + ro_dict = {'postfix' : 'in_reg', 'type': ': STD_LOGIC_VECTOR(<>.nof_mm_ports*<>.dat_w*<>.nof_dat-1 downto 0);\n'} + rw_dict = {'postfix' : 'out_reg', 'type': ': STD_LOGIC_VECTOR(<>.nof_mm_ports*<>.dat_w*<>.nof_dat-1 downto 0);\n'} + pw_dict = {'postfix' : 'pulse_write', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports*<>.nof_dat-1 downto 0);\n'} + pr_dict = {'postfix' : 'pulse_read', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports*<>.nof_dat-1 downto 0);\n'} rd_dict = {'postfix' : 'rd_dat', 'type' : ': STD_LOGIC_VECTOR(<>.dat_w-1 downto 0);\n'} rv_dict = {'postfix' : 'rd_val', 'type' : ': STD_LOGIC;\n'} - rb_dict = {'postfix' : 'rd_busy', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} + rb_dict = {'postfix' : 'rd_busy', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} wv_dict = {'postfix' : 'wr_val', 'type' : ': STD_LOGIC;\n'} - wb_dict = {'postfix' : 'wr_busy', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} + wb_dict = {'postfix' : 'wr_busy', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} - wr_en_dict = {'postfix' : 'wr_en', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} + wr_en_dict = {'postfix' : 'wr_en', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} wr_en_vec_dict = {'postfix' : 'wr_en_vec', 'type' : ': STD_LOGIC_VECTOR(0 downto 0);\n'} - wr_val_dict = {'postfix' : 'wr_val', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} + wr_val_dict = {'postfix' : 'wr_val', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} wr_val_vec_dict = {'postfix' : 'wr_val_vec', 'type' : ': STD_LOGIC_VECTOR(0 downto 0);\n'} adr_dict = {'postfix' : 'adr', 'type' : ': STD_LOGIC_VECTOR(<>.adr_w-1 downto 0);\n'} - rd_en_dict = {'postfix' : 'rd_en', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} - rd_dat_dict = {'postfix' : 'rd_dat', 'type' : ': t_slv_'+str(regGroup.width())+'_arr(0 to <>.nof_slaves-1);\n' if nof_slaves > 1 else ': STD_LOGIC_VECTOR(<>.dat_w-1 downto 0);\n'} - rd_val_dict = {'postfix' : 'rd_val', 'type' : ': STD_LOGIC_VECTOR(<>.nof_slaves-1 downto 0);\n' if nof_slaves > 1 else ': STD_LOGIC;\n'} + rd_en_dict = {'postfix' : 'rd_en', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} + rd_dat_dict = {'postfix' : 'rd_dat', 'type' : ': t_slv_'+str(regGroup.width())+'_arr(0 to <>.nof_mm_ports-1);\n' if nof_mm_ports > 1 else ': STD_LOGIC_VECTOR(<>.dat_w-1 downto 0);\n'} + rd_val_dict = {'postfix' : 'rd_val', 'type' : ': STD_LOGIC_VECTOR(<>.nof_mm_ports-1 downto 0);\n' if nof_mm_ports > 1 else ': STD_LOGIC;\n'} if ram : # if regGroup.access_mode() == "RW": dict_list = [wr_en_dict, wr_val_dict, adr_dict, rd_en_dict, rd_dat_dict, rd_val_dict] - if nof_slaves == 1 : + if nof_mm_ports == 1 : dict_list.extend([wr_en_vec_dict, wr_val_vec_dict]) reg_name = regGroup_name + '_' + reg_name # else : # RO @@ -607,32 +607,32 @@ class Slave(object): def input_statements(self, regGroup): lines = [] field_list = regGroup.fields - if regGroup.number_of_slaves() > 1 : - lines.append('\t' + regGroup.name() + '_nof_slaves_fb: FOR i in 0 to c_mm_' + regGroup.name() + '_reg.nof_slaves-1 GENERATE\n\n') - slave_offset = 'c_mm_<reg_name>_reg.dat_w*c_mm_<reg_name>_reg.nof_dat*i + ' + if regGroup.number_of_mm_ports() > 1 : + lines.append('\t' + regGroup.name() + '_nof_mm_ports_fb: FOR i in 0 to c_mm_' + regGroup.name() + '_reg.nof_mm_ports-1 GENERATE\n\n') + mm_port_offset = 'c_mm_<reg_name>_reg.dat_w*c_mm_<reg_name>_reg.nof_dat*i + ' tab_no = 2 index = '(i)' else : - slave_offset = '' + mm_port_offset = '' tab_no = 1 index = '' for field in field_list: upper_bit = field.bit_offset() + field.width() - 1 if field.side_effect() != 'PW': # and field.side_effect() != 'PR': - mapped_field = regGroup.name().upper() + '_FIELDS_RO.' + field.name() + index if field.access_mode() == 'RO' else '<reg_name>_out_reg('+slave_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ((' downto '+slave_offset+'c_byte_w*'+ str(field.address_offset()) + ('+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '')) if field.width() > 1 else '') + ')' # doesn't test for other cases WO etc. + mapped_field = regGroup.name().upper() + '_FIELDS_RO.' + field.name() + index if field.access_mode() == 'RO' else '<reg_name>_out_reg('+mm_port_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ((' downto '+mm_port_offset+'c_byte_w*'+ str(field.address_offset()) + ('+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '')) if field.width() > 1 else '') + ')' # doesn't test for other cases WO etc. else : mapped_field = '\'' + '0'*field.width() + '\'' if field.width() > 1 : mapped_field = mapped_field.replace('\'', '\"') if field.width() > 1: - line = '\t'*tab_no + '<reg_name>_in_reg('+slave_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '' ) + ' downto '+slave_offset+'c_byte_w*'+ str(field.address_offset()) + ('+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '') + ')<tabs><= ' + mapped_field + ';\n' + line = '\t'*tab_no + '<reg_name>_in_reg('+mm_port_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '' ) + ' downto '+mm_port_offset+'c_byte_w*'+ str(field.address_offset()) + ('+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '') + ')<tabs><= ' + mapped_field + ';\n' lines.append(line) # lines.append('\t\t' + regGroup.name() + '_in_reg( + c_mm_' + regGroup.name() + '_reg.dat_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '' ) + ' downto c_mm_reg.dat_w*'+ str(field.address_offset()) + ('+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '') + ') <= ' + mapped_field + ';\n') else : - line = '\t'*tab_no + regGroup.name() + '_in_reg('+slave_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ')<tabs><= ' + mapped_field + ';\n' + line = '\t'*tab_no + regGroup.name() + '_in_reg('+mm_port_offset+'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ')<tabs><= ' + mapped_field + ';\n' lines.append(line) - if regGroup.number_of_slaves() > 1 : + if regGroup.number_of_mm_ports() > 1 : lines.append('\n\tEND GENERATE;\n\n') lines = [line.replace('<reg_name>', regGroup.name()) for line in lines] lines = tab_aligned(lines) @@ -641,15 +641,15 @@ class Slave(object): def output_statements(self, regGroup): lines = [] field_list = regGroup.fields - if regGroup.number_of_slaves() > 1: - lines.append('\t' + regGroup.name() + '_nof_slaves_outputs: FOR i in 0 to c_mm_' + regGroup.name() + '_reg.nof_slaves-1 GENERATE\n\n') - slave_offset = 'c_mm_<reg_name>_reg.dat_w*c_mm_<reg_name>_reg.nof_dat*i + ' - slave_offset_pulse = 'c_mm_<reg_name>_reg.nof_dat*i + ' + if regGroup.number_of_mm_ports() > 1: + lines.append('\t' + regGroup.name() + '_nof_mm_ports_outputs: FOR i in 0 to c_mm_' + regGroup.name() + '_reg.nof_mm_ports-1 GENERATE\n\n') + mm_port_offset = 'c_mm_<reg_name>_reg.dat_w*c_mm_<reg_name>_reg.nof_dat*i + ' + mm_port_offset_pulse = 'c_mm_<reg_name>_reg.nof_dat*i + ' tab_no = 2 index = '(i)' else : - slave_offset = '' - slave_offset_pulse = '' + mm_port_offset = '' + mm_port_offset_pulse = '' tab_no = 1 index = '' for field in field_list: @@ -658,19 +658,19 @@ class Slave(object): side_effect = '' # multiple side effects need to be supported if 'P' in field.side_effect(): - side_effect_string = '<reg_name>_pulse_<>(' + slave_offset_pulse + str(word_wise(field.address_offset())) + side_effect_string = '<reg_name>_pulse_<>(' + mm_port_offset_pulse + str(word_wise(field.address_offset())) side_effect_string = (side_effect_string + ')') if field.width() == 1 else '(' + str(field.width()-1) + ' downto 0 => ' + side_effect_string + '))' if 'PW' in field.side_effect() and 'PR' in field.side_effect(): side_effect = '(' + side_effect_string.replace('<>', 'write') + ' OR ' + (side_effect_string.replace('<>', 'read')) + ') AND ' else : side_effect = side_effect_string.replace('<>', 'write' if 'PW' in field.side_effect() else 'read') + ' AND ' if field.width() > 1: - lines.append(tab_no*'\t' + regGroup.name().upper()+'_FIELDS_RW.' + field.name() + index+'<tabs><= '+side_effect+'<reg_name>_out_reg(' + slave_offset + 'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ' downto '+ slave_offset +'c_byte_w*'+ str(field.address_offset()) +( '+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '') + ');\n') + lines.append(tab_no*'\t' + regGroup.name().upper()+'_FIELDS_RW.' + field.name() + index+'<tabs><= '+side_effect+'<reg_name>_out_reg(' + mm_port_offset + 'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ' downto '+ mm_port_offset +'c_byte_w*'+ str(field.address_offset()) +( '+' + str(field.bit_offset()) if field.bit_offset() is not 0 else '') + ');\n') else : - lines.append(tab_no*'\t' + regGroup.name().upper()+'_FIELDS_RW.' + field.name() + index+'<tabs><= '+side_effect+'<reg_name>_out_reg(' + slave_offset + 'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ');\n') + lines.append(tab_no*'\t' + regGroup.name().upper()+'_FIELDS_RW.' + field.name() + index+'<tabs><= '+side_effect+'<reg_name>_out_reg(' + mm_port_offset + 'c_byte_w*' + str(field.address_offset()) + ('+' + str(upper_bit) if upper_bit is not 0 else '') + ');\n') if field.access_mode() == 'RO': if field.side_effect() == 'PR': - side_effect_string = '<reg_name>_pulse_read(' + slave_offset_pulse + str(word_wise(field.address_offset())) + ')' + side_effect_string = '<reg_name>_pulse_read(' + mm_port_offset_pulse + str(word_wise(field.address_offset())) + ')' lines.append(tab_no*'\t' + regGroup.name().upper()+'_FIELDS_PR.' + field.name() + index+'<tabs><= '+side_effect_string + ';\n') # lines.append('\n') @@ -679,7 +679,7 @@ class Slave(object): # lines.append('\t\t' + regGroup.name().upper() + '_PULSE_R.'+ field.name() + '(i)<tabs><= <reg_name>_pulse_read(' + str(field.address_offset()) + ');\n') # if field.side_effect() == 'PW': # lines.append('\t\t' + regGroup.name().upper() + '_PULSE_W.'+ field.name() + '(i)<tabs><= <reg_name>_pulse_write(' + str(field.address_offset()) + ');\n') - if regGroup.number_of_slaves() > 1 : + if regGroup.number_of_mm_ports() > 1 : lines.append('\n\tEND GENERATE;\n\n') lines = [line.replace('<reg_name>', regGroup.name()) for line in lines] lines = tab_aligned(lines) @@ -689,29 +689,29 @@ class Slave(object): def instantiate_rams(self): lines = [] for ram in self.regGroup.rams: - # logger.info("slave %s ram %s ceillog2(base_address)%d(%d) ceillog2(nof_dat)%d (%d)", regGroup.name(), ram.name(), ram.base_address(), ceil_log2(ram.base_address()) if ram.base_address() != 0 else 0, ram.number_of_fields(), ceil_log2(ram.number_of_fields())) + # logger.info("MM port %s ram %s ceillog2(base_address)%d(%d) ceillog2(nof_dat)%d (%d)", regGroup.name(), ram.name(), ram.base_address(), ceil_log2(ram.base_address()) if ram.base_address() != 0 else 0, ram.number_of_fields(), ceil_log2(ram.number_of_fields())) sublines = [] - sublines.append(('\t<>_adr <= wr_adr(c_mm_<>_ram.adr_w-1 downto 0) WHEN <>_wr_en ' + ('= \'1\'' if self.regGroup.number_of_slaves() == 1 else '/= (<>_wr_en\'range => \'0\')')+' ELSE\n\t\t\t\trd_adr(c_mm_<>_ram.adr_w-1 downto 0);\n\n ').replace('<>', self.regGroup.name() + '_' + ram.name())) - if self.regGroup.number_of_slaves() > 1: - sublines.append(('\t<>_' + ram.name() + '_gen: FOR i in 0 to c_mm_<>_reg.nof_slaves-1 GENERATE\n').replace('<>', self.regGroup.name())) + sublines.append(('\t<>_adr <= wr_adr(c_mm_<>_ram.adr_w-1 downto 0) WHEN <>_wr_en ' + ('= \'1\'' if self.regGroup.number_of_mm_ports() == 1 else '/= (<>_wr_en\'range => \'0\')')+' ELSE\n\t\t\t\trd_adr(c_mm_<>_ram.adr_w-1 downto 0);\n\n ').replace('<>', self.regGroup.name() + '_' + ram.name())) + if self.regGroup.number_of_mm_ports() > 1: + sublines.append(('\t<>_' + ram.name() + '_gen: FOR i in 0 to c_mm_<>_reg.nof_mm_ports-1 GENERATE\n').replace('<>', self.regGroup.name())) with open(os.path.join(self.tmpl_dir, 'template_common_ram_rw_rw.vho'), 'r') as inst_file: for subline in inst_file: - for tag, replace_string in {'<field_name>' : self.regGroup.name() + '_' + ram.name(), '<FIELD_NAME>': (self.regGroup.name() + '_' + ram.name()).upper(), '<reg_name>': self.regGroup.name(), '(i)' : '' if self.regGroup.number_of_slaves() == 1 else '(i)', '+ i' : '' if self.regGroup.number_of_slaves() == 1 else '+ i'}.items(): + for tag, replace_string in {'<field_name>' : self.regGroup.name() + '_' + ram.name(), '<FIELD_NAME>': (self.regGroup.name() + '_' + ram.name()).upper(), '<reg_name>': self.regGroup.name(), '(i)' : '' if self.regGroup.number_of_mm_ports() == 1 else '(i)', '+ i' : '' if self.regGroup.number_of_mm_ports() == 1 else '+ i'}.items(): subline = subline.replace(tag, replace_string) - if self.regGroup.number_of_slaves() > 1: + if self.regGroup.number_of_mm_ports() > 1: subline = '\t' + subline sublines.append(subline) - if self.regGroup.number_of_slaves() > 1: + if self.regGroup.number_of_mm_ports() > 1: sublines.append('\tEND GENERATE;\n\n') with open(os.path.join(self.tmpl_dir, 'template_common_pipeline.vho'), 'r') as inst_file: # sublines.extend(subline.replace('<field_name>', regGroup.name() + '_' + ram.name()) for subline in inst_file) for subline in inst_file: - if '<nof_slaves>' in subline: - if self.regGroup.number_of_slaves() == 1: - subline = subline.replace('<nof_slaves>', '') + if '<nof_mm_ports>' in subline: + if self.regGroup.number_of_mm_ports() == 1: + subline = subline.replace('<nof_mm_ports>', '') sublines.append(subline.replace('<field_name>', self.regGroup.name() + '_' + ram.name())) else: - subline = subline.replace('<_vec>', '_vec' if self.regGroup.number_of_slaves() == 1 else '') + subline = subline.replace('<_vec>', '_vec' if self.regGroup.number_of_mm_ports() == 1 else '') sublines.append(subline.replace('<field_name>', self.regGroup.name() + '_' + ram.name())) lines.extend(sublines) return(lines) @@ -723,7 +723,7 @@ class Slave(object): sublines = [] with open(tmpl_file, 'r') as inst_file: for subline in inst_file: - for tag, replace_string in {'<reg_name>' : self.regGroup.name() + '_' + ram.name(), '<reg_ram>': 'ram', '<adr_w>' : str(ceil_log2(ram.number_of_fields())), '<nof_dat>' : str(ram.number_of_fields()), '<nof_slaves>' : self.regGroup.number_of_slaves(), '<addr_base>' : str(int(ram.base_address()/WORD_SIZE)), '<dat_w>' : ram.width()}.items(): + for tag, replace_string in {'<reg_name>' : self.regGroup.name() + '_' + ram.name(), '<reg_ram>': 'ram', '<adr_w>' : str(ceil_log2(ram.number_of_fields())), '<nof_dat>' : str(ram.number_of_fields()), '<nof_mm_ports>' : self.regGroup.number_of_mm_ports(), '<addr_base>' : str(int(ram.base_address()/WORD_SIZE)), '<dat_w>' : ram.width()}.items(): subline = subline.replace(tag, str(replace_string)) if 'STD_LOGIC_VECTOR' not in subline: sublines.append(subline) @@ -742,8 +742,8 @@ class Slave(object): def read_write_vals(self, i, nof_regs, read_write='rd'): lines = [] for ram in self.regGroup.rams: - for j in range(self.regGroup.number_of_slaves()): - lines.append('\t\t' + self.regGroup.name() + '_' + ram.name() + '_' + read_write + '_val' + ('('+str(j)+')' if self.regGroup.number_of_slaves() > 1 else '') + (';' if (i == self.regGroup.number_of_slaves()-1 and ram == self.regGroup.rams[-1] and len(self.regGroup.fields) == 0) else ' OR\n')) + for j in range(self.regGroup.number_of_mm_ports()): + lines.append('\t\t' + self.regGroup.name() + '_' + ram.name() + '_' + read_write + '_val' + ('('+str(j)+')' if self.regGroup.number_of_mm_ports() > 1 else '') + (';' if (i == self.regGroup.number_of_mm_ports()-1 and ram == self.regGroup.rams[-1] and len(self.regGroup.fields) == 0) else ' OR\n')) lines.append('\t\t' + self.regGroup.name() + '_' + read_write + '_val' + (';\n\n' if i == nof_regs-1 else ' OR ')) return lines @@ -759,30 +759,30 @@ class Slave(object): for ram in regGroup.rams: partial = 32 - ram.width() others = '' if partial == 0 else '\'0\' & ' if partial == 1 else '\"'+'0'*partial+'\" & ' - for j in range(regGroup.number_of_slaves()): - lines.append('\t'*2 + others + regGroup.name() + '_' + ram.name() + '_rd_dat' + ('('+str(j)+')' if regGroup.number_of_slaves() > 1 else '') + (';' if (i == regGroup.number_of_slaves()-1 and ram == regGroup.rams[-1] and len(regGroup.fields) == 0) else ' WHEN '+regGroup.name() + '_' + ram.name()+'_rd_val<> = \'1\' ELSE\n'.replace('<>', '(' + str(j) + ')' if regGroup.number_of_slaves() > 1 else ''))) + for j in range(regGroup.number_of_mm_ports()): + lines.append('\t'*2 + others + regGroup.name() + '_' + ram.name() + '_rd_dat' + ('('+str(j)+')' if regGroup.number_of_mm_ports() > 1 else '') + (';' if (i == regGroup.number_of_mm_ports()-1 and ram == regGroup.rams[-1] and len(regGroup.fields) == 0) else ' WHEN '+regGroup.name() + '_' + ram.name()+'_rd_val<> = \'1\' ELSE\n'.replace('<>', '(' + str(j) + ')' if regGroup.number_of_mm_ports() > 1 else ''))) lines.append('\t'*2 + regGroup.name() + '_rd_dat' + (';\n\n' if i == nof_regs-1 else ' WHEN ' + regGroup.name() + '_rd_val = \'1\' ELSE\n')) return lines - # def fix_mem_size(self, slaveSettings, slave_type): # should be in peripheral.py - # if slaveSettings.() < 32: - # logger.warning('Updating %s width %d to 32 (minimum data width)', slave_type, slaveSettings.width()) - # slaveSettings.width(32) + # def fix_mem_size(self, mmPortSettings, mm_port_type): # should be in peripheral.py + # if mmPortSettings.() < 32: + # logger.warning('Updating %s width %d to 32 (minimum data width)', mm_port_type, mmPortSettings.width()) + # mmPortSettings.width(32) - # if slave_type.lower() == 'ram': - # if slaveSettings.address_length() < 1024: - # slaveSettings.depth(1024) + # if mm_port_type.lower() == 'ram': + # if mmPortSettings.address_length() < 1024: + # mmPortSettings.depth(1024) - # if slaveSettings.width_b() == slaveSettings.width() : - # self.depth_b = slaveSettings.address_length() + # if mmPortSettings.width_b() == mmPortSettings.width() : + # self.depth_b = mmPortSettings.address_length() # else : - # self.depth_b = slaveSettings.address_length() / (slaveSettings.width_b()/slaveSettings.width()) + # self.depth_b = mmPortSettings.address_length() / (mmPortSettings.width_b()/mmPortSettings.width()) # if self.depth_b < 1024: # logger.warning('BRAM port B violation: BRAM controller requires minimum depth of 1k') - # elif slave_type.lower() == 'fifo': - # if slaveSettings.address_length() < 512: - # slaveSettings.depth(512) + # elif mm_port_type.lower() == 'fifo': + # if mmPortSettings.address_length() < 512: + # mmPortSettings.depth(512) # return diff --git a/peripherals/demo.peripheral.yaml b/peripherals/demo.peripheral.yaml index bcd2ea5c43e476df924b213baeaf1b89df29315a..c0ff1cc3e68ed80fdfd9648fe567b213114da1e5 100644 --- a/peripherals/demo.peripheral.yaml +++ b/peripherals/demo.peripheral.yaml @@ -9,17 +9,17 @@ peripherals: - peripheral_name : periph1 peripheral_description : "Registers associated with Publish/Subscribe protocol block" - slave_ports: - - slave_name : client - slave_type : FIFO + mm_ports: + - mm_port_name : client + mm_port_type : FIFO fields: - - field_name : data width : 32 number_of_fields : 1000 access_mode : WO - - slave_name : test - slave_type : RAM + - mm_port_name : test + mm_port_type : RAM fields: - - field_name : weight width : 32 @@ -27,10 +27,10 @@ peripherals: access_mode : RW number_of_fields : 2000 - - slave_name : client - slave_type : reg - number_of_slaves : 4 - slave_description : "Registers associated with Subscription client" + - mm_port_name : client + mm_port_type : reg + number_of_mm_ports : 4 + mm_port_description : "Registers associated with Subscription client" fields: ################################# - - field_name : destination_ip @@ -96,10 +96,10 @@ peripherals: field_description : "An event queue overflow conditon has occured. Reset on acknowledge" ################################# - - slave_name : broadcast - slave_type : reg - number_of_slaves : 3 - slave_description : "Control Register for broadcast client" + - mm_port_name : broadcast + mm_port_type : reg + number_of_mm_ports : 3 + mm_port_description : "Control Register for broadcast client" fields: - control: - field_name : acknowledge @@ -120,4 +120,4 @@ peripherals: # number_of_fields : 100 # - - field_name : ram5 # number_of_fields : 500 - \ No newline at end of file + diff --git a/peripherals/example.peripheral.yaml b/peripherals/example.peripheral.yaml index eea3ccf694e5aa3a0358c26c646c577136c007d2..a3532357302291562e92a753b0ea6b9af2d5377c 100644 --- a/peripherals/example.peripheral.yaml +++ b/peripherals/example.peripheral.yaml @@ -9,12 +9,12 @@ peripherals: - peripheral_name : periph1 # name used in register module and documentation peripheral_description : "periph1 is the 1st peripheral in the example peripheral library" - slave_ports: - - slave_name : - slave_type : REG # or REG_IP when firmware generation not desired - slave_protocol : # optional, use intended for slave type REG_IP ONLY - number_of_slaves : # optional, default: 1 - slave_description : # Custom string for documentation, contained in quotation marks + mm_ports: + - mm_port_name : + mm_port_type : REG # or REG_IP when firmware generation not desired + mm_port_protocol : # optional, use intended for mm_port type REG_IP ONLY + number_of_mm_ports : # optional, default: 1 + mm_port_description : # Custom string for documentation, contained in quotation marks fields: ################################# Fully specified field with all key options - - field_name : # custom string, limit length where possible @@ -40,10 +40,10 @@ peripherals: field_description : ################################# - - slave_name : # custom string - slave_type : RAM - number_of_slaves : # optional, default: 1 - slave_description : # custom string in quotation marks + - mm_port_name : # custom string + mm_port_type : RAM + number_of_mm_ports : # optional, default: 1 + mm_port_description : # custom string in quotation marks fields : ################################# RAM is described by only one field - - field_name : data # field name not important @@ -57,10 +57,10 @@ peripherals: field_description : # custom string ################################# - - slave_name : # custom string - slave_type : FIFO - number_of_slaves : # optional, default: 1 - slave_description : # custom string in quotation marks + - mm_port_name : # custom string + mm_port_type : FIFO + number_of_mm_ports : # optional, default: 1 + mm_port_description : # custom string in quotation marks fields : ################################# FIFO is described by only one field - - field_name : data # field name not important diff --git a/peripherals/template.peripheral.yaml b/peripherals/template.peripheral.yaml index b82808d440bd61f6229946ff79207c5a78ebba7a..233298a94c29fcceed17d7a8babd96183153c943 100644 --- a/peripherals/template.peripheral.yaml +++ b/peripherals/template.peripheral.yaml @@ -9,12 +9,12 @@ peripherals: - peripheral_name : periph1 # name used in register module and documentation peripheral_description : "periph1 is the 1st peripheral in the example peripheral library" - slave_ports: - - slave_name : # custom string - slave_type : REG # or REG_IP when firmware generation not desired - slave_protocol : # optional, use intended for slave type REG_IP ONLY - number_of_slaves : # optional, default: 1 - slave_description : # Custom string for documentation, contained in quotation marks + mm_ports: + - mm_port_name : # custom string + mm_port_type : REG # or REG_IP when firmware generation not desired + mm_port_protocol : # optional, use intended for mm_port type REG_IP ONLY + number_of_mm_ports : # optional, default: 1 + mm_port_description : # Custom string for documentation, contained in quotation marks fields: ################################# Fully specified field with all key options - - field_name : # custom string, limit length where possible @@ -40,10 +40,10 @@ peripherals: field_description : ################################# - - slave_name : # custom string - slave_type : RAM - number_of_slaves : # optional, default: 1 - slave_description : # custom string in quotation marks + - mm_port_name : # custom string + mm_port_type : RAM + number_of_mm_ports : # optional, default: 1 + mm_port_description : # custom string in quotation marks fields : ################################# RAM is described by only one field - - field_name : data # field name not important @@ -57,10 +57,10 @@ peripherals: field_description : # custom string ################################# - - slave_name : # custom string - slave_type : FIFO - number_of_slaves : # optional, default: 1 - slave_description : # custom string in quotation marks + - mm_port_name : # custom string + mm_port_type : FIFO + number_of_mm_ports : # optional, default: 1 + mm_port_description : # custom string in quotation marks fields : ################################# FIFO is described by only one field - - field_name : data # field name not important diff --git a/py_args_lib/fpga.py b/py_args_lib/fpga.py index e509cfd69916a1c424272cced625303b113ad9d3..4c829a6122127bde393d62eeab00729f21e7c4e4 100644 --- a/py_args_lib/fpga.py +++ b/py_args_lib/fpga.py @@ -65,7 +65,7 @@ class FPGA(object): self.address_map = collections.OrderedDict() logger.debug("***FPGA object instantiation: creating for %s", file_path_name) - # EK FIXME: a missing required key does not give a clear error message (e.g. missing slave_port_names) + # EK FIXME: a missing required key does not give a clear error message (e.g. missing mm_port_names) # EK FIXME: need to specify board_name explicitely (via e.g. board_name cmd line argument, or buildset_name like with RadioHDL) instead of derive from a dir name. if 'boards' in self.file_path_name: @@ -169,10 +169,10 @@ class FPGA(object): value = parameter_set['value'] peripheral_from_lib.parameter(key=name, val=self._eval(value)) - if 'slave_port_names' in peripheral_config: - logger.debug("slave_port_names=%s", peripheral_config['slave_port_names']) - for slave_nr, slave_port_name in enumerate(peripheral_config['slave_port_names']): - peripheral_from_lib.set_user_defined_slavename(slave_nr, slave_port_name) + if 'mm_port_names' in peripheral_config: + logger.debug("mm_port_names=%s", peripheral_config['mm_port_names']) + for mm_port_nr, mm_port_name in enumerate(peripheral_config['mm_port_names']): + peripheral_from_lib.set_user_defined_mm_port_name(mm_port_nr, mm_port_name) if 'lock_base_address' in peripheral_config: logger.debug("lock_base_address=%s", str(peripheral_config['lock_base_address'])) @@ -200,7 +200,7 @@ class FPGA(object): peripheral_config.eval_peripheral() if self.use_avalon_base_addr is True: - logger.debug("Use qsys/sopc base addresses for the slaves") + logger.debug("Use qsys/sopc base addresses for the mm_ports") if self.read_avalon_address_map() == -1: logger.debug("Now trying auto_create") self.create_address_map() @@ -270,11 +270,11 @@ class FPGA(object): p1 = 0 p1 = data.find('<key>data_master</key>', p1) p1 = data.find('address-map', p1) - p1 = data.find('slave', p1) + p1 = data.find('mm_port', p1) p2 = data.find('/address-map', p1) addr_data = data[p1:p2] addr_data = addr_data.replace('/><','') - addr_data = addr_data.replace('slave name', 'slave_name') + addr_data = addr_data.replace('mm_port name', 'mm_port_name') addr_data = addr_data.replace("'", '') addr_data = addr_data.split(';') @@ -289,10 +289,10 @@ class FPGA(object): if v_end in v: v = v.replace(v_end, '') perip_info[k] = v - perips_info[perip_info['slave_name']] = perip_info + perips_info[perip_info['mm_port_name']] = perip_info byte_address = int(perip_info['start'][2:], 16) - avalon_base_addr[perip_info['slave_name']] = byte_address + avalon_base_addr[perip_info['mm_port_name']] = byte_address print("avalon baseadres", avalon_base_addr) for peripheral in self.peripherals.values(): @@ -300,81 +300,81 @@ class FPGA(object): # peripheral.name()[:20], lowest_free_addr, peripheral.reg_len) # TODO for periph_num in range(peripheral.number_of_peripherals()): - for slave in peripheral.slaves: + for mmport in peripheral.mm_ports: base_addr = -1 - if slave.user_defined_name(): + if mmport.user_defined_name(): try: - base_addr = avalon_base_addr[slave.user_defined_name()] - slave.base_address(base_addr) + base_addr = avalon_base_addr[mmport.user_defined_name()] + mmport.base_address(base_addr) except: - logger.warn("base address for username '%s' not found", slave.user_defined_name()) + logger.warn("base address for username '%s' not found", mmport.user_defined_name()) - addr_map_name = [peripheral.name(), slave.name()] + addr_map_name = [peripheral.name(), mmport.name()] - if isinstance(slave, Register) and not getattr(slave, 'isIP', False): + if isinstance(mmport, Register) and not getattr(mmport, 'isIP', False): addr_map_name.append('reg') - ram_span = int(slave.base_address() - slave.rams[0].base_address()) if any(slave.rams) else 0 - slave_span = int(slave.address_length() * slave.number_of_slaves() * max(ram_span, 1)) + ram_span = int(mmport.base_address() - mmport.rams[0].base_address()) if any(mmport.rams) else 0 + mm_port_span = int(mmport.address_length() * mmport.number_of_mm_ports() * max(ram_span, 1)) - logger.debug('REG-not-IP slave.address_len=%d * slave.number_of_slaves=%d * ram_span=%d', slave.address_length(), slave.number_of_slaves(), ram_span) - logger.debug("REG Slave %s_%s has span 0x%x", peripheral.name(), slave.name() , slave_span) + logger.debug('REG-not-IP mmport.address_len=%d * mmport.number_of_mm_ports=%d * ram_span=%d', mmport.address_length(), mmport.number_of_mm_ports(), ram_span) + logger.debug("REG MM port %s_%s has span 0x%x", peripheral.name(), mmport.name() , mm_port_span) if peripheral.number_of_peripherals() > 1: addr_map_name.append(str(periph_num)) - slave_port_name = '_'.join(addr_map_name) + mm_port_name = '_'.join(addr_map_name) - self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': 'LITE', - 'port_index': self.nof_lite, 'peripheral': peripheral, - 'periph_num': periph_num, 'slave': slave} - logger.debug("Register for %s has span 0x%x", peripheral.name(), slave_span) + self.address_map[mm_port_name] = {'base': base_addr, 'span': mm_port_span, 'type': 'LITE', + 'port_index': self.nof_lite, 'peripheral': peripheral, + 'periph_num': periph_num, 'mm_port': mmport} + logger.debug("Register for %s has span 0x%x", peripheral.name(), mm_port_span) - elif isinstance(slave, Register) and getattr(slave, 'isIP', False): + elif isinstance(mmport, Register) and getattr(mmport, 'isIP', False): addr_map_name.append('regip') - slave_span = int(ceil_pow2(max(slave.address_length() * slave.number_of_slaves(), 4096))) # slave.address_length()*slave.number_of_slaves()# + mm_port_span = int(ceil_pow2(max(mmport.address_length() * mmport.number_of_mm_ports(), 4096))) # mmport.address_length()*mmport.number_of_mm_ports()# - logger.debug('REG-IP slave.address_len=%d * slave.number_of_slaves=%d', slave.address_length(), slave.number_of_slaves()) - logger.debug("REG-IP Slave %s_%s has span 0x%x", peripheral.name(), slave.name() , slave_span) + logger.debug('REG-IP mmport.address_len=%d * mmport.number_of_mm_ports=%d', mmport.address_length(), mmport.number_of_mm_ports()) + logger.debug("REG-IP MM port %s_%s has span 0x%x", peripheral.name(), mmport.name() , mm_port_span) - slave_port_name = '_'.join(addr_map_name) + mm_port_name = '_'.join(addr_map_name) - self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': slave.protocol, - 'port_index': eval("self.nof_{}".format(slave.protocol.lower())), - 'peripheral': peripheral, 'periph_num': periph_num, 'slave': slave} + self.address_map[mm_port_name] = {'base': base_addr, 'span': mm_port_span, 'type': mmport.protocol, + 'port_index': eval("self.nof_{}".format(mmport.protocol.lower())), + 'peripheral': peripheral, 'periph_num': periph_num, 'mm_port': mmport} - elif isinstance(slave, RAM): + elif isinstance(mmport, RAM): addr_map_name.append('ram') - size_in_bytes = slave.address_length() * ceil_pow2(slave.number_of_slaves()) - slave_span = ceil_pow2(max(size_in_bytes, 4096)) + size_in_bytes = mmport.address_length() * ceil_pow2(mmport.number_of_mm_ports()) + mm_port_span = ceil_pow2(max(size_in_bytes, 4096)) - logger.debug("RAM Slave %s_%s has span 0x%x", peripheral.name(), slave.name() , slave_span) + logger.debug("RAM MM port %s_%s has span 0x%x", peripheral.name(), mmport.name() , mm_port_span) if peripheral.number_of_peripherals() > 1: addr_map_name.append(str(periph_num)) - slave_port_name = '_'.join(addr_map_name) + mm_port_name = '_'.join(addr_map_name) - self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': 'FULL', - 'port_index': self.nof_full, 'peripheral': peripheral, - 'periph_num': periph_num, 'slave': slave} + self.address_map[mm_port_name] = {'base': base_addr, 'span': mm_port_span, 'type': 'FULL', + 'port_index': self.nof_full, 'peripheral': peripheral, + 'periph_num': periph_num, 'mm_port': mmport} - elif isinstance(slave, FIFO): + elif isinstance(mmport, FIFO): addr_map_name.append('fifo') - size_in_bytes = slave.address_length() - slave_span = int(ceil_pow2(max(size_in_bytes, 4096))) + size_in_bytes = mmport.address_length() + mm_port_span = int(ceil_pow2(max(size_in_bytes, 4096))) - logger.debug("FIFO Slave %s_%s has span 0x%x", peripheral.name(), slave.name() , slave_span) + logger.debug("FIFO MM port %s_%s has span 0x%x", peripheral.name(), mmport.name() , mm_port_span) if peripheral.number_of_peripherals() > 1: addr_map_name.append(str(periph_num)) - slave_port_name = '_'.join(addr_map_name) + mm_port_name = '_'.join(addr_map_name) - self.address_map[slave_port_name] = {'base': base_addr, 'span': slave_span, 'type': 'FULL', - 'port_index': self.nof_full, 'access': slave.access_mode(), - 'peripheral': peripheral, 'periph_num': periph_num, 'slave': slave} + self.address_map[mm_port_name] = {'base': base_addr, 'span': mm_port_span, 'type': 'FULL', + 'port_index': self.nof_full, 'access': mmport.access_mode(), + 'peripheral': peripheral, 'periph_num': periph_num, 'mm_port': mmport} return 0 def create_address_map(self): @@ -401,93 +401,93 @@ class FPGA(object): peripheral.name()[:20], lowest_free_addr, peripheral.reg_len) # assigned_reg = False - # _nof_regs = sum([isinstance(slave, Register) for slave in peripheral.slaves]) + # _nof_regs = sum([isinstance(mmport, Register) for mmport in peripheral.mm_ports]) # _minus_regs = _nof_regs - 1 if _nof_regs > 0 else 0 - # _nof_slaves = len(peripheral.slaves) - _minus_regs + # _nof_mm_ports = len(peripheral.mm_ports) - _minus_regs for periph_num in range(peripheral.number_of_peripherals()): assigned_reg = False - for slave in peripheral.slaves: - if isinstance(slave, Register) and not getattr(slave, 'isIP', False): - slave_type = 'reg' - if assigned_reg is False: # calc for entire register slave port + for mmport in peripheral.mm_ports: + if isinstance(mmport, Register) and not getattr(mmport, 'isIP', False): + mm_port_type = 'reg' + if assigned_reg is False: # calc for entire register MM port reg_span = ceil_pow2(max(peripheral.reg_len, 4096)) lowest_free_addr = int(np.ceil(lowest_free_addr/reg_span)*reg_span) register_base = lowest_free_addr else : self.nof_lite = self.nof_lite - 1 - lowest_free_addr = register_base + (slave.base_address() if not any(slave.rams) else slave.rams[0].base_address()) - ram_span = slave.base_address() - slave.rams[0].base_address() if any(slave.rams) else 0 - slave_span = slave.address_length() * slave.number_of_slaves() + ram_span + lowest_free_addr = register_base + (mmport.base_address() if not any(mmport.rams) else mmport.rams[0].base_address()) + ram_span = mmport.base_address() - mmport.rams[0].base_address() if any(mmport.rams) else 0 + mm_port_span = mmport.address_length() * mmport.number_of_mm_ports() + ram_span - _name_list = [peripheral.name(), slave.name(), slave_type] + _name_list = [peripheral.name(), mmport.name(), mm_port_type] if peripheral.number_of_peripherals() > 1: _name_list.append(str(periph_num)) - slave_port_name = '_'.join(_name_list) + mm_port_name = '_'.join(_name_list) - self.address_map[slave_port_name] = {'base': lowest_free_addr, 'span': slave_span, 'type': 'LITE', - 'port_index': self.nof_lite, 'peripheral': peripheral, - 'periph_num': periph_num, 'slave': slave} - logger.debug("Register for %s has span 0x%x", peripheral.name(), slave_span) - lowest_free_addr = lowest_free_addr + int(slave_span) + self.address_map[mm_port_name] = {'base': lowest_free_addr, 'span': mm_port_span, 'type': 'LITE', + 'port_index': self.nof_lite, 'peripheral': peripheral, + 'periph_num': periph_num, 'mm_port': mmport} + logger.debug("Register for %s has span 0x%x", peripheral.name(), mm_port_span) + lowest_free_addr = lowest_free_addr + int(mm_port_span) self.nof_lite = self.nof_lite + 1 assigned_reg = True - elif isinstance(slave, Register) and getattr(slave, 'isIP', False): - slave_type = 'regip' - slave_span = ceil_pow2(max(slave.address_length() * slave.number_of_slaves(), 4096)) # slave.address_length()*slave.number_of_slaves()# - lowest_free_addr = int(np.ceil(lowest_free_addr / slave_span) * slave_span) + elif isinstance(mmport, Register) and getattr(mmport, 'isIP', False): + mm_port_type = 'regip' + mm_port_span = ceil_pow2(max(mmport.address_length() * mmport.number_of_mm_ports(), 4096)) # mmport.address_length()*mmport.number_of_mm_ports()# + lowest_free_addr = int(np.ceil(lowest_free_addr / mm_port_span) * mm_port_span) - _name_list = [peripheral.name(), slave.name(), slave_type] - slave_port_name = '_'.join(_name_list) + _name_list = [peripheral.name(), mmport.name(), mm_port_type] + mm_port_name = '_'.join(_name_list) - self.address_map[slave_port_name] = {'base': lowest_free_addr, 'span': slave_span, 'type': slave.protocol, - 'port_index': eval("self.nof_{}".format(slave.protocol.lower())), - 'peripheral': peripheral, 'periph_num': periph_num, 'slave': slave} - if slave.protocol.lower() == 'lite': + self.address_map[mm_port_name] = {'base': lowest_free_addr, 'span': mm_port_span, 'type': mmport.protocol, + 'port_index': eval("self.nof_{}".format(mmport.protocol.lower())), + 'peripheral': peripheral, 'periph_num': periph_num, 'mm_port': mmport} + if mmport.protocol.lower() == 'lite': self.nof_lite = self.nof_lite + 1 else : self.nof_full = self.nof_full + 1 - lowest_free_addr = lowest_free_addr + slave_span + lowest_free_addr = lowest_free_addr + mm_port_span - elif isinstance(slave, RAM): - slave_type = 'ram' - size_in_bytes = slave.address_length() * ceil_pow2(slave.number_of_slaves()) - slave_span = ceil_pow2(max(size_in_bytes, 4096)) - logger.debug("Slave %s_%s has span 0x%x", peripheral.name(), slave.name() , slave_span) - # slave_name = slave.name() + ('_{}'.format(slave_no) if slave.number_of_slaves() >1 else '') - lowest_free_addr = int(np.ceil(lowest_free_addr / slave_span) * slave_span) + elif isinstance(mmport, RAM): + mm_port_type = 'ram' + size_in_bytes = mmport.address_length() * ceil_pow2(mmport.number_of_mm_ports()) + mm_port_span = ceil_pow2(max(size_in_bytes, 4096)) + logger.debug("MM port %s_%s has span 0x%x", peripheral.name(), mmport.name() , mm_port_span) + # mm_port_name = mmport.name() + ('_{}'.format(mm_port_no) if mmport.number_of_mm_ports() >1 else '') + lowest_free_addr = int(np.ceil(lowest_free_addr / mm_port_span) * mm_port_span) - _name_list = [peripheral.name(), slave.name(), slave_type] + _name_list = [peripheral.name(), mmport.name(), mm_port_type] if peripheral.number_of_peripherals() > 1: _name_list.append(str(periph_num)) - slave_port_name = '_'.join(_name_list) + mm_port_name = '_'.join(_name_list) - self.address_map[slave_port_name] = {'base': lowest_free_addr, 'span': slave_span, 'type': 'FULL', - 'port_index': self.nof_full, 'peripheral': peripheral, - 'periph_num': periph_num, 'slave': slave} + self.address_map[mm_port_name] = {'base': lowest_free_addr, 'span': mm_port_span, 'type': 'FULL', + 'port_index': self.nof_full, 'peripheral': peripheral, + 'periph_num': periph_num, 'mm_port': mmport} self.nof_full = self.nof_full + 1 - lowest_free_addr = lowest_free_addr + slave_span + lowest_free_addr = lowest_free_addr + mm_port_span - elif isinstance(slave, FIFO): - slave_type = 'fifo' - size_in_bytes = slave.address_length() - slave_span = ceil_pow2(max(size_in_bytes, 4096)) - for i in range(slave.number_of_slaves()): - lowest_free_addr = int(np.ceil(lowest_free_addr / slave_span) * slave_span) + elif isinstance(mmport, FIFO): + mm_port_type = 'fifo' + size_in_bytes = mmport.address_length() + mm_port_span = ceil_pow2(max(size_in_bytes, 4096)) + for i in range(mmport.number_of_mm_ports()): + lowest_free_addr = int(np.ceil(lowest_free_addr / mm_port_span) * mm_port_span) - _name_list = [peripheral.name(), slave.name(), slave_type] + _name_list = [peripheral.name(), mmport.name(), mm_port_type] if peripheral.number_of_peripherals() > 1: _name_list.append(str(periph_num)) - slave_port_name = '_'.join(_name_list) + mm_port_name = '_'.join(_name_list) - self.address_map[slave_port_name] = {'base': lowest_free_addr, 'span': slave_span, 'type': 'FULL', - 'port_index': self.nof_full, 'access': slave.access_mode(), - 'peripheral': peripheral, 'periph_num': periph_num, 'slave': slave} + self.address_map[mm_port_name] = {'base': lowest_free_addr, 'span': mm_port_span, 'type': 'FULL', + 'port_index': self.nof_full, 'access': mmport.access_mode(), + 'peripheral': peripheral, 'periph_num': periph_num, 'mm_port': mmport} self.nof_full = self.nof_full + 1 - lowest_free_addr = lowest_free_addr + slave_span + lowest_free_addr = lowest_free_addr + mm_port_span - if slave_span > 65536: - logger.error("Slave %s has slave span %d. Maximum slave span in Vivado Address Editor is 64kB", slave.name(), slave_span) + if mm_port_span > 65536: + logger.error("MM port %s has mm_port_span %d. Maximum mm_port_span in Vivado Address Editor is 64kB", mmport.name(), mm_port_span) sys.exit() def show_overview(self): @@ -505,9 +505,9 @@ class FPGA(object): else: logger.debug(" %-20s %s", key, str(val)) logger.debug("- FPGA Address Map:") - for slave_name, attributes in self.address_map.items(): + for mm_port_name, attributes in self.address_map.items(): logger.debug(" %-30s 0x%x, range %5.3fkB at port MSTR_%s[%d]", - slave_name, attributes['base'], float(attributes['span'] / 1024.0), attributes['type'], attributes['port_index']) + mm_port_name, attributes['base'], float(attributes['span'] / 1024.0), attributes['type'], attributes['port_index']) logger.debug("- Peripherals:") for peripheral in sorted(self.peripherals): self.peripherals[peripheral].show_overview(header=False) diff --git a/py_args_lib/peripheral.py b/py_args_lib/peripheral.py index 88dee035e707c5d16b8139fdf05a88c302784c0a..07fb45f5773930750978f002fd4d505ee5af818a 100644 --- a/py_args_lib/peripheral.py +++ b/py_args_lib/peripheral.py @@ -40,23 +40,23 @@ logger = logging.getLogger('main.peripheral') class Peripheral(BaseObject): - """ A Peripheral consists of 1 or more MM slaves. The slave can be a + """ A Peripheral consists of one or more MM ports. The MM port can be a Register, RAM or FIFO. - The Peripheral has parameters to configure the MM slaves. + The Peripheral has parameters to configure the MM ports. A Peripheral has two levels of supporting multiple instances: - 1) At system level a peripheral can be used more than once. The individual - peripherals are then distinghuised by defining a unique label per + 1) At FPGA level a peripheral can be used more than once. The individual + peripherals are then distinghuised by defining a unique pelabel per instance. 2) At peripheral level internally in the peripheral if the peripheral support an array of instances. The size of the array is then specified via nof_inst. Dependent on the specific definition of the peripheral, the nof_inst then either replicates some fields in a register or it - replicates some or all MM slaves nof_inst times. + replicates some or all MM ports nof_inst times. The Peripheral evaluates the nof_inst and parameters to set the - dimensions of the MM slaves. + dimensions of the MM ports. """ def __init__(self, library_config): super().__init__() @@ -65,7 +65,7 @@ class Peripheral(BaseObject): self.registers = {} # all used registers self.rams = {} # all used rams self.fifos = {} # all used fifos - self.slaves = [] + self.mm_ports = [] self._component_name = library_config['peripheral_name'] self.name(self._component_name) self._valid_keys = ['number_of_peripherals'] @@ -77,11 +77,11 @@ class Peripheral(BaseObject): logger.debug("extract config for %s", self.component_name()) self.extract_config() - def get_slave(self, name): + def get_mm_port(self, name): - for slave in self.slaves: - if name == slave.name() or slave.user_defined_name(): - return slave + for mmport in self.mm_ports: + if name == mmport.name() or mmport.user_defined_name(): + return mmport return None def component_name(self): @@ -122,11 +122,11 @@ class Peripheral(BaseObject): return return self._parameters[key] - def set_user_defined_slavename(self, slave_nr, name): - """ Set user defined slave name + def set_user_defined_mm_port_name(self, mm_port_nr, name): + """ Set user defined mm_port_name """ - if slave_nr in range(len(self.slaves)): - self.slaves[slave_nr].user_defined_name(name) + if mm_port_nr in range(len(self.mm_ports)): + self.mm_ports[mm_port_nr].user_defined_name(name) def extract_config(self): """ extract all kv pairs from the config (yaml file) @@ -178,29 +178,29 @@ class Peripheral(BaseObject): logger.debug("used parameters=%s", str(self._parameters)) - if 'slave_ports' in self._config: - slave_ports = deepcopy(self._config['slave_ports']) + if 'mm_ports' in self._config: + mm_ports = deepcopy(self._config['mm_ports']) - if not isinstance(slave_ports, list): - logger.error("slave_ports not a list in *.peripheral.yaml") + if not isinstance(mm_ports, list): + logger.error("mm_ports not a list in *.peripheral.yaml") sys.exit() - for slave_nr, slave_info in enumerate(slave_ports): - logger.debug("slave_name=%s slave_type=%s", slave_info.get('slave_name', None), slave_info.get('slave_type', None)) - slave_name = slave_info['slave_name'] + for mm_port_nr, mm_port_info in enumerate(mm_ports): + logger.debug("mm_port_name=%s mm_port_type=%s", mm_port_info.get('mm_port_name', None), mm_port_info.get('mm_port_type', None)) + mm_port_name = mm_port_info['mm_port_name'] - if slave_name is None: - logger.error("Peripheral '%s': 'slave_name' key missing value in *.peripheral.yaml", self.name()) + if mm_port_name is None: + logger.error("Peripheral '%s': 'mm_port_name' key missing value in *.peripheral.yaml", self.name()) sys.exit() i = 0 - if slave_info.get('slave_type', '').upper() in VALID_SLAVE_TYPES: - number_of_slaves = slave_info.get('number_of_slaves', DEFAULT_NUMBER_OF_SLAVES) + if mm_port_info.get('mm_port_type', '').upper() in VALID_SLAVE_TYPES: + number_of_mm_ports = mm_port_info.get('number_of_mm_ports', DEFAULT_NUMBER_OF_SLAVES) fields = [] - if 'fields' in slave_info: + if 'fields' in mm_port_info: defaults = {} - for field_group in slave_info['fields']: + for field_group in mm_port_info['fields']: if isinstance(field_group, dict): # labelled field group (group_label, v) = field_group.popitem() field_group = v @@ -246,8 +246,8 @@ class Peripheral(BaseObject): sys.exit() else: - logger.error("Peripheral '%s': Slave '%s': '%s' key missing value in *.peripheral.yaml", - self.name(), slave_name, key) + logger.error("Peripheral '%s': MM port '%s': '%s' key missing value in *.peripheral.yaml", + self.name(), mm_port_name, key) sys.exit() for key, val in defaults.items(): @@ -262,24 +262,24 @@ class Peripheral(BaseObject): logger.error("*.peripheral.yaml: field '%s' not succesfully added to fields", field_name) sys.exit() - if slave_info['slave_type'].upper() in ['RAM', 'FIFO']: + if mm_port_info['mm_port_type'].upper() in ['RAM', 'FIFO']: field = field_group[0] - if slave_info['slave_type'] in ['RAM']: - self.add_ram(slave_nr, slave_name, field, number_of_slaves) + if mm_port_info['mm_port_type'] in ['RAM']: + self.add_ram(mm_port_nr, mm_port_name, field, number_of_mm_ports) else: - self.add_fifo(slave_nr, slave_name, field, number_of_slaves) - else: # slave_type is REG or REG_IP - logger.debug('adding register %s\n', slave_name) - self.add_register(slave_nr, slave_name, fields, number_of_slaves, slave_info['slave_type'].upper() == 'REG_IP', - slave_info.get('slave_protocol', None), slave_info.get('slave_span', None)) - if 'slave_description' in slave_info.keys(): - self.slaves[-1].update_args({'slave_description': slave_info['slave_description']}) - if 'dual_clock' in slave_info.keys(): - self.slaves[-1].update_args({'dual_clock': slave_info['dual_clock']}) + self.add_fifo(mm_port_nr, mm_port_name, field, number_of_mm_ports) + else: # mm_port_type is REG or REG_IP + logger.debug('adding register %s\n', mm_port_name) + self.add_register(mm_port_nr, mm_port_name, fields, number_of_mm_ports, mm_port_info['mm_port_type'].upper() == 'REG_IP', + mm_port_info.get('mm_port_protocol', None), mm_port_info.get('mm_port_span', None)) + if 'mm_port_description' in mm_port_info.keys(): + self.mm_ports[-1].update_args({'mm_port_description': mm_port_info['mm_port_description']}) + if 'dual_clock' in mm_port_info.keys(): + self.mm_ports[-1].update_args({'dual_clock': mm_port_info['dual_clock']}) else : - logger.error("Peripheral '%s': Slave '%s': Invalid value %s for 'slave_type' key in *.peripheral.yaml", - self.name(), slave_name, slave_info.get('slave_type', 'None')) + logger.error("Peripheral '%s': MM port '%s': Invalid value %s for 'mm_port_type' key in *.peripheral.yaml", + self.name(), mm_port_name, mm_port_info.get('mm_port_type', 'None')) sys.exit() if 'peripheral_description' in self._config: @@ -333,48 +333,48 @@ class Peripheral(BaseObject): """ self._parameters[name] = value - def add_register(self, slave_nr, name, fields, number_of_slaves, isIP, protocol, slave_span): + def add_register(self, mm_port_nr, name, fields, number_of_mm_ports, isIP, protocol, mm_port_span): """ add register to peripheral """ - register = deepcopy(self.init_slave('Register', name, fields)) - register.number_of_slaves(number_of_slaves) + register = deepcopy(self.init_mm_port('Register', name, fields)) + register.number_of_mm_ports(number_of_mm_ports) register.isIP = isIP - register.slave_span = slave_span + register.mm_port_span = mm_port_span if protocol is not None and protocol.upper() in ['LITE', 'FULL']: # EK: TODO Remove AXI specific protocol field register.protocol = protocol.upper() - self.registers['slave_{}'.format(slave_nr)] = register - self.slaves.append(register) + self.registers['mm_port_{}'.format(mm_port_nr)] = register + self.mm_ports.append(register) - def add_ram(self, slave_nr, name, settings, number_of_slaves): + def add_ram(self, mm_port_nr, name, settings, number_of_mm_ports): """ add RAM to peripheral """ logger.debug("name is %s", name) - ram = deepcopy(self.init_slave('RAM', name, settings)) - ram.number_of_slaves(number_of_slaves) - self.rams['slave_{}'.format(slave_nr)] = ram - self.slaves.append(ram) + ram = deepcopy(self.init_mm_port('RAM', name, settings)) + ram.number_of_mm_ports(number_of_mm_ports) + self.rams['mm_port_{}'.format(mm_port_nr)] = ram + self.mm_ports.append(ram) - def add_fifo(self, slave_nr, name, field, number_of_slaves): + def add_fifo(self, mm_port_nr, name, field, number_of_mm_ports): """ add FIFO to peripheral """ - fifo = deepcopy(self.init_slave('FIFO', name, field)) - fifo.number_of_slaves(number_of_slaves) - self.fifos['slave_{}'.format(slave_nr)] = fifo - self.slaves.append(fifo) - - def init_slave(self, slave_type, name, settings): - """ init Slave based on type with error checking """ - add_slave = "{}(name, settings)".format(slave_type) + fifo = deepcopy(self.init_mm_port('FIFO', name, field)) + fifo.number_of_mm_ports(number_of_mm_ports) + self.fifos['mm_port_{}'.format(mm_port_nr)] = fifo + self.mm_ports.append(fifo) + + def init_mm_port(self, mm_port_type, name, settings): + """ init MM port based on type with error checking """ + add_mm_port = "{}(name, settings)".format(mm_port_type) try : - slave = eval(add_slave) + mmport = eval(add_mm_port) except ARGSNameError: - logger.error("Invalid slave_name '%s' for %s in *.peripheral.yaml", name, slave_type) + logger.error("Invalid mm_port_name '%s' for %s in *.peripheral.yaml", name, mm_port_type) sys.exit() except ARGSModeError: - logger.error("Invalid access mode for %s '%s' in *.peripheral.yaml", slave_type, name) + logger.error("Invalid access mode for %s '%s' in *.peripheral.yaml", mm_port_type, name) sys.exit() - return slave + return mmport def eval_fields(self, fields): """ Evaluate the fields """ @@ -382,7 +382,7 @@ class Peripheral(BaseObject): for field in fields: # .values(): logger.debug("eval field %s", field.name()) if [(field.name() == _field.name() and field.group_name() == _field.group_name()) for _field in fields].count(True) > 1: - logger.error("Field name '%s' group_name '%s' is not unique within slave field list in *.peripheral.yaml", + logger.error("Field name '%s' group_name '%s' is not unique within MM port field list in *.peripheral.yaml", field.name(), field.group_name()) sys.exit() if field.group_name() is not None: @@ -400,14 +400,14 @@ class Peripheral(BaseObject): def eval_fifo(self): """ Evaluate the paramters and the nof_inst of the peripheral """ - for slave in self.slaves: - if isinstance(slave, FIFO): + for mmport in self.mm_ports: + if isinstance(mmport, FIFO): # Evaluate the fields - self.eval_fields([slave]) + self.eval_fields([mmport]) else : continue - fifo = slave - fifo.number_of_slaves(val=self._eval(fifo.number_of_slaves())) + fifo = mmport + fifo.number_of_mm_ports(val=self._eval(fifo.number_of_mm_ports())) logger.debug(" -FIFO depth (fields): %s", fifo.number_of_fields()) fifo.address_length(val=ceil_pow2(self._eval(fifo.number_of_fields())) * WORD_SIZE) # address_length in bytes logger.debug(" -FIFO depth (bytes): %s", fifo.address_length()) @@ -419,10 +419,10 @@ class Peripheral(BaseObject): For example: address_length = c_nof_weights*c_nof_signal_paths witdh = c_weights_w*c_nof_complex """ - for slave in self.slaves: + for mmport in self.mm_ports: # Evaluate the fields and see if there are field that have to be repeated. - if isinstance(slave, RAM): - ram = slave + if isinstance(mmport, RAM): + ram = mmport else: continue @@ -432,12 +432,12 @@ class Peripheral(BaseObject): if ram.user_width() < DEFAULT_FIELD_WIDTH: ram.user_width(DEFAULT_FIELD_WIDTH) - ram.number_of_slaves(val=self._eval(ram.number_of_slaves())) + ram.number_of_mm_ports(val=self._eval(ram.number_of_mm_ports())) - for slave in self.slaves: + for mmport in self.mm_ports: # Evaluate the fields and see if there are field that have to be repeated. - if isinstance(slave, RAM): - ram = slave + if isinstance(mmport, RAM): + ram = mmport else: continue logger.debug(" -RAM depth (fields): %s", ram.number_of_fields()) @@ -462,9 +462,9 @@ class Peripheral(BaseObject): logger.debug("Number of registers = %d", len(self.registers.items())) - for slave in self.slaves: - if isinstance(slave, Register): - register = slave + for mmport in self.mm_ports: + if isinstance(mmport, Register): + register = mmport else : continue logger.debug("evaluate %s", register.name()) @@ -493,7 +493,7 @@ class Peripheral(BaseObject): self.eval_fields(fields_eval) self.eval_fields(register.rams) - register.number_of_slaves(val=self._eval(register.number_of_slaves())) + register.number_of_mm_ports(val=self._eval(register.number_of_mm_ports())) register_name = [] if self.prefix() not in (None, ''): @@ -505,7 +505,7 @@ class Peripheral(BaseObject): base_addr = 0 for field in register.rams: base_addr = ceil(base_addr / (ceil_pow2(field.number_of_fields()) * WORD_SIZE)) * ceil_pow2(field.number_of_fields()) * WORD_SIZE # lowest possible base_addr - base_addr = base_addr + ceil_pow2(field.number_of_fields()) * WORD_SIZE * register.number_of_slaves() # new base address + base_addr = base_addr + ceil_pow2(field.number_of_fields()) * WORD_SIZE * register.number_of_mm_ports() # new base address field.base_address(base_addr) # ### Assigned Address and bits to register fields @@ -586,7 +586,7 @@ class Peripheral(BaseObject): register.update_address_length() # Estimate the new address_length after evaluation of the fields and nof_inst logger.info(" %s address_length: %d", register.name(), register.address_length()) register.base_address(base_addr) - base_addr = base_addr + register.address_length() * register.number_of_slaves() + base_addr = base_addr + register.address_length() * register.number_of_mm_ports() self.reg_len = base_addr @@ -616,12 +616,12 @@ class Peripheral(BaseObject): if self.number_of_peripherals() > 1: logger.debug(" number_of_peripheral_instances=%d", self.number_of_peripherals()) logger.debug(" RAM and REG:") - for ram in self.slaves: + for ram in self.mm_ports: if not isinstance(ram, RAM): continue logger.debug(" %-20s:", ram.name()) - if ram.number_of_slaves() > 1: - logger.debug(" number_of_slaves=%-3s", str(ram.number_of_slaves())) + if ram.number_of_mm_ports() > 1: + logger.debug(" number_of_mm_ports=%-3s", str(ram.number_of_mm_ports())) logger.debug(" fields:") # first make list with address_offset as first item to print later fields orderd on address. fields = [] @@ -633,12 +633,12 @@ class Peripheral(BaseObject): logger.debug(" width=%-2s number_of_fields=%s", str(field.width()), str(field.number_of_fields())) - for reg in self.slaves: + for reg in self.mm_ports: if not isinstance(reg, Register): continue logger.debug(" %-20s:", reg.name()) - if reg.number_of_slaves() > 1: - logger.debug(" number_of_slaves=%-3s", str(reg.number_of_slaves())) + if reg.number_of_mm_ports() > 1: + logger.debug(" number_of_mm_ports=%-3s", str(reg.number_of_mm_ports())) logger.debug(" address_length=%-3s", str(reg.address_length())) logger.debug(" fields:") diff --git a/py_args_lib/peripheral_lib/fifo.py b/py_args_lib/peripheral_lib/fifo.py index 1201a1bf5e9312a1560285dbe900b8e11e569ed5..56200c634c2ed929e6fa5b4d7a59eef24b886fc9 100644 --- a/py_args_lib/peripheral_lib/fifo.py +++ b/py_args_lib/peripheral_lib/fifo.py @@ -43,12 +43,12 @@ class FIFO(Field): self.name(name) self.description = "" - def number_of_slaves(self, val=None): - """ set/get number of slaves """ + def number_of_mm_ports(self, val=None): + """ set/get number_of_mm_ports """ if val is not None: - self.set_kv('number_of_slaves', val) + self.set_kv('number_of_mm_ports', val) return - return self._as_int('number_of_slaves') + return self._as_int('number_of_mm_ports') def update_address_length(self): """ update total address_length of Register in bytes """ diff --git a/py_args_lib/peripheral_lib/ram.py b/py_args_lib/peripheral_lib/ram.py index 755867cd9d5f965dac9523f80066b71b581853e3..a82221e32887f00b6373f66933ad0781b6feb13c 100644 --- a/py_args_lib/peripheral_lib/ram.py +++ b/py_args_lib/peripheral_lib/ram.py @@ -46,15 +46,15 @@ class RAM(Field): self.name(name) self.description = "" - self._valid_keys = ['number_of_slaves', 'user_width'] - self._args.update({'number_of_slaves' : DEFAULT_NUMBER_OF_SLAVES}) + self._valid_keys = ['number_of_mm_ports', 'user_width'] + self._args.update({'number_of_mm_ports' : DEFAULT_NUMBER_OF_SLAVES}) - def number_of_slaves(self, val=None): - """ set/get number of slaves """ + def number_of_mm_ports(self, val=None): + """ set/get number_of_mm_ports """ if val is not None: - self.set_kv('number_of_slaves', val) + self.set_kv('number_of_mm_ports', val) return - return self._as_int('number_of_slaves') + return self._as_int('number_of_mm_ports') def user_depth(self, val=None): """ val: depth in bytes """ diff --git a/py_args_lib/peripheral_lib/register.py b/py_args_lib/peripheral_lib/register.py index 94148573389e07d11d101992911fb819a01ca646..1e89c8a05b898bbb7e772bf1abaa35bbcb6af0b9 100644 --- a/py_args_lib/peripheral_lib/register.py +++ b/py_args_lib/peripheral_lib/register.py @@ -35,7 +35,7 @@ from field import Field logger = logging.getLogger('main.periph.register') -class Register(BaseObject): # EK: TODO rename to REG(), to match RAM and FIFO class names and to match slave_type key in peripheral.yaml +class Register(BaseObject): # EK: TODO rename to REG(), to match RAM and FIFO class names and to match mm_port_type key in peripheral.yaml """ A register consists of Fields """ def __init__(self, name, fields=None, settings=None): @@ -48,25 +48,25 @@ class Register(BaseObject): # EK: TODO rename to REG(), to match RAM and FIFO self.rams = [] # EK: TODO remove rams, because no rams in Register - self._valid_keys = ['number_of_slaves', 'address_length', 'slave_description', 'base_address'] # EK: TODO why here and not in constants.py, best use only one place + self._valid_keys = ['number_of_mm_ports', 'address_length', 'mm_port_description', 'base_address'] # EK: TODO why here and not in constants.py, best use only one place - self._args.update({'number_of_slaves' : DEFAULT_NUMBER_OF_SLAVES, + self._args.update({'number_of_mm_ports' : DEFAULT_NUMBER_OF_SLAVES, 'address_length' : DEFAULT_ADDRESS_LENGTH, # EK: TODO strange address_length is not an ARGS yaml key, so why in this list? 'dual_clock' : False, - 'slave_description': DEFAULT_SLAVE_DESCRIPTION}) # EK: TODO what is the purpose of this list, it seems incomplete. + 'mm_port_description': DEFAULT_SLAVE_DESCRIPTION}) # EK: TODO what is the purpose of this list, it seems incomplete. # self.update_address_length() self.isIP = False # EK: TODO remove platform specific isIP - self.slave_span = None + self.mm_port_span = None self.protocol = 'LITE' # EK: TODO remove AXI specific protocol field (LITE, FULL) - def number_of_slaves(self, val=None): - """ set/get number of slaves """ + def number_of_mm_ports(self, val=None): + """ set/get number_of_mm_ports """ if val is not None: - self.set_kv('number_of_slaves', val) + self.set_kv('number_of_mm_ports', val) return - return self._as_int('number_of_slaves') + return self._as_int('number_of_mm_ports') def add_field(self, name, settings): """ add new Field to Register with given settings @@ -87,10 +87,10 @@ class Register(BaseObject): # EK: TODO rename to REG(), to match RAM and FIFO n_bytes = 0 if any(self.fields): - n_bytes += max(max([_field.address_offset() for _field in self.fields]) + WORD_SIZE, self.slave_span if self.slave_span is not None else 0) + n_bytes += max(max([_field.address_offset() for _field in self.fields]) + WORD_SIZE, self.mm_port_span if self.mm_port_span is not None else 0) if any(self.rams): - #n_bytes += max(max([_field.address_offset() for _field in self.rams]) + WORD_SIZE, self.slave_span if self.slave_span is not None else 0) + #n_bytes += max(max([_field.address_offset() for _field in self.rams]) + WORD_SIZE, self.mm_port_span if self.mm_port_span is not None else 0) n_bytes += ceil_pow2(self.rams[0].number_of_fields()) * WORD_SIZE self.set_kv('address_length', n_bytes) diff --git a/systems/demo.system.yaml b/systems/demo.system.yaml index 2e6ea7ab92c9fabeb9bd20aaa2b52ad5311a8d91..8178093e028565a0cfb44d8316b8dbe22d659809 100644 --- a/systems/demo.system.yaml +++ b/systems/demo.system.yaml @@ -20,14 +20,14 @@ parameters: peripherals: - peripheral_name: rom_system_info subsystem_name : '' - slave_port_names: + mm_port_names: - rom_system_info parameters: - { name: lock_base_address, value: 0x1000 } - peripheral_name: reg_system_info subsystem_name : '' - slave_port_names: + mm_port_names: - reg_system_info parameters: - { name: lock_base_address, value: 0x0 } @@ -35,13 +35,13 @@ peripherals: - peripheral_name: fringe_stop_unit subsystem_name : '' number_of_peripherals: nof_fringe_stop_units - slave_port_names: + mm_port_names: - ram_fringe_stop_step - fringe_stop_offset - peripheral_name: diag_block_gen subsystem_name : input - slave_port_names: + mm_port_names: - reg_diag_bg_input - ram_diag_bg_input parameters: @@ -50,7 +50,7 @@ peripherals: - peripheral_name: diag_block_gen subsystem_name : output - slave_port_names: + mm_port_names: - reg_diag_bg_output - ram_diag_bg_output parameters: @@ -58,7 +58,7 @@ peripherals: - peripheral_name: diag_block_gen subsystem_name : mesh - slave_port_names: + mm_port_names: - reg_diag_bg_mesh - ram_diag_bg_mesh parameters: @@ -67,7 +67,7 @@ peripherals: - peripheral_name: diag_block_gen subsystem_name : proc - slave_port_names: + mm_port_names: - reg_diag_bg_proc - ram_diag_bg_proc parameters: @@ -76,7 +76,7 @@ peripherals: - peripheral_name: bf_unit subsystem_name : '' - slave_port_names: + mm_port_names: - ram_bf_weights - ram_ss_ss_wide - ram_st_sst_bf @@ -90,7 +90,7 @@ peripherals: - peripheral_name: diag_data_buffer subsystem_name : input_pre - slave_port_names: + mm_port_names: - reg_diag_data_buffer_input_pre - ram_diag_data_buffer_input_pre parameters: @@ -100,7 +100,7 @@ peripherals: - peripheral_name: diag_data_buffer subsystem_name : input_post - slave_port_names: + mm_port_names: - reg_diag_data_buffer_input_post - ram_diag_data_buffer_input_post parameters: @@ -110,7 +110,7 @@ peripherals: - peripheral_name: diag_data_buffer subsystem_name : mesh - slave_port_names: + mm_port_names: - reg_diag_data_buffer_mesh - ram_diag_data_buffer_mesh parameters: @@ -120,7 +120,7 @@ peripherals: - peripheral_name: diag_data_buffer subsystem_name : proc - slave_port_names: + mm_port_names: - reg_diag_data_buffer_proc - ram_diag_data_buffer_proc parameters: @@ -130,14 +130,14 @@ peripherals: - peripheral_name: dp_bsn_align subsystem_name : input - slave_port_names: + mm_port_names: - reg_dp_bsn_align_input parameters: - { name : g_nof_input, value: 3 } - peripheral_name: dp_fifo_fill subsystem_name : '' - slave_port_names: + mm_port_names: - reg_dp_fifo_fill parameters: - { name : g_nof_streams, value: 3 } diff --git a/uniboard_rom_system_info.py b/uniboard_rom_system_info.py index 03b00b0d40813794b9d0995818f35614af342118..16c11404730285247f31e1d2d53f6d0fff69da5d 100755 --- a/uniboard_rom_system_info.py +++ b/uniboard_rom_system_info.py @@ -214,22 +214,22 @@ class RomSystem(object): for peripheral_name in self.fpga.locked_base_addresses: base_address = int(self.fpga.locked_base_addresses[peripheral_name]) - size = ceil_pow2(int(peripheral.get_slave('system').fields['field_reg_info'].number_of_fields())) # TODO: if not available calculate real size + size = ceil_pow2(int(peripheral.get_mm_port('system').fields['field_reg_info'].number_of_fields())) # TODO: if not available calculate real size peripheral = peripherals['system'] #print(peripheral.registers) base_address = int(peripheral.parameter('lock_base_address')) - size = ceil_pow2(int(peripheral.get_slave('system').fields['field_reg_info'].number_of_fields())) # TODO: if not available calculate real size - name = peripheral.get_slave('system').user_defined_name() + size = ceil_pow2(int(peripheral.get_mm_port('system').fields['field_reg_info'].number_of_fields())) # TODO: if not available calculate real size + name = peripheral.get_mm_port('system').user_defined_name() if name is None: name = "system" self.memory_mapper.add(name=name, size=size, nof_instances=1, base_address=base_address, hide_in_reg_file=True) peripheral = peripherals['rom_system'] base_address = int(peripheral.parameter('lock_base_address')) - size = ceil_pow2(int(peripheral.get_slave('rom_system_info').fields['field_rom_info'].number_of_fields())) # TODO: if not available calculate real size - name = peripheral.get_slave('rom_system').user_defined_name() + size = ceil_pow2(int(peripheral.get_mm_port('rom_system_info').fields['field_rom_info'].number_of_fields())) # TODO: if not available calculate real size + name = peripheral.get_mm_port('rom_system').user_defined_name() if name is None: name = "rom_system" self.memory_mapper.add(name=name, size=size, nof_instances=1, base_address=base_address, hide_in_reg_file=True) @@ -245,7 +245,7 @@ class RomSystem(object): for rkey, rval in peripheral.rams.items(): n_addresses = rval.get_kv('address_length') - nof_inst = rval.number_of_slaves() * peripheral.number_of_peripherals() + nof_inst = rval.number_of_mm_ports() * peripheral.number_of_peripherals() if rval.user_defined_name() is not None: _name = rval.user_defined_name() else: @@ -258,7 +258,7 @@ class RomSystem(object): for rkey, rval in peripheral.registers.items(): n_addresses = rval.get_kv('address_length') - nof_inst = rval.number_of_slaves() * peripheral.number_of_peripherals() + nof_inst = rval.number_of_mm_ports() * peripheral.number_of_peripherals() if rval.user_defined_name() is not None: _name = rval.user_defined_name() else: