From cdb4b1a6a89fa5073e0774b39e816b9421212136 Mon Sep 17 00:00:00 2001
From: wierenga <sdos@astron.nl>
Date: Wed, 12 Jul 2006 14:56:10 +0000
Subject: [PATCH] BugID: 778 Initialization sequence finally working! Add delay
between RSU Clear and BSWrite.
---
MAC/APL/PIC/RSPDriver/src/Cache.cc | 9 +++++++--
MAC/APL/PIC/RSPDriver/src/RSUWrite.cc | 4 ++--
MAC/APL/PIC/RSPDriver/src/SetClocksCmd.cc | 2 +-
MAC/APL/PIC/RSPDriver/src/StatusRead.cc | 4 ++--
MAC/APL/PIC/RSPDriver/src/TDSProtocolWrite.cc | 5 +++++
5 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/MAC/APL/PIC/RSPDriver/src/Cache.cc b/MAC/APL/PIC/RSPDriver/src/Cache.cc
index a4bc2520609..0ababdbb751 100644
--- a/MAC/APL/PIC/RSPDriver/src/Cache.cc
+++ b/MAC/APL/PIC/RSPDriver/src/Cache.cc
@@ -48,6 +48,13 @@ CacheBuffer::CacheBuffer(Cache* cache) : m_cache(cache)
{
reset(); // reset by allocating memory and settings default values
+ // When the sample frequency (m_clock) is modified the RSP
+ // board goes through a reset. For this reason we reset all
+ // values in the cacht to default (using Cache::reset), but
+ // the value of m_clock should not be reset. For that reason
+ // it is initialized here separately outside reset().
+ m_clock = GET_CONFIG("RSPDriver.DEFAULT_SAMPLING_FREQUENCY", i);
+
// print sizes of the cache
LOG_DEBUG_STR("m_beamletweights().size() =" << m_beamletweights().size() * sizeof(complex<int16>));
LOG_DEBUG_STR("m_subbandselection().size() =" << m_subbandselection().size() * sizeof(uint16));
@@ -178,8 +185,6 @@ void CacheBuffer::reset(void)
m_versions.bp() = versioninit;
m_versions.ap().resize(StationSettings::instance()->nrBlps());
m_versions.ap() = versioninit;
-
- m_clock = GET_CONFIG("RSPDriver.DEFAULT_SAMPLING_FREQUENCY", i);
}
RTC::Timestamp CacheBuffer::getTimestamp() const
diff --git a/MAC/APL/PIC/RSPDriver/src/RSUWrite.cc b/MAC/APL/PIC/RSPDriver/src/RSUWrite.cc
index 6dec1561d0a..a3c499a0908 100644
--- a/MAC/APL/PIC/RSPDriver/src/RSUWrite.cc
+++ b/MAC/APL/PIC/RSPDriver/src/RSUWrite.cc
@@ -37,7 +37,7 @@
#include "InitState.h"
// nof seconds to wait with writing BS register after RSU clear
-#define WAIT_AFTER ((long)3)
+#define WRITE_BS_DELAY ((long)5)
using namespace blitz;
using namespace LOFAR;
@@ -71,7 +71,7 @@ void RSUWrite::sendrequest()
reset.hdr.set(MEPHeader::RSU_RESET_HDR);
if (InitState::instance().getState() == InitState::WRITE_BS &&
- m_mark != Timestamp(0,0) && m_mark + ((long)3) <= m_scheduler.getCurrentTime()) {
+ m_mark != Timestamp(0,0) && m_mark + WRITE_BS_DELAY <= m_scheduler.getCurrentTime()) {
// next write all BS registers on all AP's of this board
for (int blp = 0; blp < StationSettings::instance()->nrBlpsPerBoard(); blp++) {
diff --git a/MAC/APL/PIC/RSPDriver/src/SetClocksCmd.cc b/MAC/APL/PIC/RSPDriver/src/SetClocksCmd.cc
index b3c6d9a633f..cdd37b8f26b 100644
--- a/MAC/APL/PIC/RSPDriver/src/SetClocksCmd.cc
+++ b/MAC/APL/PIC/RSPDriver/src/SetClocksCmd.cc
@@ -63,6 +63,7 @@ void SetClocksCmd::ack(CacheBuffer& /*cache*/)
void SetClocksCmd::apply(CacheBuffer& cache, bool setModFlag)
{
cache.getClock() = m_event->clock;
+ LOG_INFO_STR(formatString("Setting clock to %d MHz @ ", m_event->clock) << getTimestamp());
if (setModFlag) {
cache.getCache().getState().tds().write();
}
@@ -70,7 +71,6 @@ void SetClocksCmd::apply(CacheBuffer& cache, bool setModFlag)
void SetClocksCmd::complete(CacheBuffer& /*cache*/)
{
- LOG_INFO_STR("SetClocksCmd completed at time=" << getTimestamp());
}
const Timestamp& SetClocksCmd::getTimestamp() const
diff --git a/MAC/APL/PIC/RSPDriver/src/StatusRead.cc b/MAC/APL/PIC/RSPDriver/src/StatusRead.cc
index 1c447d2a782..796e9b099e8 100644
--- a/MAC/APL/PIC/RSPDriver/src/StatusRead.cc
+++ b/MAC/APL/PIC/RSPDriver/src/StatusRead.cc
@@ -126,8 +126,8 @@ GCFEvent::TResult StatusRead::handleack(GCFEvent& event, GCFPortInterface& /*por
Cache::getInstance().getBack().getClock() = ack.board.rsp.bp_clock;
#endif
} else if (ack.board.rsp.bp_clock != Cache::getInstance().getBack().getClock()) {
- LOG_WARN_STR(formatString("Reported clock (%d MHz) is different from cache settings (%d MHz)",
- ack.board.rsp.bp_clock, Cache::getInstance().getBack().getClock()));
+ LOG_WARN_STR(formatString("Reported clock (%d MHz) is different from cache settings (%d MHz) on RSP board %d",
+ ack.board.rsp.bp_clock, Cache::getInstance().getBack().getClock(), getBoardId()));
}
}
break;
diff --git a/MAC/APL/PIC/RSPDriver/src/TDSProtocolWrite.cc b/MAC/APL/PIC/RSPDriver/src/TDSProtocolWrite.cc
index bbcb05b0e5e..2938f61fe71 100644
--- a/MAC/APL/PIC/RSPDriver/src/TDSProtocolWrite.cc
+++ b/MAC/APL/PIC/RSPDriver/src/TDSProtocolWrite.cc
@@ -158,7 +158,12 @@ void TDSProtocolWrite::sendrequest()
// indicate that we're initialising the hardware
if (InitState::instance().getState() == InitState::INIT) {
+
InitState::instance().init(InitState::WRITE_TDS);
+
+ LOG_INFO_STR(formatString("Sending clock setting via RSP board %d: %d MHz",
+ getBoardId(), Cache::getInstance().getBack().getClock()));
+
}
uint32 tds_control = 0;
--
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