diff --git a/MAC/APL/PAC/Cal_Server/src/CalServer.cc b/MAC/APL/PAC/Cal_Server/src/CalServer.cc
index 469b5905a0a8894f11b258fc231211f3304841a3..6d5aabdfac8927f259aab65a9b8ae24102a81d58 100644
--- a/MAC/APL/PAC/Cal_Server/src/CalServer.cc
+++ b/MAC/APL/PAC/Cal_Server/src/CalServer.cc
@@ -735,55 +735,16 @@ GCFEvent::TResult CalServer::handle_cal_start(GCFEvent& e, GCFPortInterface &por
//
// set the control register of the RCU's
- // if in HBA mode turn on HBAs in groups to prevent resetting of boards
- //
-
RSPSetrcuEvent setrcu;
- bitset<MAX_RCUS> testmask;
- Timestamp timeStamp;
-
- // #define N_PWR_RCUS_PER_STEP 12
- #define N_PWR_RCUS_PER_STEP 8
- int nPwrRCUs = m_n_rcus / 2; // only the even rcus deliver power to the HBAs
- int steps = nPwrRCUs / N_PWR_RCUS_PER_STEP; // 4 steps for NL stations, 8 steps for IS stations
- int jump = m_n_rcus / N_PWR_RCUS_PER_STEP; // jump = 8 for NL stations and 16 for IS stations
+ setrcu.timestamp = Timestamp(0,0);
+ setrcu.rcumask = start.subset & validmask;
+ setrcu.settings().resize(1);
+ setrcu.settings()(0) = start.rcumode()(0);
- if (steps == 0) { steps = 1; } // limit for test cabinet
- if (jump < 2) { jump = 2; } // limit for test cabinet
-
- // if LBA mode select all rcus in one step
- if (start.rcumode()(0).getMode() <= 4) {
- steps = 1;
- jump = 2;
- }
- int delay(0);
- for (int step = 0; step < steps; ++step) {
- validmask.reset();
- // select 12 even(X) rcus and 12 odd(Y) rcus
- for (uint rcu = (step * 2); rcu < m_n_rcus; rcu += jump) {
- validmask.set(rcu); // select X (HBA power supply)
- validmask.set(rcu+1); // select Y
- }
-
- // if any rcus in this masker send command
- testmask = start.subset & validmask;
- if (testmask.any()) {
- delay = SCHEDULING_DELAY + step;
- timeStamp.setNow(delay);
- setrcu.timestamp = timeStamp; // in steps of 1 second
-
- //TODO: Step20.2: might have to send 2 settings e.g. when using all X-pols
-
- setrcu.rcumask = start.subset & validmask;
- setrcu.settings().resize(1);
- setrcu.settings()(0) = start.rcumode()(0);
-
- LOG_DEBUG(formatString("Sending RSP_SETRCU(%08X)", start.rcumode()(0).getRaw()));
- itsRSPDriver->send(setrcu);
- } // if in mask
- } // for steps
- _enableRCUs(subarray, delay + 4);
+ LOG_DEBUG(formatString("Sending RSP_SETRCU(%08X)", start.rcumode()(0).getRaw()));
+ itsRSPDriver->send(setrcu);
+ _enableRCUs(subarray, SCHEDULING_DELAY + 4);
} // conflict?
}
}
diff --git a/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc b/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc
index 6c5f8cd84eb306943837074f27683ba1eaca1032..ce0802a20f554916df8ecf3948b947c1eec8ad88 100644
--- a/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc
+++ b/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc
@@ -45,37 +45,41 @@ namespace LOFAR {
#define WRITE_ALL_TIMEOUT 5
-
/*
* Implements the following sequences:
* from idle state:
- * - SEQ_STARTUP, starts on sequence disableClock
- * - SEQ_SETCLOCK, starts on sequence writeClock
- * - SEQ_RSPCLEAR, starts on sequence RSUclear
+ * - SEQ_STARTUP, on driver startup, starts on sequence disableClock
+ * - SEQ_SETCLOCK, on clock change, starts on sequence writeClock
+ * - SEQ_RSPCLEAR, on request, starts on sequence RSUclear
*
- * idle_state <--------------------------------------------,
- * | | | |
- * | | '-> disableClock_state <-------------------. | STARTUP_WAIT
- * | | writePLL_state ---> writeError ----' | WRITE_TIMEOUT
- * | '----> writeClock_state <-------------------. | STARTUP_WAIT
- * | readClock_state ---> readError -----' | TDREAD_TIMEOUT
- * | ,------- ok <------------' |
- * '--C----> RSUclear_state <----------------------, | RSUCLEAR_WAIT
- * |----> RCUdisable_state -----> writeError -------| | WRITE_TIMEOUT
- * | ,----- ok <-----------' '--> ok & finalState---C---'
- * | '--> setAll_state --> writeError -------| WRITE_TIMEOUT
- * | - Blocksync |
- * | - RADwrite |
- * | - PPSsync |
- * | - CDOenable |
- * | - SDObitmode |
- * | - SDOselect |
- * | - SDOenable |
- * | RCUenable_state --> writeError -------' WRITE_TIMEOUT
- * | --> finalState=True --,
+ * idle_state <-------------------------------------------.
+ * | | | |
+ * | | '-> disableClock_state <----------------------. | STARTUP_WAIT
+ * | | readDisabledClock_state --> readError ----' |
+ * | | writePLL_state <--------------------------. | WRITE_TIMEOUT
+ * | | readPLL_state ---------> readError ------' | TDREAD_TIMEOUT
+ * | | |
+ * | '----> writeClock_state <------------------------. | STARTUP_WAIT
+ * | readClock_state --------> readError ------' | TDREAD_TIMEOUT
+ * | .------- ok <----------' |
+ * | | |
+ * '--|----> RSUclear_state <--------------------------. | RSUCLEAR_WAIT
+ * | | |
+ * x----> RCUdisable_state -----> writeError -------x | WRITE_TIMEOUT
+ * | .----- ok <-----------' '--> ok & finalState---|--'
+ * | | |
+ * | '--> setAll_state ---------> writeError -------x WRITE_TIMEOUT
+ * | - Blocksync |
+ * | - RADwrite |
+ * | - PPSsync |
+ * | - CDOenable |
+ * | - SDObitmode |
+ * | - SDOselect |
+ * | - SDOenable |
+ * | RCUenable_state ------> writeError -------' WRITE_TIMEOUT
+ * | '-----> finalState=True --.
* | |
* '------------------------------------------------'
- *
*/
@@ -161,8 +165,9 @@ GCFEvent::TResult Sequencer::idle_state(GCFEvent& event, GCFPortInterface& /*por
//
// disableClock_state(event, port)
//
-// before switching clock, goto 125 MHz (both clocks off)
-// this prevents locking of firmware
+// Before programming the PLL on the TDS boards disable clock outputs.
+// The RSPBoards will reload the fpga firmware running on internal 125MHz clock.
+// This prevents blocking RSPBoards while programming the PLL.
//
GCFEvent::TResult Sequencer::disableClock_state(GCFEvent& event, GCFPortInterface& /*port*/)
{
@@ -170,7 +175,7 @@ GCFEvent::TResult Sequencer::disableClock_state(GCFEvent& event, GCFPortInterfac
case F_ENTRY: {
LOG_INFO("Entering Sequencer::disableClock_state");
- // save clock
+ // save clock, for later use
itsClockRequest = Cache::getInstance().getBack().getClock();
// set clock to internal board clock (125MHz)
@@ -203,6 +208,8 @@ GCFEvent::TResult Sequencer::disableClock_state(GCFEvent& event, GCFPortInterfac
//
// readClock_state(event, port)
//
+// read back clock, to check if firmware is really running on 125MHz.
+//
GCFEvent::TResult Sequencer::readDisabledClock_state(GCFEvent& event, GCFPortInterface& /*port*/)
{
switch (event.signal) {
@@ -249,7 +256,10 @@ GCFEvent::TResult Sequencer::readDisabledClock_state(GCFEvent& event, GCFPortInt
//
// writePLL_state(event, port)
-//
+//
+// write start sequence to PLL on TDS board this is needed only once, on Driver start.
+// PLL is programmed if clock is set to 0
+//
GCFEvent::TResult Sequencer::writePLL_state(GCFEvent& event, GCFPortInterface& /*port*/)
{
switch (event.signal) {
@@ -287,6 +297,8 @@ GCFEvent::TResult Sequencer::writePLL_state(GCFEvent& event, GCFPortInterface& /
//
// readPLL_state(event, port)
//
+// check programming result, if no errors, set clock back to default freq (from RSPDriver.conf)
+//
GCFEvent::TResult Sequencer::readPLL_state(GCFEvent& event, GCFPortInterface& /*port*/)
{
switch (event.signal) {
@@ -314,8 +326,9 @@ GCFEvent::TResult Sequencer::readPLL_state(GCFEvent& event, GCFPortInterface& /*
}
}
else if (Cache::getInstance().getState().tdread().isMatchAll(RegisterState::IDLE)) {
- Cache::getInstance().getBack().getClock() = 200; //itsClockRequest;
- Cache::getInstance().getFront().getClock() = 200; //itsClockRequest;
+ // set back default clock frequency
+ Cache::getInstance().getBack().getClock() = itsClockRequest;
+ Cache::getInstance().getFront().getClock() = itsClockRequest;
TRAN(Sequencer::writeClock_state);
}
break;