diff --git a/MAC/APL/PIC/RSP_Driver/src/RCUProtocolWrite.cc b/MAC/APL/PIC/RSP_Driver/src/RCUProtocolWrite.cc index a32c822fbda2f7728d2972242f9b233347d10772..fd4872e7a93ed70a13afdd20cc4ef506201341f4 100644 --- a/MAC/APL/PIC/RSP_Driver/src/RCUProtocolWrite.cc +++ b/MAC/APL/PIC/RSP_Driver/src/RCUProtocolWrite.cc @@ -147,22 +147,12 @@ void RCUProtocolWrite::sendrequest() // add waits while turning on hbas to reduce power peaks. // if RCU enable changed or rcumode changed // if rcumode > 0 - if ((rcucontrol.isModeModified()) && (rcucontrol.getMode() > 0)) { + if (rcucontrol.isModeModified()) { // wait between two RCUs is set to maximum, so that an international station // running on 160MHz clock can finisch the job in 1 second. - uint32 delay = 0; // in clock ticks, 2000000 = 8msec on 200MHz, 10msec on 160MHz - // add extra wait for each board only for first rcu - /* - if ((global_rcu % 8) == 0) { - delay = (4000000 * (global_rcu / 2)); // power up one power RCU at a time. - //delay = (2000000 * ((global_rcu % 32) / 2)); // per crate, 3 or 6 power RCUs at a time. - } - else if ((global_rcu % 2) == 0) { - delay = 16000000 * (global_rcu / 2); - }*/ - delay = 4000000 * (global_rcu / 2); - uint32 wait = htonl(delay); - LOG_INFO_STR(formatString("RCU I2C wait rcu %d = %f sec (delay=%04x, wait=%04x)", global_rcu, delay * (1./200e6), delay, wait)); + // in clock ticks, 1500000 = 7.5msec on 200MHz, 9.4msec on 160MHz + uint32 wait = 660000 * global_rcu; + LOG_INFO_STR(formatString("RCUProtocolWrite add wait rcu %d = %f sec", global_rcu, wait * (1./200e6))); memcpy(i2c_protocol_write+1, &wait, 4); } diff --git a/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc b/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc index 9e96ffde47adc14ac32abfa5a1e992895cd19778..6c5f8cd84eb306943837074f27683ba1eaca1032 100644 --- a/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc +++ b/MAC/APL/PIC/RSP_Driver/src/Sequencer.cc @@ -45,34 +45,6 @@ namespace LOFAR { #define WRITE_ALL_TIMEOUT 5 -/* - * Implements the following sequences: - * from idle state: - * - SEQ_STARTUP, starts on sequence disableClock - * - SEQ_SETCLOCK, starts on sequence writeClock - * - SEQ_RSPCLEAR, starts on sequence RSUclear - * - * idle_state <--------------------------------------------, - * | | | | - * | | '-> disableClock_state <-------------------. | STARTUP_WAIT - * | | writePLL_state ---> writeError ----' | WRITE_TIMEOUT - * | '----> writeClock_state <-------------------. | STARTUP_WAIT - * | readClock_state ---> readError -----' | TDREAD_TIMEOUT - * | ,------- ok <------------' | - * '--C----> RSUclear_state <----------------------, | RSUCLEAR_WAIT - * |----> RCUdisable_state -----> writeError -------| | WRITE_TIMEOUT - * | ,----- ok <-----------' '--> ok & finalState---C---' - * | '--> setBlocksync_state --> writeError -------| WRITE_TIMEOUT - * | RADwrite_state --> writeError -------| WRITE_TIMEOUT - * | PPSsync_state --> writeError -------| WRITE_TIMEOUT - * | RCUenable_state --> writeError -------| WRITE_TIMEOUT - * | CDOenable_state --> writeError -------| WRITE_TIMEOUT - * | writeSDO_state --> writeError -------' WRITE_TIMEOUT - * | --> finalState=True --, - * | | - * '------------------------------------------------' - * - */ /* * Implements the following sequences: @@ -483,7 +455,6 @@ GCFEvent::TResult Sequencer::RCUdisable_state(GCFEvent& event, GCFPortInterface& TRAN(Sequencer::idle_state); } else { - //TRAN(Sequencer::setBlocksync_state); TRAN(Sequencer::setAll_state); } } @@ -526,7 +497,6 @@ GCFEvent::TResult Sequencer::RSUclear_state(GCFEvent& event, GCFPortInterface& / case F_TIMER: if (itsTimer++ > RSUCLEAR_WAIT && Cache::getInstance().getState().rsuclear().isMatchAll(RegisterState::IDLE)) { - //TRAN(Sequencer::setBlocksync_state); TRAN(Sequencer::setAll_state); } break; @@ -556,6 +526,9 @@ GCFEvent::TResult Sequencer::setAll_state(GCFEvent& event, GCFPortInterface& /*p Cache::getInstance().getState().rad().write(); Cache::getInstance().getState().crcontrol().reset(); Cache::getInstance().getState().crcontrol().read(); + // Note: we set the state to read iso write so that the CRSync action knows it a new start. + // It will send a 'reset' to the registers first and than change the state to write during + // the repeated writes till all APs have the right delay. Cache::getInstance().getState().cdo().reset(); Cache::getInstance().getState().cdo().write(); if (StationSettings::instance()->hasAartfaac()) { @@ -590,19 +563,6 @@ GCFEvent::TResult Sequencer::setAll_state(GCFEvent& event, GCFPortInterface& /*p if (Cache::getInstance().getState().cdo().getMatchCount(RegisterState::WRITE) > 0) { LOG_WARN("Failed to enable receivers. Retrying..."); } -/* - if (StationSettings::instance()->hasAartfaac()) { - if (Cache::getInstance().getState().sdoState().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to set SDO state. Retrying..."); - } - if (Cache::getInstance().getState().sdoSelectState().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to set SDO select. Retrying..."); - } - if (Cache::getInstance().getState().bypasssettings().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to set SDO settings. Retrying..."); - } - } -*/ TRAN(Sequencer::RSUclear_state); } else if (Cache::getInstance().getState().bs().isMatchAll(RegisterState::IDLE) @@ -611,18 +571,6 @@ GCFEvent::TResult Sequencer::setAll_state(GCFEvent& event, GCFPortInterface& /*p && Cache::getInstance().getState().cdo().isMatchAll(RegisterState::IDLE) ) { TRAN(Sequencer::RCUenable_state); -/* - if (StationSettings::instance()->hasAartfaac()) { - if ( Cache::getInstance().getState().sdoState().isMatchAll(RegisterState::IDLE) - && Cache::getInstance().getState().sdoSelectState().isMatchAll(RegisterState::IDLE) - && Cache::getInstance().getState().bypasssettings().isMatchAll(RegisterState::IDLE) ) { - TRAN(Sequencer::RCUenable_state); - } - } - else { - TRAN(Sequencer::RCUenable_state); - } -*/ } break; @@ -638,118 +586,6 @@ GCFEvent::TResult Sequencer::setAll_state(GCFEvent& event, GCFPortInterface& /*p } -// -// setBlocksync_state(event, port) -// -GCFEvent::TResult Sequencer::setBlocksync_state(GCFEvent& event, GCFPortInterface& /*port*/) -{ - switch (event.signal) { - case F_ENTRY: - LOG_INFO("Entering Sequencer::setBlocksync_state"); - Cache::getInstance().getState().bs().reset(); - Cache::getInstance().getState().bs().write(); - itsTimer = 0; - break; - - case F_TIMER: - if (itsTimer++ > WRITE_TIMEOUT && - Cache::getInstance().getState().bs().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to set BS (blocksync) register. Retrying..."); - Cache::getInstance().getState().bs().reset(); - TRAN(Sequencer::RSUclear_state); - } - else if (Cache::getInstance().getState().bs().isMatchAll(RegisterState::IDLE)) { - TRAN(Sequencer::RADwrite_state); - } - break; - - case F_EXIT: - LOG_DEBUG("Leaving Sequencer::setBlocksync_state"); - break; - - default: - break; - } - - return (GCFEvent::HANDLED); -} - -// -// RADwrite_state(event, port) -// -GCFEvent::TResult Sequencer::RADwrite_state(GCFEvent& event, GCFPortInterface& /*port*/) -{ - switch (event.signal) { - case F_ENTRY: - LOG_INFO("Entering Sequencer::RADwrite_state"); - Cache::getInstance().getState().rad().reset(); - Cache::getInstance().getState().rad().write(); - itsTimer = 0; - break; - - case F_TIMER: - if (itsTimer++ > WRITE_TIMEOUT && - Cache::getInstance().getState().rad().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to write RAD settings register. Retrying..."); - TRAN(Sequencer::RSUclear_state); - } - else if (Cache::getInstance().getState().rad().isMatchAll(RegisterState::IDLE)) { - TRAN(Sequencer::PPSsync_state); - } - break; - - case F_EXIT: - LOG_DEBUG("Leaving Sequencer::RADwrite_state"); - break; - - default: - break; - } - - return (GCFEvent::HANDLED); -} - -// -// PPSsync_state(event, port) -// -GCFEvent::TResult Sequencer::PPSsync_state(GCFEvent& event, GCFPortInterface& /*port*/) -{ - switch (event.signal) { - case F_ENTRY: - LOG_INFO("Entering Sequencer::PPSsync_state"); - Cache::getInstance().getState().crcontrol().reset(); // set to IDLE - Cache::getInstance().getState().crcontrol().read(); // set to READ - // Note: we set the state to read iso write so that the CRSync action knows it a new start. - // It will send a 'reset' to the registers first and than change the state to write during - // the repeated writes till all APs have the right delay. - itsTimer = 0; - break; - - case F_TIMER: - if (itsTimer++ > WRITE_TIMEOUT && - Cache::getInstance().getState().crcontrol().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to write PPSsync settings register. Retrying..."); - stringstream ss; - Cache::getInstance().getState().crcontrol().print(ss); - LOG_DEBUG_STR("PPSsync failure state: " << ss); - TRAN(Sequencer::RSUclear_state); - } - else if (Cache::getInstance().getState().crcontrol().isMatchAll(RegisterState::IDLE)) { - TRAN(Sequencer::RCUenable_state); - } - break; - - case F_EXIT: - LOG_DEBUG("Leaving Sequencer::PPSsync_state"); - break; - - default: - break; - } - - return (GCFEvent::HANDLED); -} - // // enableRCUs [private] // @@ -812,7 +648,6 @@ GCFEvent::TResult Sequencer::RCUenable_state(GCFEvent& event, GCFPortInterface& } else if (Cache::getInstance().getState().rcusettings().isMatchAll(RegisterState::IDLE)) { itsFinalState = true; TRAN(Sequencer::RCUdisable_state); - //TRAN(Sequencer::CDOenable_state); } } break; @@ -828,82 +663,6 @@ GCFEvent::TResult Sequencer::RCUenable_state(GCFEvent& event, GCFPortInterface& return (GCFEvent::HANDLED); } -// -// CDOenable_state(event, port) -// -GCFEvent::TResult Sequencer::CDOenable_state(GCFEvent& event, GCFPortInterface& /*port*/) -{ - switch (event.signal) { - case F_ENTRY: - LOG_INFO("Entering Sequencer::CDOenable_state"); - Cache::getInstance().getState().cdo().reset(); - Cache::getInstance().getState().cdo().write(); - itsTimer = 0; - break; - - case F_TIMER: - if (itsTimer++ > WRITE_TIMEOUT && - Cache::getInstance().getState().cdo().getMatchCount(RegisterState::WRITE) > 0) { - LOG_WARN("Failed to enable receivers. Retrying..."); - TRAN(Sequencer::RSUclear_state); - } else if (Cache::getInstance().getState().cdo().isMatchAll(RegisterState::IDLE)) { - if (StationSettings::instance()->hasAartfaac()) { - TRAN(Sequencer::setSDOwrite_state); - } - else { - itsFinalState = true; - TRAN(Sequencer::RCUdisable_state); - } - } - break; - - case F_EXIT: - LOG_DEBUG("Leaving Sequencer::CDOenable_state"); - break; - - default: - break; - } - - return (GCFEvent::HANDLED); -} - -// -// setSDOwrite_state(event, port) -// -GCFEvent::TResult Sequencer::setSDOwrite_state(GCFEvent& event, GCFPortInterface& /*port*/) -{ - switch (event.signal) { - case F_ENTRY: - LOG_INFO("Entering Sequencer::setSDOwrite_state"); - - Cache::getInstance().getState().sdoState().reset(); - Cache::getInstance().getState().sdoState().write(); - Cache::getInstance().getState().sdoSelectState().reset(); - Cache::getInstance().getState().sdoSelectState().write(); - - for (int blp_nr = 0; blp_nr < StationSettings::instance()->nrBlps(); blp_nr += 4) { - Cache::getInstance().getState().bypasssettings().reset(blp_nr); - Cache::getInstance().getState().bypasssettings().write(blp_nr); - } - itsFinalState = true; - TRAN(Sequencer::RCUdisable_state); - break; - - case F_TIMER: - break; - - case F_EXIT: - LOG_DEBUG("Leaving Sequencer::setSDOwrite_state"); - break; - - default: - break; - } - return (GCFEvent::HANDLED); -} - - } // namespace RSP } // namespace LOFAR diff --git a/MAC/APL/PIC/RSP_Driver/src/Sequencer.h b/MAC/APL/PIC/RSP_Driver/src/Sequencer.h index ee2215f6542aa8dd106e7317c0ed93900a458431..23f3d95f5f5aa40da5b5247d32a02c7b25541677 100644 --- a/MAC/APL/PIC/RSP_Driver/src/Sequencer.h +++ b/MAC/APL/PIC/RSP_Driver/src/Sequencer.h @@ -79,12 +79,7 @@ public: GCFEvent::TResult RCUdisable_state (GCFEvent& event, GCFPortInterface& port); GCFEvent::TResult RSUclear_state (GCFEvent& event, GCFPortInterface& port); GCFEvent::TResult setAll_state (GCFEvent& event, GCFPortInterface& port); - GCFEvent::TResult setBlocksync_state(GCFEvent& event, GCFPortInterface& port); - GCFEvent::TResult RADwrite_state (GCFEvent& event, GCFPortInterface& port); - GCFEvent::TResult PPSsync_state (GCFEvent& event, GCFPortInterface& port); GCFEvent::TResult RCUenable_state (GCFEvent& event, GCFPortInterface& port); - GCFEvent::TResult CDOenable_state (GCFEvent& event, GCFPortInterface& port); - GCFEvent::TResult setSDOwrite_state (GCFEvent& event, GCFPortInterface& port); /*@}*/ private: