From fcd1ef4ab48876d6da2cfdbde7a869fad35d2d79 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 22 Sep 2022 05:20:03 +0200
Subject: [PATCH] back to booleans 2
---
src/fpga_map.cpp | 72 ++++++++++++++++++++++++------------------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/src/fpga_map.cpp b/src/fpga_map.cpp
index 3aaf78cb..6f7651b8 100644
--- a/src/fpga_map.cpp
+++ b/src/fpga_map.cpp
@@ -64,19 +64,19 @@ FpgaMap::FpgaMap()
// Add all opc-ua points:
// opc-ua name, intern cmdID, n_nodes, n_data, permision, data_format
- pointMap->add_register("FPGA_ucp_block_comm_R", UCP_BLOCK, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_ucp_block_comm_RW", UCP_BLOCK, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_ucp_block_comm_R", UCP_BLOCK, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_ucp_block_comm_RW", UCP_BLOCK, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_ucp_status_R", UCP_STATUS, nFpgas, 6, "RO", REG_FORMAT_INT64);
- pointMap->add_register("FPGA_ucp_status_reset_WO", UCP_STATUS, nFpgas, 1, "WO", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_ucp_status_reset_WO", UCP_STATUS, nFpgas, 1, "WO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_temp_R", TEMP, nFpgas, 1, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_firmware_version_R", FIRMWARE_VERSION, nFpgas, 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_hardware_version_R", HARDWARE_VERSION, nFpgas, 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_global_node_index_R", GLOBAL_NODE_INDEX, nFpgas, 1, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_sst_offload_weighted_subbands_R", SST_OFFLOAD_WEIGHTED_SUBBANDS, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_sst_offload_weighted_subbands_RW", SST_OFFLOAD_WEIGHTED_SUBBANDS, nFpgas, 1, "RW", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_sst_offload_enable_R", SST_OFFLOAD_ENABLE, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_sst_offload_enable_RW", SST_OFFLOAD_ENABLE, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_sst_offload_weighted_subbands_R", SST_OFFLOAD_WEIGHTED_SUBBANDS, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_sst_offload_weighted_subbands_RW", SST_OFFLOAD_WEIGHTED_SUBBANDS, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_sst_offload_enable_R", SST_OFFLOAD_ENABLE, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_sst_offload_enable_RW", SST_OFFLOAD_ENABLE, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_sst_offload_hdr_eth_destination_mac_R", SST_OFFLOAD_HDR_ETH_DESTINATION_MAC, nFpgas, 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_sst_offload_hdr_eth_destination_mac_RW", SST_OFFLOAD_HDR_ETH_DESTINATION_MAC, nFpgas, 1, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_sst_offload_hdr_ip_destination_address_R", SST_OFFLOAD_HDR_IP_DESTINATION_ADDRESS, nFpgas, 1, "RO", REG_FORMAT_STRING);
@@ -87,8 +87,8 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_sst_offload_nof_valid_R", SST_OFFLOAD_NOF_VALID, nFpgas, 1, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_sst_offload_bsn_R", SST_OFFLOAD_BSN, nFpgas, 1, "RO", REG_FORMAT_INT64);
- pointMap->add_register("FPGA_bst_offload_enable_R", BST_OFFLOAD_ENABLE, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_bst_offload_enable_RW", BST_OFFLOAD_ENABLE, nFpgas, nBeamsets, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_bst_offload_enable_R", BST_OFFLOAD_ENABLE, nFpgas, nBeamsets, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_bst_offload_enable_RW", BST_OFFLOAD_ENABLE, nFpgas, nBeamsets, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_R", BST_OFFLOAD_HDR_ETH_DESTINATION_MAC, nFpgas, nBeamsets, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_RW", BST_OFFLOAD_HDR_ETH_DESTINATION_MAC, nFpgas, nBeamsets, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_ip_destination_address_R", BST_OFFLOAD_HDR_IP_DESTINATION_ADDRESS, nFpgas, nBeamsets, "RO", REG_FORMAT_STRING);
@@ -103,10 +103,10 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_xst_subband_select_RW", XST_SUBBAND_SELECT, nFpgas, 1+C_N_crosslets_max, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_integration_interval_R", XST_INTEGRATION_INTERVAL, nFpgas, 1, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_xst_integration_interval_RW", XST_INTEGRATION_INTERVAL, nFpgas, 1, "RW", REG_FORMAT_DOUBLE);
- pointMap->add_register("FPGA_xst_processing_enable_R", XST_PROCESSING_ENABLE, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_processing_enable_RW", XST_PROCESSING_ENABLE, nFpgas, 1, "RW", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_offload_enable_R", XST_OFFLOAD_ENABLE, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_offload_enable_RW", XST_OFFLOAD_ENABLE, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_xst_processing_enable_R", XST_PROCESSING_ENABLE, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_processing_enable_RW", XST_PROCESSING_ENABLE, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_offload_enable_R", XST_OFFLOAD_ENABLE, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_offload_enable_RW", XST_OFFLOAD_ENABLE, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_xst_offload_nof_crosslets_R", XST_OFFLOAD_NOF_CROSSLETS, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_offload_nof_crosslets_RW", XST_OFFLOAD_NOF_CROSSLETS, nFpgas, 1, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_offload_hdr_eth_destination_mac_R", XST_OFFLOAD_HDR_ETH_DESTINATION_MAC, nFpgas, 1, "RO", REG_FORMAT_STRING);
@@ -122,10 +122,10 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_xst_offload_bsn_R", XST_OFFLOAD_BSN, nFpgas, 1, "RO", REG_FORMAT_INT64);
pointMap->add_register("FPGA_xst_ring_nof_transport_hops_R", XST_RING_NOF_TRANSPORT_HOPS, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_ring_nof_transport_hops_RW", XST_RING_NOF_TRANSPORT_HOPS, nFpgas, 1, "RW", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_xst_ring_rx_clear_total_counts_R", XST_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_ring_rx_clear_total_counts_RW", XST_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, 1, "RW", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_rx_align_stream_enable_R", XST_RX_ALIGN_STREAM_ENABLE, nFpgas, C_P_sq, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_xst_rx_align_stream_enable_RW", XST_RX_ALIGN_STREAM_ENABLE, nFpgas, C_P_sq, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_xst_ring_rx_clear_total_counts_R", XST_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_ring_rx_clear_total_counts_RW", XST_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_rx_align_stream_enable_R", XST_RX_ALIGN_STREAM_ENABLE, nFpgas, C_P_sq, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_xst_rx_align_stream_enable_RW", XST_RX_ALIGN_STREAM_ENABLE, nFpgas, C_P_sq, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_xst_rx_align_nof_replaced_packets_R", XST_RX_ALIGN_NOF_REPLACED_PACKETS, nFpgas, C_P_sq, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_xst_ring_rx_total_nof_packets_received_R", XST_RING_RX_TOTAL_NOF_PACKETS_RECEIVED, nFpgas, 1, "RO", REG_FORMAT_UINT64);
pointMap->add_register("FPGA_xst_ring_rx_total_nof_packets_discarded_R", XST_RING_RX_TOTAL_NOF_PACKETS_DISCARDED, nFpgas, 1, "RO", REG_FORMAT_UINT32);
@@ -148,8 +148,8 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_xst_ring_tx_nof_valid_R", XST_RING_TX_NOF_VALID, nFpgas, nFpgas, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_xst_ring_tx_latency_R", XST_RING_TX_LATENCY, nFpgas, nFpgas, "RO", REG_FORMAT_INT32);
- pointMap->add_register("FPGA_beamlet_output_enable_R", BEAMLET_OUTPUT_ENABLE, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_beamlet_output_enable_RW", BEAMLET_OUTPUT_ENABLE, nFpgas, nBeamsets, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_beamlet_output_enable_R", BEAMLET_OUTPUT_ENABLE, nFpgas, nBeamsets, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_beamlet_output_enable_RW", BEAMLET_OUTPUT_ENABLE, nFpgas, nBeamsets, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_beamlet_output_scale_R", BEAMLET_OUTPUT_SCALE, nFpgas, nBeamsets, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_beamlet_output_scale_RW", BEAMLET_OUTPUT_SCALE, nFpgas, nBeamsets, "RW", REG_FORMAT_DOUBLE);
// pointMap->add_register("FPGA_beamlet_output_nof_beamlets_R", BEAMLET_OUTPUT_NOF_BEAMLETS, nFpgas, 1, "RO", REG_FORMAT_UINT32); // not implemented in sdpfw
@@ -171,11 +171,11 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_beamlet_output_nof_packets_R", BEAMLET_OUTPUT_NOF_PACKETS, nFpgas, nBeamsets, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_beamlet_output_nof_valid_R", BEAMLET_OUTPUT_NOF_VALID, nFpgas, nBeamsets, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_beamlet_output_bsn_R", BEAMLET_OUTPUT_BSN, nFpgas, nBeamsets, "RO", REG_FORMAT_INT64);
- pointMap->add_register("FPGA_beamlet_output_ready_R", BEAMLET_OUTPUT_READY, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_beamlet_output_xon_R", BEAMLET_OUTPUT_XON, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_beamlet_output_ready_R", BEAMLET_OUTPUT_READY, nFpgas, nBeamsets, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_beamlet_output_xon_R", BEAMLET_OUTPUT_XON, nFpgas, nBeamsets, "RO", REG_FORMAT_BOOLEAN);
- pointMap->add_register("FPGA_processing_enable_R", PROCESSING_ENABLE, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_processing_enable_RW", PROCESSING_ENABLE, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_processing_enable_R", PROCESSING_ENABLE, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_processing_enable_RW", PROCESSING_ENABLE, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_sdp_info_station_id_R", SDP_INFO_STATION_ID, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_sdp_info_station_id_RW", SDP_INFO_STATION_ID, nFpgas, 1, "RW", REG_FORMAT_UINT32);
@@ -189,8 +189,8 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_sdp_info_fsub_type_R", SDP_INFO_FSUB_TYPE, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_sdp_info_block_period_R", SDP_INFO_BLOCK_PERIOD, nFpgas, 1, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_wg_enable_R", WG_ENABLE, nFpgas, C_S_pn, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_wg_enable_RW", WG_ENABLE, nFpgas, C_S_pn, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_wg_enable_R", WG_ENABLE, nFpgas, C_S_pn, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_wg_enable_RW", WG_ENABLE, nFpgas, C_S_pn, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_wg_amplitude_R", WG_AMPLITUDE, nFpgas, C_S_pn, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_wg_amplitude_RW", WG_AMPLITUDE, nFpgas, C_S_pn, "RW", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_wg_phase_R", WG_PHASE, nFpgas, C_S_pn, "RO", REG_FORMAT_DOUBLE);
@@ -238,10 +238,10 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_bf_weights_yy_RW", BF_WEIGHTS_YY, nFpgas, C_A_pn* nBeamsets*C_S_sub_bf, "RW", REG_FORMAT_UINT32); // cint16
pointMap->add_register("FPGA_bf_ring_nof_transport_hops_R", BF_RING_NOF_TRANSPORT_HOPS, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_bf_ring_nof_transport_hops_RW", BF_RING_NOF_TRANSPORT_HOPS, nFpgas, nBeamsets, "RW", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_bf_ring_rx_clear_total_counts_R", BF_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_bf_ring_rx_clear_total_counts_RW", BF_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, nBeamsets, "RW", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_bf_rx_align_stream_enable_R", BF_RX_ALIGN_STREAM_ENABLE, nFpgas, nBeamsets*C_P_sum, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_bf_rx_align_stream_enable_RW", BF_RX_ALIGN_STREAM_ENABLE, nFpgas, nBeamsets*C_P_sum, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_bf_ring_rx_clear_total_counts_R", BF_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, nBeamsets, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_bf_ring_rx_clear_total_counts_RW", BF_RING_RX_CLEAR_TOTAL_COUNTS, nFpgas, nBeamsets, "RW", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_bf_rx_align_stream_enable_R", BF_RX_ALIGN_STREAM_ENABLE, nFpgas, nBeamsets*C_P_sum, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_bf_rx_align_stream_enable_RW", BF_RX_ALIGN_STREAM_ENABLE, nFpgas, nBeamsets*C_P_sum, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bf_rx_align_nof_replaced_packets_R", BF_RX_ALIGN_NOF_REPLACED_PACKETS, nFpgas, nBeamsets*C_P_sum, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_bf_ring_rx_total_nof_packets_received_R", BF_RING_RX_TOTAL_NOF_PACKETS_RECEIVED, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT64);
pointMap->add_register("FPGA_bf_ring_rx_total_nof_packets_discarded_R", BF_RING_RX_TOTAL_NOF_PACKETS_DISCARDED, nFpgas, nBeamsets, "RO", REG_FORMAT_UINT32);
@@ -266,11 +266,11 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_signal_input_data_buffer_R", SIGNAL_INPUT_DATA_BUFFER, nFpgas, C_S_pn*C_V_si_db, "RO", REG_FORMAT_INT16);
pointMap->add_register("FPGA_signal_input_histogram_R", SIGNAL_INPUT_HISTOGRAM, nFpgas, C_S_pn*C_V_si_histogram, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_subband_spectral_inversion_R", SUBBAND_SPECTRAL_INVERSION, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_subband_spectral_inversion_RW", SUBBAND_SPECTRAL_INVERSION, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_subband_spectral_inversion_R", SUBBAND_SPECTRAL_INVERSION, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_subband_spectral_inversion_RW", SUBBAND_SPECTRAL_INVERSION, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_pps_expected_cnt_R", PPS_EXPECTED_CNT, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_pps_expected_cnt_RW", PPS_EXPECTED_CNT, nFpgas, 1, "RW", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_pps_present_R", PPS_PRESENT, nFpgas, 1, "RO", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_pps_present_R", PPS_PRESENT, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_pps_capture_cnt_R", PPS_CAPTURE_CNT, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_monitor_pps_offset_time_R", MONITOR_PPS_OFFSET_TIME, nFpgas, 1, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_time_since_last_pps_R", TIME_SINCE_LAST_PPS, nFpgas, 1, "RO", REG_FORMAT_DOUBLE);
@@ -290,10 +290,10 @@ FpgaMap::FpgaMap()
pointMap->add_register("FPGA_ring_node_offset_RW", RING_NODE_OFFSET, nFpgas, 1, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_ring_nof_nodes_R", RING_NOF_NODES, nFpgas, 1, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_ring_nof_nodes_RW", RING_NOF_NODES, nFpgas, 1, "RW", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_ring_use_cable_to_next_rn_R", RING_USE_CABLE_TO_NEXT_RN, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_ring_use_cable_to_next_rn_RW", RING_USE_CABLE_TO_NEXT_RN, nFpgas, 1, "RW", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_ring_use_cable_to_previous_rn_R", RING_USE_CABLE_TO_PREVIOUS_RN, nFpgas, 1, "RO", REG_FORMAT_UINT8);
- pointMap->add_register("FPGA_ring_use_cable_to_previous_rn_RW", RING_USE_CABLE_TO_PREVIOUS_RN, nFpgas, 1, "RW", REG_FORMAT_UINT8);
+ pointMap->add_register("FPGA_ring_use_cable_to_next_rn_R", RING_USE_CABLE_TO_NEXT_RN, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_ring_use_cable_to_next_rn_RW", RING_USE_CABLE_TO_NEXT_RN, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_ring_use_cable_to_previous_rn_R", RING_USE_CABLE_TO_PREVIOUS_RN, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN);
+ pointMap->add_register("FPGA_ring_use_cable_to_previous_rn_RW", RING_USE_CABLE_TO_PREVIOUS_RN, nFpgas, 1, "RW", REG_FORMAT_BOOLEAN);
}
FpgaMap::~FpgaMap()
--
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