diff --git a/CDB/stations/LTS_ConfigDb.json b/CDB/stations/LTS_ConfigDb.json
index f2da845d2ff61156028d44cad795aae366288d71..7279907140d5f3594173db7ad7dba7cdda816619 100644
--- a/CDB/stations/LTS_ConfigDb.json
+++ b/CDB/stations/LTS_ConfigDb.json
@@ -38,40 +38,58 @@
                                 "5.0"
                             ],
                             "FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00",
-                                "00:07:43:06:c7:00"
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64",
+                                "90:e2:ba:7a:a9:64"
                             ],
                             "FPGA_beamlet_output_hdr_ip_destination_address_RW_default": [
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254",
-                                "192.168.0.254"
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249",
+                                "192.168.2.249"
+                            ],
+                            "FPGA_beamlet_offload_hdr_udp_destination_port_RW_default": [
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234",
+                                "1234"
                             ]
                         }
                     }
@@ -116,7 +134,7 @@
                             "TR_fpga_mask_RW_default": [
                                 "False", "False", "False", "False",
                                 "False", "False", "False", "False",
-                                "True",  "True",  "True",  "True",
+                                "False", "False", "False",  "True",
                                 "False", "False", "False", "False"
                             ],
                             "FPGA_sdp_info_station_id_RW_default": [