diff --git a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
index 5307b17045e7299964475a9051f10ce0e8fb1adb..4956f09fdbc1d2b412f93022d8a85f5200fa47c5 100644
--- a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
+++ b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
@@ -149,8 +149,13 @@ class SDP(opcua_device):
     TR_tod_R = attribute_wrapper(comms_annotation=["TR_tod_R"], datatype=numpy.int64, dims=(2,))
     TR_tod_pps_delta_R = attribute_wrapper(comms_annotation=["TR_tod_pps_delta_R"], datatype=numpy.double)
 
+    # TODO: needs to not be statically declared as this can change depending on the station and configuration
     S_pn = 12 # Number of ADC signal inputs per Processing Node (PN) FPGA.
     N_pn = 16 # Number of FPGAs per antenna band that is controlled via the SC - SDP interface.
+    A_pn = 6
+    N_pol = 2
+    N_beamlets_ctrl = 488
+    N_pol_bf = 2
 
     # OPC-UA MP only points for AIT
     FPGA_signal_input_mean_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_mean_R"], datatype=numpy.double , dims=(S_pn, N_pn))
@@ -165,10 +170,58 @@ class SDP(opcua_device):
     FPGA_bsn_monitor_input_nof_packets_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_packets_R"], datatype=numpy.int32, dims=(N_pn,))
     FPGA_bsn_monitor_input_nof_valid_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_valid_R"], datatype=numpy.int32, dims=(N_pn,))
     FPGA_bsn_monitor_input_nof_err_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_err_R"], datatype=numpy.int32, dims=(N_pn,))
-
     FPGA_signal_input_samples_delay_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
     FPGA_signal_input_samples_delay_RW = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_RW"], datatype=numpy.uint32, dims=(S_pn, N_pn), access=AttrWriteType.READ_WRITE)
 
+    # List of OPC-UA CP for BF beamlets
+
+    # cint16[N_pn][A_pn][N_pol][N_beamlets_ctrl]
+    # Co-polarization BF weights. The N_pol = 2 parameter index is:
+    # 0 for antenna polarization X in beamlet polarization X,
+    # 1 for antenna polarization Y in beamlet polarization Y.
+    FPGA_bf_weights_xx_yy_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_yy_R"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xx_yy_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_yy_RW"], datatype=numpy.int16, dims=(A_pn * N_pol *  N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+    # cint16[N_pn][A_pn][N_pol][N_beamlets_ctrl]
+    # Cross-polarization BF weights. The N_pol = 2 parameter index is (note that index pol in range 0:N_pol-1 is the antenna polarization, so index !pol is the beamlet polarization):
+    # 0 for antenna polarization X in beamlet polarization Y,
+    # 1 for antenna polarization Y in beamlet polarization X.
+    FPGA_bf_weights_xy_yx_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_yx_R"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xy_yx_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_yx_RW"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+    # cint16[N_pn][N_pol_bf][A_pn][N_pol][N_beamlets_ctrl]
+    # Full Jones matrix of BF weights.
+    FPGA_bf_weights_xx_xy_yx_yy_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_xy_yx_yy_R"], datatype=numpy.int16, dims=(N_pol_bf * A_pn * N_pol * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xx_xy_yx_yy_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_xy_yx_yy_RW"], datatype=numpy.int16, dims=(N_pol_bf * A_pn * N_pol * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+    # cint16[N_pn][A_pn][N_pol][N_beamlets_ctrl]
+    # Single polarization BF weights using only antenna polarization X. Only X polarization antennas contribute to the X and Y polarization beamlets,
+    # so this can form twice as many, but only X polarization, beams. The N_pol = 2 parameter index is:
+    # 0 for antenna polarization X in beamlet polarization X,
+    # 1 for antenna polarization X in beamlet polarization Y.
+    FPGA_bf_weights_xx_yx_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_yx_R"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xx_yx_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_yx_RW"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+    # cint16[N_pn][A_pn][N_pol][N_beamlets_ctrl]
+    # Single polarization BF weights using only antenna polarization Y. Only Y polarization antennas contribute to the X and Y polarization beamlets,
+    # so this can form twice as many, but only Y polarization, beams. The N_pol = 2 parameter index is:
+    # 0 for antenna polarization Y in beamlet polarization X,
+    # 1 for antenna polarization Y in beamlet polarization Y.
+    FPGA_bf_weights_xy_yy_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_yy_R"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xy_yy_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_yy_RW"], datatype=numpy.int16, dims=(A_pn * N_pol * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+    # cint16[N_pn][A_pn][N_beamlets_ctrl]
+    # BF weights for separate access to respectively w_xx, w_xy, w_yx, and w_yy.
+    FPGA_bf_weights_xx_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_R"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xx_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xx_RW"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+    FPGA_bf_weights_xy_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_R"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_xy_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_xy_RW"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+    FPGA_bf_weights_yx_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_yx_R"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_yx_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_yx_RW"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+    FPGA_bf_weights_yy_R = attribute_wrapper(comms_annotation=["FPGA_bf_weights_yy_R"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn))
+    FPGA_bf_weights_yy_RW = attribute_wrapper(comms_annotation=["FPGA_bf_weights_yy_RW"], datatype=numpy.int16, dims=(A_pn * N_beamlets_ctrl, N_pn), access=AttrWriteType.READ_WRITE)
+
+
 
     # --------
     # overloaded functions
@@ -183,4 +236,4 @@ class SDP(opcua_device):
 # ----------
 def main(**kwargs):
     """Main function of the SDP module."""
-    return entry(SDP, **kwargs)
+    return entry(SDP, **kwargs)
\ No newline at end of file