From 646598b5279f8c311f456229e42b9eda5b7c7015 Mon Sep 17 00:00:00 2001
From: thijs snijder <snijder@astron.nl>
Date: Mon, 8 Nov 2021 15:40:14 +0100
Subject: [PATCH] changed type from int32 to uint32
---
tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
index 0749755a1..ed970bc56 100644
--- a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
+++ b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
@@ -161,8 +161,8 @@ class SDP(opcua_device):
FPGA_bsn_monitor_input_nof_valid_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_valid_R"], datatype=numpy.int32, dims=(N_pn,))
FPGA_bsn_monitor_input_nof_err_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_err_R"], datatype=numpy.int32, dims=(N_pn,))
- FPGA_signal_input_samples_delay_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_R"], datatype=numpy.int32, dims=(S_pn, N_pn))
- FPGA_signal_input_samples_delay_RW = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_RW"], datatype=numpy.int32, dims=(S_pn, N_pn), access=AttrWriteType.READ_WRITE)
+ FPGA_signal_input_samples_delay_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
+ FPGA_signal_input_samples_delay_RW = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_RW"], datatype=numpy.uint32, dims=(S_pn, N_pn), access=AttrWriteType.READ_WRITE)
# --------
--
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