diff --git a/CDB/stations/DTS_ConfigDb.json b/CDB/stations/DTS_ConfigDb.json
index 685a3d62da82e40aa05ea409c20f2475e3472ea5..48f333e2b01a05a9b2ae700cedee61e5fb396579 100644
--- a/CDB/stations/DTS_ConfigDb.json
+++ b/CDB/stations/DTS_ConfigDb.json
@@ -63,7 +63,7 @@
"LTS/SDP/1": {
"properties": {
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "10.99.0.252"
],
"OPC_Server_Port": [
"4840"
@@ -100,7 +100,7 @@
"LTS/SST/1": {
"properties": {
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "10.99.0.252"
],
"OPC_Server_Port": [
"4840"
@@ -127,22 +127,22 @@
"0c:c4:7a:c0:30:f1"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1"
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250"
]
}
}
@@ -155,7 +155,7 @@
"LTS/XST/1": {
"properties": {
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "10.99.0.252"
],
"OPC_Server_Port": [
"4840"
@@ -182,22 +182,22 @@
"0c:c4:7a:c0:30:f1"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1",
- "10.99.0.1"
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250",
+ "10.99.250.250"
]
}
}
diff --git a/CDB/stations/LTS_ConfigDb.json b/CDB/stations/LTS_ConfigDb.json
index 672ff0210a9bad8ed6c48db2f648393b8cee0069..ae87cfeaf8a1ceda043ecc3f130776fa73e944bc 100644
--- a/CDB/stations/LTS_ConfigDb.json
+++ b/CDB/stations/LTS_ConfigDb.json
@@ -72,7 +72,7 @@
"LTS/SDP/1": {
"properties": {
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "dop369.astron.nl"
],
"OPC_Server_Port": [
"4840"
@@ -115,7 +115,7 @@
"5101"
],
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "dop369.astron.nl"
],
"OPC_Server_Port": [
"4840"
@@ -194,7 +194,7 @@
"5102"
],
"OPC_Server_Name": [
- "dop36.astron.nl"
+ "dop369.astron.nl"
],
"OPC_Server_Port": [
"4840"
diff --git a/devices/devices/apsct.py b/devices/devices/apsct.py
index c8b0cb0ad8843fc44fd6c3e298d3a6cfd15d6f5f..78a0626d8a12985d944c752e544aff93209373be 100644
--- a/devices/devices/apsct.py
+++ b/devices/devices/apsct.py
@@ -46,11 +46,14 @@ class APSCT(opcua_device):
# Attributes
# ----------
+ APSCTTR_I2C_error_R = attribute_wrapper(comms_annotation=["APSCTTR_I2C_error_R" ],datatype=numpy.int64 )
+ APSCTTR_monitor_rate_RW = attribute_wrapper(comms_annotation=["APSCTTR_monitor_rate_RW" ],datatype=numpy.int64 , access=AttrWriteType.READ_WRITE)
APSCTTR_translator_busy_R = attribute_wrapper(comms_annotation=["APSCTTR_translator_busy_R" ],datatype=numpy.bool_ )
- APSCT_I2C_error_R = attribute_wrapper(comms_annotation=["APSCT_I2C_error_R" ],datatype=numpy.int64 )
- APSCT_ID_R = attribute_wrapper(comms_annotation=["APSCT_ID_R" ],datatype=numpy.int64 )
APSCT_INPUT_10MHz_good_R = attribute_wrapper(comms_annotation=["APSCT_INPUT_10MHz_good_R" ],datatype=numpy.bool_ )
APSCT_INPUT_PPS_good_R = attribute_wrapper(comms_annotation=["APSCT_INPUT_PPS_good_R" ],datatype=numpy.bool_ )
+ APSCT_PCB_ID_R = attribute_wrapper(comms_annotation=["APSCT_PCB_ID_R" ],datatype=numpy.int64 )
+ APSCT_PCB_number_R = attribute_wrapper(comms_annotation=["APSCT_PCB_number_R" ],datatype=numpy.str )
+ APSCT_PCB_version_R = attribute_wrapper(comms_annotation=["APSCT_PCB_version_R" ],datatype=numpy.str )
APSCT_PLL_160MHz_error_R = attribute_wrapper(comms_annotation=["APSCT_PLL_160MHz_error_R" ],datatype=numpy.bool_ )
APSCT_PLL_160MHz_locked_R = attribute_wrapper(comms_annotation=["APSCT_PLL_160MHz_locked_R" ],datatype=numpy.bool_ )
APSCT_PLL_200MHz_error_R = attribute_wrapper(comms_annotation=["APSCT_PLL_200MHz_error_R" ],datatype=numpy.bool_ )
@@ -67,8 +70,7 @@ class APSCT(opcua_device):
APSCT_PWR_PLL_200MHz_3V3_R = attribute_wrapper(comms_annotation=["APSCT_PWR_PLL_200MHz_3V3_R"],datatype=numpy.float64)
APSCT_PWR_PLL_200MHz_on_R = attribute_wrapper(comms_annotation=["APSCT_PWR_PLL_200MHz_on_R" ],datatype=numpy.bool_ )
APSCT_PWR_PPSDIST_3V3_R = attribute_wrapper(comms_annotation=["APSCT_PWR_PPSDIST_3V3_R" ],datatype=numpy.float64)
- APSCT_temperature_R = attribute_wrapper(comms_annotation=["APSCT_temperature_R" ],datatype=numpy.float64)
- APSCT_version_R = attribute_wrapper(comms_annotation=["APSCT_version_R" ],datatype=numpy.str )
+ APSCT_TEMP_R = attribute_wrapper(comms_annotation=["APSCT_TEMP_R" ],datatype=numpy.float64)
# --------
# overloaded functions
diff --git a/devices/devices/apspu.py b/devices/devices/apspu.py
index cec9e56364a7c78d8938d0fb9241a840d1e0f95e..3daab9c071a73b75a4d28def984d4794d4aa7aef 100644
--- a/devices/devices/apspu.py
+++ b/devices/devices/apspu.py
@@ -43,22 +43,24 @@ class APSPU(opcua_device):
# Attributes
# ----------
+ APSPUTR_I2C_error_R = attribute_wrapper(comms_annotation=["APSPUTR_I2C_error_R" ],datatype=numpy.int64 )
+ APSPUTR_monitor_rate_RW = attribute_wrapper(comms_annotation=["APSPUTR_monitor_rate_RW" ],datatype=numpy.int64 , access=AttrWriteType.READ_WRITE)
APSPUTR_translator_busy_R = attribute_wrapper(comms_annotation=["APSPUTR_translator_busy_R" ],datatype=numpy.bool_ )
- APSPU_FAN1_RMS_R = attribute_wrapper(comms_annotation=["APSPU_FAN1_RMS_R" ],datatype=numpy.float64)
- APSPU_FAN2_RMS_R = attribute_wrapper(comms_annotation=["APSPU_FAN2_RMS_R" ],datatype=numpy.float64)
- APSPU_FAN3_RMS_R = attribute_wrapper(comms_annotation=["APSPU_FAN3_RMS_R" ],datatype=numpy.float64)
- APSPU_I2C_error_R = attribute_wrapper(comms_annotation=["APSPU_I2C_error_R" ],datatype=numpy.int64 )
- APSPU_ID_R = attribute_wrapper(comms_annotation=["APSPU_ID_R" ],datatype=numpy.int64 )
+ APSPU_FAN1_RPM_R = attribute_wrapper(comms_annotation=["APSPU_FAN1_RPM_R" ],datatype=numpy.float64)
+ APSPU_FAN2_RPM_R = attribute_wrapper(comms_annotation=["APSPU_FAN2_RPM_R" ],datatype=numpy.float64)
+ APSPU_FAN3_RPM_R = attribute_wrapper(comms_annotation=["APSPU_FAN3_RPM_R" ],datatype=numpy.float64)
APSPU_LBA_IOUT_R = attribute_wrapper(comms_annotation=["APSPU_LBA_IOUT_R" ],datatype=numpy.float64)
APSPU_LBA_TEMP_R = attribute_wrapper(comms_annotation=["APSPU_LBA_TEMP_R" ],datatype=numpy.float64)
APSPU_LBA_VOUT_R = attribute_wrapper(comms_annotation=["APSPU_LBA_VOUT_R" ],datatype=numpy.float64)
+ APSPU_PCB_ID_R = attribute_wrapper(comms_annotation=["APSPU_PCB_ID_R" ],datatype=numpy.int64 )
+ APSPU_PCB_number_R = attribute_wrapper(comms_annotation=["APSPU_PCB_number_R" ],datatype=numpy.str )
+ APSPU_PCB_version_R = attribute_wrapper(comms_annotation=["APSPU_PCB_version_R" ],datatype=numpy.str )
APSPU_RCU2A_IOUT_R = attribute_wrapper(comms_annotation=["APSPU_RCU2A_IOUT_R" ],datatype=numpy.float64)
APSPU_RCU2A_TEMP_R = attribute_wrapper(comms_annotation=["APSPU_RCU2A_TEMP_R" ],datatype=numpy.float64)
APSPU_RCU2A_VOUT_R = attribute_wrapper(comms_annotation=["APSPU_RCU2A_VOUT_R" ],datatype=numpy.float64)
APSPU_RCU2D_IOUT_R = attribute_wrapper(comms_annotation=["APSPU_RCU2D_IOUT_R" ],datatype=numpy.float64)
APSPU_RCU2D_TEMP_R = attribute_wrapper(comms_annotation=["APSPU_RCU2D_TEMP_R" ],datatype=numpy.float64)
APSPU_RCU2D_VOUT_R = attribute_wrapper(comms_annotation=["APSPU_RCU2D_VOUT_R" ],datatype=numpy.float64)
- APSPU_version_R = attribute_wrapper(comms_annotation=["APSPU_version_R" ],datatype=numpy.str )
# --------
# overloaded functions
diff --git a/devices/devices/recv.py b/devices/devices/recv.py
index d180e955a56ee583a7a2fbc1a732d933c27acced..b5cc7f6e7cd6031d290f0d2509ec651dc181765a 100644
--- a/devices/devices/recv.py
+++ b/devices/devices/recv.py
@@ -63,11 +63,12 @@ class RECV(opcua_device):
# ----------
# Attributes
# ----------
- Ant_status_R = attribute(dtype=str, max_dim_x=3, max_dim_y=32)
+ ANT_status_R = attribute(dtype=str, max_dim_x=3, max_dim_y=32)
+ RCU_LED_colour_R = attribute(dtype=numpy.uint32, max_dim_x=32, fget=lambda self: (2 * self.RCU_LED_green_on_R + 4 * self.RCU_LED_red_on_R).astype(numpy.uint32))
ANT_mask_RW = attribute_wrapper(comms_annotation=["ANT_mask_RW" ],datatype=numpy.bool_ , dims=(3,32), access=AttrWriteType.READ_WRITE)
- HBAT_beamformer_delays_R = attribute_wrapper(comms_annotation=["HBAT_beamformer_delays_R" ],datatype=numpy.int64 , dims=(32,96))
- HBAT_beamformer_delays_RW = attribute_wrapper(comms_annotation=["HBAT_beamformer_delays_RW" ],datatype=numpy.int64 , dims=(32,96), access=AttrWriteType.READ_WRITE)
+ HBAT_BF_delays_R = attribute_wrapper(comms_annotation=["HBAT_BF_delays_R" ],datatype=numpy.int64 , dims=(32,96))
+ HBAT_BF_delays_RW = attribute_wrapper(comms_annotation=["HBAT_BF_delays_RW" ],datatype=numpy.int64 , dims=(32,96), access=AttrWriteType.READ_WRITE)
HBAT_LED_on_R = attribute_wrapper(comms_annotation=["HBAT_LED_on_R" ],datatype=numpy.bool_ , dims=(32,96))
HBAT_LED_on_RW = attribute_wrapper(comms_annotation=["HBAT_LED_on_RW" ],datatype=numpy.bool_ , dims=(32,96), access=AttrWriteType.READ_WRITE)
HBAT_PWR_LNA_on_R = attribute_wrapper(comms_annotation=["HBAT_PWR_LNA_on_R" ],datatype=numpy.bool_ , dims=(32,96))
@@ -82,14 +83,14 @@ class RECV(opcua_device):
RCU_DTH_freq_R = attribute_wrapper(comms_annotation=["RCU_DTH_freq_R" ],datatype=numpy.int64 , dims=(3,32))
RCU_DTH_freq_RW = attribute_wrapper(comms_annotation=["RCU_DTH_freq_RW" ],datatype=numpy.int64 , dims=(3,32), access=AttrWriteType.READ_WRITE)
RCU_DTH_on_R = attribute_wrapper(comms_annotation=["RCU_DTH_on_R" ],datatype=numpy.bool_ , dims=(3,32))
- RCU_DTH_shutdown_R = attribute_wrapper(comms_annotation=["RCU_DTH_shutdown_R" ],datatype=numpy.bool_ , dims=(3,32))
- RCU_I2C_error_R = attribute_wrapper(comms_annotation=["RCU_I2C_error_R" ],datatype=numpy.int64 , dims=(32,))
- RCU_ID_R = attribute_wrapper(comms_annotation=["RCU_ID_R" ],datatype=numpy.int64 , dims=(32,))
- RCU_LED_green_off_R = attribute_wrapper(comms_annotation=["RCU_LED_green_off_R" ],datatype=numpy.bool_ , dims=(32,))
- RCU_LED_green_off_RW = attribute_wrapper(comms_annotation=["RCU_LED_green_off_RW" ],datatype=numpy.bool_ , dims=(32,), access=AttrWriteType.READ_WRITE)
- RCU_LED_red_off_R = attribute_wrapper(comms_annotation=["RCU_LED_red_off_R" ],datatype=numpy.bool_ , dims=(32,))
- RCU_LED_red_off_RW = attribute_wrapper(comms_annotation=["RCU_LED_red_off_RW" ],datatype=numpy.bool_ , dims=(32,), access=AttrWriteType.READ_WRITE)
+ RCU_LED_green_on_R = attribute_wrapper(comms_annotation=["RCU_LED_green_on_R" ],datatype=numpy.bool_ , dims=(32,))
+ RCU_LED_green_on_RW = attribute_wrapper(comms_annotation=["RCU_LED_green_on_RW" ],datatype=numpy.bool_ , dims=(32,), access=AttrWriteType.READ_WRITE)
+ RCU_LED_red_on_R = attribute_wrapper(comms_annotation=["RCU_LED_red_on_R" ],datatype=numpy.bool_ , dims=(32,))
+ RCU_LED_red_on_RW = attribute_wrapper(comms_annotation=["RCU_LED_red_on_RW" ],datatype=numpy.bool_ , dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_mask_RW = attribute_wrapper(comms_annotation=["RCU_mask_RW" ],datatype=numpy.bool_ , dims=(32,), access=AttrWriteType.READ_WRITE)
+ RCU_PCB_ID_R = attribute_wrapper(comms_annotation=["RCU_PCB_ID_R" ],datatype=numpy.int64 , dims=(32,))
+ RCU_PCB_number_R = attribute_wrapper(comms_annotation=["RCU_PCB_number_R" ],datatype=numpy.str , dims=(32,))
+ RCU_PCB_version_R = attribute_wrapper(comms_annotation=["RCU_PCB_version_R" ],datatype=numpy.str , dims=(32,))
RCU_PWR_1V8_R = attribute_wrapper(comms_annotation=["RCU_PWR_1V8_R" ],datatype=numpy.float64, dims=(32,))
RCU_PWR_2V5_R = attribute_wrapper(comms_annotation=["RCU_PWR_2V5_R" ],datatype=numpy.float64, dims=(32,))
RCU_PWR_3V3_R = attribute_wrapper(comms_annotation=["RCU_PWR_3V3_R" ],datatype=numpy.float64, dims=(32,))
@@ -101,8 +102,9 @@ class RECV(opcua_device):
RCU_PWR_ANT_VOUT_R = attribute_wrapper(comms_annotation=["RCU_PWR_ANT_VOUT_R" ],datatype=numpy.float64, dims=(3,32))
RCU_PWR_DIGITAL_on_R = attribute_wrapper(comms_annotation=["RCU_PWR_DIGITAL_on_R" ],datatype=numpy.bool_ , dims=(32,))
RCU_PWR_good_R = attribute_wrapper(comms_annotation=["RCU_PWR_good_R" ],datatype=numpy.bool_ , dims=(32,))
- RCU_temperature_R = attribute_wrapper(comms_annotation=["RCU_temperature_R" ],datatype=numpy.float64, dims=(32,))
- RCU_version_R = attribute_wrapper(comms_annotation=["RCU_version_R" ],datatype=numpy.str , dims=(32,))
+ RCU_TEMP_R = attribute_wrapper(comms_annotation=["RCU_TEMP_R" ],datatype=numpy.float64, dims=(32,))
+ RECVTR_I2C_error_R = attribute_wrapper(comms_annotation=["RECVTR_I2C_error_R" ],datatype=numpy.int64 , dims=(32,))
+ RECVTR_monitor_rate_RW = attribute_wrapper(comms_annotation=["RECVTR_monitor_rate_RW" ],datatype=numpy.int64 , access=AttrWriteType.READ_WRITE)
RECVTR_translator_busy_R = attribute_wrapper(comms_annotation=["RECVTR_translator_busy_R" ],datatype=numpy.bool_ )
# --------
@@ -191,7 +193,7 @@ class RECV(opcua_device):
return rcu_status
- def read_Ant_status_R(self):
+ def read_ANT_status_R(self):
""" Returns a set of strings denoting the status of each antenna.
An empty string means no problems were detected. A non-empty
@@ -199,9 +201,9 @@ class RECV(opcua_device):
This function can be used as input to modify the Ant_mask_RW. """
- ant_mask = self.Ant_mask_RW
+ ant_mask = self.ANT_mask_RW
rcu_mask = self.RCU_mask_RW
- adc_lock = self.RCU_ADC_lock_R
+ adc_lock = self.RCU_ADC_locked_R
i2c_errors = self.RCU_I2C_STATUS_R
nr_rcus = len(ant_mask)
diff --git a/devices/devices/sdp/sdp.py b/devices/devices/sdp/sdp.py
index 6cdfe9a2b2788f1b3466bbdb38a4ca5c83e9780f..d41d50af989c47ec0ee2fac3f0349bf8f00a3d53 100644
--- a/devices/devices/sdp/sdp.py
+++ b/devices/devices/sdp/sdp.py
@@ -99,73 +99,73 @@ class SDP(opcua_device):
# Attributes
# ----------
- FPGA_beamlet_output_enable_R = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_enable_R"], datatype=numpy.bool_, dims=(16,))
- FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_beamlet_output_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
- FPGA_beamlet_output_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_beamlet_output_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
- FPGA_beamlet_output_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_beamlet_output_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
- FPGA_beamlet_output_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_beamlet_output_scale_R = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_scale_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_beamlet_output_scale_RW = attribute_wrapper(comms_annotation=["2:FPGA_beamlet_output_scale_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_firmware_version_R = attribute_wrapper(comms_annotation=["2:FPGA_firmware_version_R"], datatype=numpy.str, dims=(16,))
- FPGA_global_node_index_R = attribute_wrapper(comms_annotation=["2:FPGA_global_node_index_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_hardware_version_R = attribute_wrapper(comms_annotation=["2:FPGA_hardware_version_R"], datatype=numpy.str, dims=(16,))
- FPGA_processing_enable_R = attribute_wrapper(comms_annotation=["2:FPGA_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
- FPGA_processing_enable_RW = attribute_wrapper(comms_annotation=["2:FPGA_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_scrap_R = attribute_wrapper(comms_annotation=["2:FPGA_scrap_R"], datatype=numpy.int32, dims=(8192,))
- FPGA_scrap_RW = attribute_wrapper(comms_annotation=["2:FPGA_scrap_RW"], datatype=numpy.int32, dims=(8192,), access=AttrWriteType.READ_WRITE)
- FPGA_sdp_info_antenna_band_index_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_antenna_band_index_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_block_period_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_block_period_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_f_adc_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_f_adc_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_fsub_type_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_fsub_type_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_nyquist_sampling_zone_index_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_nyquist_sampling_zone_index_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_nyquist_sampling_zone_index_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_nyquist_sampling_zone_index_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sdp_info_observation_id_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_observation_id_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_observation_id_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_observation_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sdp_info_station_id_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_station_id_R"], datatype=numpy.uint32, dims=(16,))
- FPGA_sdp_info_station_id_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_station_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_subband_weights_R = attribute_wrapper(comms_annotation=["2:FPGA_subband_weights_R"], datatype=numpy.uint32, dims=(12 * 512, 16))
- FPGA_subband_weights_RW = attribute_wrapper(comms_annotation=["2:FPGA_subband_weights_RW"], datatype=numpy.uint32, dims=(12 * 512, 16), access=AttrWriteType.READ_WRITE)
- FPGA_temp_R = attribute_wrapper(comms_annotation=["2:FPGA_temp_R"], datatype=numpy.float_, dims=(16,))
- FPGA_weights_R = attribute_wrapper(comms_annotation=["2:FPGA_weights_R"], datatype=numpy.int16, dims=(12 * 488 * 2, 16))
- FPGA_weights_RW = attribute_wrapper(comms_annotation=["2:FPGA_weights_RW"], datatype=numpy.int16, dims=(12 * 488 * 2, 16), access=AttrWriteType.READ_WRITE)
- FPGA_wg_amplitude_R = attribute_wrapper(comms_annotation=["2:FPGA_wg_amplitude_R"], datatype=numpy.float_, dims=(12, 16))
- FPGA_wg_amplitude_RW = attribute_wrapper(comms_annotation=["2:FPGA_wg_amplitude_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
- FPGA_wg_enable_R = attribute_wrapper(comms_annotation=["2:FPGA_wg_enable_R"], datatype=numpy.bool_, dims=(12, 16))
- FPGA_wg_enable_RW = attribute_wrapper(comms_annotation=["2:FPGA_wg_enable_RW"], datatype=numpy.bool_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
- FPGA_wg_frequency_R = attribute_wrapper(comms_annotation=["2:FPGA_wg_frequency_R"], datatype=numpy.float_, dims=(12, 16))
- FPGA_wg_frequency_RW = attribute_wrapper(comms_annotation=["2:FPGA_wg_frequency_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
- FPGA_wg_phase_R = attribute_wrapper(comms_annotation=["2:FPGA_wg_phase_R"], datatype=numpy.float_, dims=(12, 16))
- FPGA_wg_phase_RW = attribute_wrapper(comms_annotation=["2:FPGA_wg_phase_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
- TR_fpga_mask_R = attribute_wrapper(comms_annotation=["2:TR_fpga_mask_R"], datatype=numpy.bool_, dims=(16,))
- TR_fpga_mask_RW = attribute_wrapper(comms_annotation=["2:TR_fpga_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- TR_fpga_communication_error_R = attribute_wrapper(comms_annotation=["2:TR_fpga_communication_error_R"], datatype=numpy.bool_, dims=(16,))
- TR_sdp_config_first_fpga_nr_R = attribute_wrapper(comms_annotation=["2:TR_sdp_config_first_fpga_nr_R"], datatype=numpy.uint32)
- TR_sdp_config_nof_beamsets_R = attribute_wrapper(comms_annotation=["2:TR_sdp_config_nof_beamsets_R"], datatype=numpy.uint32)
- TR_sdp_config_nof_fpgas_R = attribute_wrapper(comms_annotation=["2:TR_sdp_config_nof_fpgas_R"], datatype=numpy.uint32)
- TR_software_version_R = attribute_wrapper(comms_annotation=["2:TR_software_version_R"], datatype=numpy.str)
- TR_start_time_R = attribute_wrapper(comms_annotation=["2:TR_start_time_R"], datatype=numpy.int64)
- TR_tod_R = attribute_wrapper(comms_annotation=["2:TR_tod_R"], datatype=numpy.int64, dims=(2,))
- TR_tod_pps_delta_R = attribute_wrapper(comms_annotation=["2:TR_tod_pps_delta_R"], datatype=numpy.double)
+ FPGA_beamlet_output_enable_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
+ FPGA_beamlet_output_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
+ FPGA_beamlet_output_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_beamlet_output_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_scale_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_beamlet_output_scale_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_firmware_version_R = attribute_wrapper(comms_annotation=["FPGA_firmware_version_R"], datatype=numpy.str, dims=(16,))
+ FPGA_global_node_index_R = attribute_wrapper(comms_annotation=["FPGA_global_node_index_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_hardware_version_R = attribute_wrapper(comms_annotation=["FPGA_hardware_version_R"], datatype=numpy.str, dims=(16,))
+ FPGA_processing_enable_R = attribute_wrapper(comms_annotation=["FPGA_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_processing_enable_RW = attribute_wrapper(comms_annotation=["FPGA_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_scrap_R = attribute_wrapper(comms_annotation=["FPGA_scrap_R"], datatype=numpy.int32, dims=(8192,))
+ FPGA_scrap_RW = attribute_wrapper(comms_annotation=["FPGA_scrap_RW"], datatype=numpy.int32, dims=(8192,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_antenna_band_index_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_antenna_band_index_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_block_period_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_block_period_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_f_adc_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_f_adc_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_fsub_type_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_fsub_type_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_nyquist_sampling_zone_index_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_nyquist_sampling_zone_index_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_nyquist_sampling_zone_index_RW = attribute_wrapper(comms_annotation=["FPGA_sdp_info_nyquist_sampling_zone_index_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_observation_id_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_observation_id_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_observation_id_RW = attribute_wrapper(comms_annotation=["FPGA_sdp_info_observation_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_station_id_R = attribute_wrapper(comms_annotation=["FPGA_sdp_info_station_id_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_station_id_RW = attribute_wrapper(comms_annotation=["FPGA_sdp_info_station_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_subband_weights_R = attribute_wrapper(comms_annotation=["FPGA_subband_weights_R"], datatype=numpy.uint32, dims=(12 * 512, 16))
+ FPGA_subband_weights_RW = attribute_wrapper(comms_annotation=["FPGA_subband_weights_RW"], datatype=numpy.uint32, dims=(12 * 512, 16), access=AttrWriteType.READ_WRITE)
+ FPGA_temp_R = attribute_wrapper(comms_annotation=["FPGA_temp_R"], datatype=numpy.float_, dims=(16,))
+ FPGA_weights_R = attribute_wrapper(comms_annotation=["FPGA_weights_R"], datatype=numpy.int16, dims=(12 * 488 * 2, 16))
+ FPGA_weights_RW = attribute_wrapper(comms_annotation=["FPGA_weights_RW"], datatype=numpy.int16, dims=(12 * 488 * 2, 16), access=AttrWriteType.READ_WRITE)
+ FPGA_wg_amplitude_R = attribute_wrapper(comms_annotation=["FPGA_wg_amplitude_R"], datatype=numpy.float_, dims=(12, 16))
+ FPGA_wg_amplitude_RW = attribute_wrapper(comms_annotation=["FPGA_wg_amplitude_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
+ FPGA_wg_enable_R = attribute_wrapper(comms_annotation=["FPGA_wg_enable_R"], datatype=numpy.bool_, dims=(12, 16))
+ FPGA_wg_enable_RW = attribute_wrapper(comms_annotation=["FPGA_wg_enable_RW"], datatype=numpy.bool_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
+ FPGA_wg_frequency_R = attribute_wrapper(comms_annotation=["FPGA_wg_frequency_R"], datatype=numpy.float_, dims=(12, 16))
+ FPGA_wg_frequency_RW = attribute_wrapper(comms_annotation=["FPGA_wg_frequency_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
+ FPGA_wg_phase_R = attribute_wrapper(comms_annotation=["FPGA_wg_phase_R"], datatype=numpy.float_, dims=(12, 16))
+ FPGA_wg_phase_RW = attribute_wrapper(comms_annotation=["FPGA_wg_phase_RW"], datatype=numpy.float_, dims=(12, 16), access=AttrWriteType.READ_WRITE)
+ TR_fpga_mask_R = attribute_wrapper(comms_annotation=["TR_fpga_mask_R"], datatype=numpy.bool_, dims=(16,))
+ TR_fpga_mask_RW = attribute_wrapper(comms_annotation=["TR_fpga_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ TR_fpga_communication_error_R = attribute_wrapper(comms_annotation=["TR_fpga_communication_error_R"], datatype=numpy.bool_, dims=(16,))
+ TR_sdp_config_first_fpga_nr_R = attribute_wrapper(comms_annotation=["TR_sdp_config_first_fpga_nr_R"], datatype=numpy.uint32)
+ TR_sdp_config_nof_beamsets_R = attribute_wrapper(comms_annotation=["TR_sdp_config_nof_beamsets_R"], datatype=numpy.uint32)
+ TR_sdp_config_nof_fpgas_R = attribute_wrapper(comms_annotation=["TR_sdp_config_nof_fpgas_R"], datatype=numpy.uint32)
+ TR_software_version_R = attribute_wrapper(comms_annotation=["TR_software_version_R"], datatype=numpy.str)
+ TR_start_time_R = attribute_wrapper(comms_annotation=["TR_start_time_R"], datatype=numpy.int64)
+ TR_tod_R = attribute_wrapper(comms_annotation=["TR_tod_R"], datatype=numpy.int64, dims=(2,))
+ TR_tod_pps_delta_R = attribute_wrapper(comms_annotation=["TR_tod_pps_delta_R"], datatype=numpy.double)
S_pn = 12 # Number of ADC signal inputs per Processing Node (PN) FPGA.
N_pn = 16 # Number of FPGAs per antenna band that is controlled via the SC - SDP interface.
# OPC-UA MP only points for AIT
- FPGA_signal_input_mean_R = attribute_wrapper(comms_annotation=["2:FPGA_signal_input_mean_R"], datatype=numpy.double , dims=(S_pn, N_pn))
- FPGA_signal_input_rms_R = attribute_wrapper(comms_annotation=["2:FPGA_signal_input_rms_R"], datatype=numpy.double, dims=(S_pn, N_pn))
-
- FPGA_jesd204b_csr_rbd_count_R = attribute_wrapper(comms_annotation=["2:FPGA_jesd204b_csr_rbd_count_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
- FPGA_jesd204b_csr_dev_syncn_R = attribute_wrapper(comms_annotation=["2:FPGA_jesd204b_csr_dev_syncn_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
- FPGA_jesd204b_rx_err0_R = attribute_wrapper(comms_annotation=["2:FPGA_jesd204b_rx_err0_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
- FPGA_jesd204b_rx_err1_R = attribute_wrapper(comms_annotation=["2:FPGA_jesd204b_rx_err1_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
-
- FPGA_bsn_monitor_input_bsn_R = attribute_wrapper(comms_annotation=["2:FPGA_bsn_monitor_input_bsn_R"], datatype=numpy.int64, dims=(N_pn,))
- FPGA_bsn_monitor_input_nof_packets_R = attribute_wrapper(comms_annotation=["2:FPGA_bsn_monitor_input_nof_packets_R"], datatype=numpy.int32, dims=(N_pn,))
- FPGA_bsn_monitor_input_nof_valid_R = attribute_wrapper(comms_annotation=["2:FPGA_bsn_monitor_input_nof_valid_R"], datatype=numpy.int32, dims=(N_pn,))
- FPGA_bsn_monitor_input_nof_err_R = attribute_wrapper(comms_annotation=["2:FPGA_bsn_monitor_input_nof_err_R"], datatype=numpy.int32, dims=(N_pn,))
+ FPGA_signal_input_mean_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_mean_R"], datatype=numpy.double , dims=(S_pn, N_pn))
+ FPGA_signal_input_rms_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_rms_R"], datatype=numpy.double, dims=(S_pn, N_pn))
+
+ FPGA_jesd204b_csr_rbd_count_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_csr_rbd_count_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
+ FPGA_jesd204b_csr_dev_syncn_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_csr_dev_syncn_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
+ FPGA_jesd204b_rx_err0_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_rx_err0_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
+ FPGA_jesd204b_rx_err1_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_rx_err1_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
+
+ FPGA_bsn_monitor_input_bsn_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_bsn_R"], datatype=numpy.int64, dims=(N_pn,))
+ FPGA_bsn_monitor_input_nof_packets_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_packets_R"], datatype=numpy.int32, dims=(N_pn,))
+ FPGA_bsn_monitor_input_nof_valid_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_valid_R"], datatype=numpy.int32, dims=(N_pn,))
+ FPGA_bsn_monitor_input_nof_err_R = attribute_wrapper(comms_annotation=["FPGA_bsn_monitor_input_nof_err_R"], datatype=numpy.int32, dims=(N_pn,))
# --------
diff --git a/devices/devices/sdp/sst.py b/devices/devices/sdp/sst.py
index 277714ab0b7ada6882a5ec1086690b3c29fb2382..d790170bb997f5e69044a2ef45754e04b9d62d1c 100644
--- a/devices/devices/sdp/sst.py
+++ b/devices/devices/sdp/sst.py
@@ -85,16 +85,16 @@ class SST(Statistics):
# ----------
# FPGA control points for SSTs
- FPGA_sst_offload_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sst_offload_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
- FPGA_sst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
- FPGA_sst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
- FPGA_sst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
- FPGA_sst_offload_weighted_subbands_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_weighted_subbands_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_sst_offload_weighted_subbands_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_sst_offload_weighted_subbands_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_sst_offload_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_sst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
+ FPGA_sst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
+ FPGA_sst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_sst_offload_weighted_subbands_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_weighted_subbands_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_weighted_subbands_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_sst_offload_weighted_subbands_R"], datatype=numpy.bool_, dims=(16,))
# number of packets with valid payloads
nof_valid_payloads_R = attribute_wrapper(comms_id=StatisticsClient, comms_annotation={"type": "statistics", "parameter": "nof_valid_payloads"}, dims=(SSTCollector.MAX_FPGAS,), datatype=numpy.uint64)
diff --git a/devices/devices/sdp/xst.py b/devices/devices/sdp/xst.py
index c9883303b80425f0c142181994d43e477ec5431c..1740563c916115373d435896c075815a477795ea 100644
--- a/devices/devices/sdp/xst.py
+++ b/devices/devices/sdp/xst.py
@@ -101,20 +101,20 @@ class XST(Statistics):
# ----------
# FPGA control points for XSTs
- FPGA_xst_integration_interval_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_RW"], datatype=numpy.double, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_integration_interval_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_R"], datatype=numpy.double, dims=(16,))
- FPGA_xst_offload_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_offload_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
- FPGA_xst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
- FPGA_xst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
- FPGA_xst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
- FPGA_xst_processing_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- FPGA_xst_processing_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
- FPGA_xst_subband_select_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_subband_select_RW"], datatype=numpy.uint32, dims=(8,16), access=AttrWriteType.READ_WRITE)
- FPGA_xst_subband_select_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_subband_select_R"], datatype=numpy.uint32, dims=(8,16))
+ FPGA_xst_integration_interval_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_integration_interval_RW"], datatype=numpy.double, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_integration_interval_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_integration_interval_R"], datatype=numpy.double, dims=(16,))
+ FPGA_xst_offload_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_offload_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_xst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_eth_destination_mac_R"], datatype=numpy.str, dims=(16,))
+ FPGA_xst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_ip_destination_address_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_ip_destination_address_R"], datatype=numpy.str, dims=(16,))
+ FPGA_xst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_xst_processing_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_processing_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_xst_subband_select_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_subband_select_RW"], datatype=numpy.uint32, dims=(8,16), access=AttrWriteType.READ_WRITE)
+ FPGA_xst_subband_select_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["FPGA_xst_subband_select_R"], datatype=numpy.uint32, dims=(8,16))
# number of packets with valid payloads
nof_valid_payloads_R = attribute_wrapper(comms_id=StatisticsClient, comms_annotation={"type": "statistics", "parameter": "nof_valid_payloads"}, dims=(XSTCollector.MAX_FPGAS,), datatype=numpy.uint64)
diff --git a/devices/devices/unb2.py b/devices/devices/unb2.py
index bad1b1a324c9c838960d07cdfeb804b2789bbac6..0feb3e53d90e84a708aeaed9a511b86975801cfa 100644
--- a/devices/devices/unb2.py
+++ b/devices/devices/unb2.py
@@ -64,42 +64,44 @@ class UNB2(opcua_device):
'UNB2_mask_RW'
]
+ UNB2TR_I2C_bus_DDR4_error_R = attribute_wrapper(comms_annotation=["UNB2TR_I2C_bus_DDR4_error_R"],datatype=numpy.int64 , dims=(4,2))
+ UNB2TR_I2C_bus_error_R = attribute_wrapper(comms_annotation=["UNB2TR_I2C_bus_error_R" ],datatype=numpy.int64 , dims=(2,))
+ UNB2TR_I2C_bus_FPGA_PS_error_R = attribute_wrapper(comms_annotation=["UNB2TR_I2C_bus_FPGA_PS_error_R"],datatype=numpy.int64 , dims=(4,2))
+ UNB2TR_I2C_bus_PS_error_R = attribute_wrapper(comms_annotation=["UNB2TR_I2C_bus_PS_error_R" ],datatype=numpy.int64 , dims=(2,))
+ UNB2TR_I2C_bus_QSFP_error_R = attribute_wrapper(comms_annotation=["UNB2TR_I2C_bus_QSFP_error_R"],datatype=numpy.int64 , dims=(24,2))
+ UNB2TR_monitor_rate_RW = attribute_wrapper(comms_annotation=["UNB2TR_monitor_rate_RW" ],datatype=numpy.int64 , access=AttrWriteType.READ_WRITE)
UNB2TR_translator_busy_R = attribute_wrapper(comms_annotation=["UNB2TR_translator_busy_R" ],datatype=numpy.bool_ )
UNB2_DC_DC_48V_12V_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_DC_DC_48V_12V_IOUT_R" ],datatype=numpy.float64, dims=(2,))
UNB2_DC_DC_48V_12V_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_DC_DC_48V_12V_TEMP_R" ],datatype=numpy.float64, dims=(2,))
UNB2_DC_DC_48V_12V_VIN_R = attribute_wrapper(comms_annotation=["UNB2_DC_DC_48V_12V_VIN_R" ],datatype=numpy.float64, dims=(2,))
UNB2_DC_DC_48V_12V_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_DC_DC_48V_12V_VOUT_R" ],datatype=numpy.float64, dims=(2,))
- UNB2_EEPROM_Serial_Number_R = attribute_wrapper(comms_annotation=["UNB2_EEPROM_Serial_Number_R"],datatype=numpy.str , dims=(2,))
- UNB2_EEPROM_Unique_ID_R = attribute_wrapper(comms_annotation=["UNB2_EEPROM_Unique_ID_R" ],datatype=numpy.int64 , dims=(2,))
- UNB2_FPGA_DDR4_SLOT_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_DDR4_SLOT_TEMP_R"],datatype=numpy.float64, dims=(16,))
- UNB2_FPGA_POL_CORE_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_IOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_CORE_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_TEMP_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_VOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_ERAM_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_IOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_ERAM_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_TEMP_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_ERAM_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_VOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_HGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_IOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_HGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_TEMP_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_HGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_VOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_PGM_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_IOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_PGM_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_TEMP_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_PGM_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_VOUT_R" ],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_RXGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_IOUT_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_RXGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_TEMP_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_RXGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_VOUT_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_TXGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_IOUT_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_TEMP_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_POL_TXGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_VOUT_R"],datatype=numpy.float64, dims=(8,))
- UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_QSFP_CAGE_LOS_R" ],datatype=numpy.int64 , dims=(48,))
- UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_QSFP_CAGE_TEMP_R"],datatype=numpy.float64, dims=(48,))
- UNB2_Front_Panel_LED_R = attribute_wrapper(comms_annotation=["UNB2_Front_Panel_LED_R" ],datatype=numpy.int64 , dims=(2,))
- UNB2_Front_Panel_LED_RW = attribute_wrapper(comms_annotation=["UNB2_Front_Panel_LED_RW" ],datatype=numpy.int64 , dims=(2,), access=AttrWriteType.READ_WRITE)
- UNB2_I2C_bus_DDR4_error_R = attribute_wrapper(comms_annotation=["UNB2_I2C_bus_DDR4_error_R" ],datatype=numpy.int64 , dims=(8,))
- UNB2_I2C_bus_error_R = attribute_wrapper(comms_annotation=["UNB2_I2C_bus_error_R" ],datatype=numpy.int64 , dims=(2,))
- UNB2_I2C_bus_FPGA_PS_error_R = attribute_wrapper(comms_annotation=["UNB2_I2C_bus_FPGA_PS_error_R"],datatype=numpy.int64 , dims=(8,))
- UNB2_I2C_bus_PS_error_R = attribute_wrapper(comms_annotation=["UNB2_I2C_bus_PS_error_R" ],datatype=numpy.int64 , dims=(2,))
- UNB2_I2C_bus_QSFP_error_R = attribute_wrapper(comms_annotation=["UNB2_I2C_bus_QSFP_error_R" ],datatype=numpy.int64 , dims=(48,))
+ UNB2_FPGA_DDR4_SLOT_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_DDR4_SLOT_TEMP_R"],datatype=numpy.float64, dims=(8,2))
+ UNB2_FPGA_POL_CORE_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_IOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_CORE_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_TEMP_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_CORE_VOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_ERAM_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_IOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_ERAM_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_TEMP_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_ERAM_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_ERAM_VOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_HGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_IOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_HGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_TEMP_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_HGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_HGXB_VOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_PGM_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_IOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_PGM_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_TEMP_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_PGM_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_PGM_VOUT_R" ],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_RXGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_IOUT_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_RXGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_TEMP_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_RXGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_RXGXB_VOUT_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_TXGXB_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_IOUT_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_TEMP_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_POL_TXGXB_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_POL_TXGXB_VOUT_R"],datatype=numpy.float64, dims=(4,2))
+ UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_QSFP_CAGE_LOS_R" ],datatype=numpy.int64 , dims=(24,2))
+ UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_FPGA_QSFP_CAGE_TEMP_R"],datatype=numpy.float64, dims=(24,2))
+ UNB2_Front_Panel_LED_colour_R = attribute_wrapper(comms_annotation=["UNB2_Front_Panel_LED_colour_R"],datatype=numpy.int64 , dims=(2,))
+ UNB2_Front_Panel_LED_colour_RW = attribute_wrapper(comms_annotation=["UNB2_Front_Panel_LED_colour_RW"],datatype=numpy.int64 , dims=(2,), access=AttrWriteType.READ_WRITE)
UNB2_mask_RW = attribute_wrapper(comms_annotation=["UNB2_mask_RW" ],datatype=numpy.bool_ , dims=(2,), access=AttrWriteType.READ_WRITE)
+ UNB2_PCB_ID_R = attribute_wrapper(comms_annotation=["UNB2_PCB_ID_R" ],datatype=numpy.int64 , dims=(2,))
+ UNB2_PCB_number_R = attribute_wrapper(comms_annotation=["UNB2_PCB_number_R" ],datatype=numpy.str , dims=(2,))
+ UNB2_PCB_version_R = attribute_wrapper(comms_annotation=["UNB2_PCB_version_R" ],datatype=numpy.str , dims=(2,))
UNB2_POL_CLOCK_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_POL_CLOCK_IOUT_R" ],datatype=numpy.float64, dims=(2,))
UNB2_POL_CLOCK_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_POL_CLOCK_TEMP_R" ],datatype=numpy.float64, dims=(2,))
UNB2_POL_CLOCK_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_POL_CLOCK_VOUT_R" ],datatype=numpy.float64, dims=(2,))
@@ -115,8 +117,7 @@ class UNB2(opcua_device):
UNB2_POL_SWITCH_PHY_IOUT_R = attribute_wrapper(comms_annotation=["UNB2_POL_SWITCH_PHY_IOUT_R"],datatype=numpy.float64, dims=(2,))
UNB2_POL_SWITCH_PHY_TEMP_R = attribute_wrapper(comms_annotation=["UNB2_POL_SWITCH_PHY_TEMP_R"],datatype=numpy.float64, dims=(2,))
UNB2_POL_SWITCH_PHY_VOUT_R = attribute_wrapper(comms_annotation=["UNB2_POL_SWITCH_PHY_VOUT_R"],datatype=numpy.float64, dims=(2,))
- UNB2_PWR_off_R = attribute_wrapper(comms_annotation=["UNB2_PWR_off_R" ],datatype=numpy.bool_ , dims=(2,))
- UNB2_PWR_off_RW = attribute_wrapper(comms_annotation=["UNB2_PWR_off_RW" ],datatype=numpy.bool_ , dims=(2,), access=AttrWriteType.READ_WRITE)
+ UNB2_PWR_on_R = attribute_wrapper(comms_annotation=["UNB2_PWR_on_R" ],datatype=numpy.bool_ , dims=(2,))
# --------
# overloaded functions
diff --git a/docker-compose/grafana/Dockerfile b/docker-compose/grafana/Dockerfile
index bc766bcd3b0d71f346fd70e34fa27dd91fc27b04..e51cce5eeaa0310c1ecd698d8d797e3163ce4457 100644
--- a/docker-compose/grafana/Dockerfile
+++ b/docker-compose/grafana/Dockerfile
@@ -1,5 +1,9 @@
FROM grafana/grafana
+# Install some plugins
+RUN grafana-cli plugins install briangann-datatable-panel
+RUN grafana-cli plugins install ae3e-plotly-panel
+
COPY grafana.ini /etc/grafana/
# Add default configuration through provisioning (see https://grafana.com/docs/grafana/latest/administration/provisioning)
diff --git a/docker-compose/grafana/dashboards/home.json b/docker-compose/grafana/dashboards/home.json
index 6d4641a656c20b40ceaa8a18d2b02da47b0b55ba..f1b7a626e2ca470f513d22cadf240345cacf2f25 100644
--- a/docker-compose/grafana/dashboards/home.json
+++ b/docker-compose/grafana/dashboards/home.json
@@ -22,7 +22,7 @@
"fiscalYearStartMonth": 0,
"gnetId": null,
"graphTooltip": 0,
- "id": 6,
+ "id": 5,
"links": [],
"liveNow": false,
"panels": [
@@ -484,6 +484,196 @@
],
"type": "table"
},
+ {
+ "datasource": "ELK logs",
+ "description": "List of the errors in the selected timespan",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "thresholds"
+ },
+ "custom": {
+ "align": "auto",
+ "displayMode": "auto",
+ "filterable": true
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 80
+ }
+ ]
+ }
+ },
+ "overrides": [
+ {
+ "matcher": {
+ "id": "byName",
+ "options": "@timestamp"
+ },
+ "properties": [
+ {
+ "id": "custom.width",
+ "value": 149
+ }
+ ]
+ },
+ {
+ "matcher": {
+ "id": "byName",
+ "options": "level"
+ },
+ "properties": [
+ {
+ "id": "custom.width",
+ "value": 62
+ }
+ ]
+ },
+ {
+ "matcher": {
+ "id": "byName",
+ "options": "program"
+ },
+ "properties": [
+ {
+ "id": "custom.width",
+ "value": 287
+ }
+ ]
+ },
+ {
+ "matcher": {
+ "id": "byName",
+ "options": "extra.logger_name"
+ },
+ "properties": [
+ {
+ "id": "custom.width",
+ "value": 72
+ }
+ ]
+ },
+ {
+ "matcher": {
+ "id": "byName",
+ "options": "extra.lofar_id"
+ },
+ "properties": [
+ {
+ "id": "custom.width",
+ "value": 196
+ }
+ ]
+ }
+ ]
+ },
+ "gridPos": {
+ "h": 5,
+ "w": 24,
+ "x": 0,
+ "y": 10
+ },
+ "id": 56,
+ "options": {
+ "showHeader": true,
+ "sortBy": []
+ },
+ "pluginVersion": "8.2.1",
+ "targets": [
+ {
+ "alias": "",
+ "bucketAggs": [],
+ "metrics": [
+ {
+ "hide": false,
+ "id": "1",
+ "settings": {
+ "limit": "500"
+ },
+ "type": "logs"
+ }
+ ],
+ "query": "level:(ERROR or CRIT or FATAL)",
+ "refId": "A",
+ "timeField": "@timestamp"
+ }
+ ],
+ "title": "Error Log",
+ "transformations": [
+ {
+ "id": "organize",
+ "options": {
+ "excludeByName": {
+ "@version": true,
+ "_id": true,
+ "_index": true,
+ "_source": true,
+ "_type": true,
+ "extra.func_name": true,
+ "extra.interpreter": true,
+ "extra.interpreter_version": true,
+ "extra.line": true,
+ "extra.logger_name": true,
+ "extra.logstash_async_version": true,
+ "extra.path": true,
+ "extra.process_name": true,
+ "extra.software_version": true,
+ "extra.tango_device": true,
+ "extra.thread_name": true,
+ "highlight": true,
+ "host": true,
+ "logsource": true,
+ "pid": true,
+ "port": true,
+ "sort": true,
+ "tags": true,
+ "type": true
+ },
+ "indexByName": {
+ "@timestamp": 0,
+ "@version": 5,
+ "_id": 6,
+ "_index": 7,
+ "_source": 8,
+ "_type": 9,
+ "extra.func_name": 10,
+ "extra.interpreter": 11,
+ "extra.interpreter_version": 12,
+ "extra.line": 13,
+ "extra.lofar_id": 4,
+ "extra.logger_name": 14,
+ "extra.logstash_async_version": 15,
+ "extra.path": 16,
+ "extra.process_name": 17,
+ "extra.software_version": 18,
+ "extra.tango_device": 19,
+ "extra.thread_name": 20,
+ "highlight": 21,
+ "host": 2,
+ "level": 1,
+ "logsource": 22,
+ "message": 23,
+ "pid": 24,
+ "port": 25,
+ "program": 3,
+ "sort": 26,
+ "tags": 27,
+ "type": 28
+ },
+ "renameByName": {}
+ }
+ }
+ ],
+ "type": "table"
+ },
{
"collapsed": false,
"datasource": null,
@@ -491,7 +681,301 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 10
+ "y": 15
+ },
+ "id": 49,
+ "panels": [],
+ "title": "APSCT & APSPU",
+ "type": "row"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "State of APSCT",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "thresholds"
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 1
+ }
+ ]
+ }
+ },
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 3,
+ "w": 21,
+ "x": 0,
+ "y": 16
+ },
+ "id": 24,
+ "options": {
+ "colorMode": "background",
+ "graphMode": "none",
+ "justifyMode": "auto",
+ "orientation": "auto",
+ "reduceOptions": {
+ "calcs": [
+ "lastNotNull"
+ ],
+ "fields": "",
+ "values": false
+ },
+ "text": {},
+ "textMode": "name"
+ },
+ "pluginVersion": "8.2.1",
+ "targets": [
+ {
+ "exemplar": true,
+ "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PWR_on_R\"}",
+ "interval": "",
+ "legendFormat": "Power",
+ "refId": "A"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/apsct/1\",name=\"APSCTTR_I2C_error_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "I2C",
+ "refId": "B"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PLL_200MHz_error_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "PLL",
+ "refId": "C"
+ },
+ {
+ "exemplar": true,
+ "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PLL_200MHz_locked_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "PLL Lock",
+ "refId": "D"
+ },
+ {
+ "exemplar": true,
+ "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_INPUT_10MHz_good_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "10MHz",
+ "refId": "E"
+ },
+ {
+ "exemplar": true,
+ "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_INPUT_PPS_good_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "PPS",
+ "refId": "F"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PPS_ignore_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "PPS used",
+ "refId": "G"
+ }
+ ],
+ "title": "APS Clock State",
+ "type": "stat"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "State of APSPU",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "thresholds"
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 1
+ }
+ ]
+ }
+ },
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 3,
+ "w": 3,
+ "x": 21,
+ "y": 16
+ },
+ "id": 50,
+ "options": {
+ "colorMode": "background",
+ "graphMode": "none",
+ "justifyMode": "auto",
+ "orientation": "auto",
+ "reduceOptions": {
+ "calcs": [
+ "lastNotNull"
+ ],
+ "fields": "",
+ "values": false
+ },
+ "text": {},
+ "textMode": "name"
+ },
+ "pluginVersion": "8.2.1",
+ "targets": [
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/apspu/1\",name=\"APSPUTR_I2C_error_R\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "I2C",
+ "refId": "B"
+ }
+ ],
+ "title": "APS Power Unit State",
+ "type": "stat"
+ },
+ {
+ "collapsed": true,
+ "datasource": null,
+ "gridPos": {
+ "h": 1,
+ "w": 24,
+ "x": 0,
+ "y": 19
+ },
+ "id": 53,
+ "panels": [],
+ "title": "UNB2",
+ "type": "row"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "State of Unboard 2 I2C Bus",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "thresholds"
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "transparent",
+ "value": null
+ },
+ {
+ "color": "green",
+ "value": 1
+ },
+ {
+ "color": "red",
+ "value": 2
+ }
+ ]
+ }
+ },
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 3,
+ "w": 24,
+ "x": 0,
+ "y": 20
+ },
+ "id": 54,
+ "options": {
+ "colorMode": "background",
+ "graphMode": "none",
+ "justifyMode": "auto",
+ "orientation": "auto",
+ "reduceOptions": {
+ "calcs": [
+ "lastNotNull"
+ ],
+ "fields": "",
+ "values": false
+ },
+ "text": {},
+ "textMode": "name"
+ },
+ "pluginVersion": "8.2.1",
+ "targets": [
+ {
+ "exemplar": true,
+ "expr": "(1 + (device_attribute{device=\"lts/unb2/1\",name=\"UNB2TR_I2C_bus_error_R\"} != bool 0)) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "I2C {{x}}",
+ "refId": "A"
+ },
+ {
+ "exemplar": true,
+ "expr": "(1 + device_attribute{device=\"lts/unb2/1\",name=\"UNB2TR_I2C_bus_PS_error_R\"}) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "PS {{x}}",
+ "refId": "B"
+ },
+ {
+ "exemplar": true,
+ "expr": "(1 + sum by (x) (device_attribute{device=\"lts/unb2/1\",name=\"UNB2TR_I2C_bus_FPGA_PS_error_R\"})) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "FPGA PS {{x}}",
+ "refId": "C"
+ },
+ {
+ "exemplar": true,
+ "expr": "(1 + sum by (x) (device_attribute{device=\"lts/unb2/1\",name=\"UNB2TR_I2C_bus_DDR4_error_R\"})) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "DDR {{x}}",
+ "refId": "D"
+ },
+ {
+ "exemplar": true,
+ "expr": "(1 + sum by (x) (device_attribute{device=\"lts/unb2/1\",name=\"UNB2TR_I2C_bus_QSFP_error_R\"})) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "QSFP {{x}}",
+ "refId": "E"
+ }
+ ],
+ "title": "UNB2 I2C State",
+ "type": "stat"
+ },
+ {
+ "collapsed": false,
+ "datasource": null,
+ "gridPos": {
+ "h": 1,
+ "w": 24,
+ "x": 0,
+ "y": 23
},
"id": 17,
"panels": [],
@@ -530,12 +1014,12 @@
"h": 8,
"w": 6,
"x": 0,
- "y": 11
+ "y": 24
},
"id": 21,
"options": {
"colorMode": "background",
- "graphMode": "area",
+ "graphMode": "none",
"justifyMode": "auto",
"orientation": "auto",
"reduceOptions": {
@@ -552,13 +1036,14 @@
"targets": [
{
"exemplar": true,
- "expr": "sum by (x)(1 + (device_attribute{device=\"lts/recv/1\",name=\"RCU_ADC_lock_R\"} == bool 129)) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"} - 3",
+ "expr": "sum by (x)(1 + (device_attribute{device=\"lts/recv/1\",name=\"RCU_ADC_locked_R\"})) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"} - 3",
+ "instant": false,
"interval": "",
"legendFormat": "{{y}}",
"refId": "A"
}
],
- "title": "RCU ADC lock",
+ "title": "RCU Clock Lock",
"type": "stat"
},
{
@@ -593,12 +1078,12 @@
"h": 8,
"w": 6,
"x": 6,
- "y": 11
+ "y": 24
},
"id": 25,
"options": {
"colorMode": "background",
- "graphMode": "area",
+ "graphMode": "none",
"justifyMode": "auto",
"orientation": "auto",
"reduceOptions": {
@@ -615,17 +1100,20 @@
"targets": [
{
"exemplar": true,
- "expr": "(2 - device_attribute{device=\"lts/recv/1\",name=\"RCU_I2C_STATUS_R\"}) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "expr": "(1 + (device_attribute{device=\"lts/recv/1\",name=\"RECVTR_I2C_error_R\"} == bool 0)) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
+ "hide": false,
+ "instant": false,
"interval": "",
"legendFormat": "{{y}}",
"refId": "A"
}
],
- "title": "RCU I2C status",
+ "title": "RCU I2C State",
"type": "stat"
},
{
"datasource": "Prometheus",
+ "description": "",
"fieldConfig": {
"defaults": {
"color": {
@@ -636,12 +1124,16 @@
"mode": "absolute",
"steps": [
{
- "color": "green",
+ "color": "transparent",
"value": null
},
{
"color": "red",
"value": 1
+ },
+ {
+ "color": "green",
+ "value": 2
}
]
}
@@ -649,12 +1141,12 @@
"overrides": []
},
"gridPos": {
- "h": 5,
- "w": 3,
+ "h": 8,
+ "w": 6,
"x": 12,
- "y": 11
+ "y": 24
},
- "id": 24,
+ "id": 51,
"options": {
"colorMode": "background",
"graphMode": "none",
@@ -674,37 +1166,15 @@
"targets": [
{
"exemplar": true,
- "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PWR_on_R\"}",
- "interval": "",
- "legendFormat": "Power",
- "refId": "A"
- },
- {
- "exemplar": true,
- "expr": "device_attribute{device=\"lts/apsct/1\",name=\"APSCT_I2C_error_R\"}",
- "hide": false,
- "interval": "",
- "legendFormat": "I2C",
- "refId": "B"
- },
- {
- "exemplar": true,
- "expr": "device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PLL_200MHz_error_R\"}",
- "hide": false,
- "interval": "",
- "legendFormat": "PLL",
- "refId": "C"
- },
- {
- "exemplar": true,
- "expr": "1-device_attribute{device=\"lts/apsct/1\",name=\"APSCT_PLL_200MHz_locked_R\"}",
+ "expr": "(1 + device_attribute{device=\"lts/recv/1\",name=\"RCU_PWR_good_R\"}) * on(x) device_attribute{device=\"lts/recv/1\",name=\"RCU_mask_RW\"}",
"hide": false,
+ "instant": false,
"interval": "",
- "legendFormat": "PLL Lock",
- "refId": "D"
+ "legendFormat": "{{y}}",
+ "refId": "A"
}
],
- "title": "Clock",
+ "title": "RCU Power good",
"type": "stat"
},
{
@@ -714,7 +1184,7 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 19
+ "y": 32
},
"id": 19,
"panels": [],
@@ -754,7 +1224,7 @@
"h": 8,
"w": 5,
"x": 0,
- "y": 20
+ "y": 33
},
"id": 11,
"options": {
@@ -822,7 +1292,7 @@
"h": 8,
"w": 5,
"x": 5,
- "y": 20
+ "y": 33
},
"id": 9,
"options": {
@@ -896,7 +1366,7 @@
"h": 4,
"w": 3,
"x": 10,
- "y": 20
+ "y": 33
},
"id": 12,
"options": {
@@ -938,7 +1408,7 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 28
+ "y": 41
},
"id": 27,
"panels": [],
@@ -978,7 +1448,7 @@
"h": 8,
"w": 5,
"x": 0,
- "y": 29
+ "y": 42
},
"id": 28,
"options": {
@@ -1076,7 +1546,7 @@
"h": 8,
"w": 5,
"x": 5,
- "y": 29
+ "y": 42
},
"id": 29,
"options": {
@@ -1185,7 +1655,7 @@
"h": 8,
"w": 5,
"x": 10,
- "y": 29
+ "y": 42
},
"id": 30,
"options": {
@@ -1278,7 +1748,7 @@
"h": 8,
"w": 5,
"x": 15,
- "y": 29
+ "y": 42
},
"id": 33,
"options": {
@@ -1373,7 +1843,7 @@
"h": 8,
"w": 3,
"x": 20,
- "y": 29
+ "y": 42
},
"id": 34,
"options": {
@@ -1410,7 +1880,7 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 37
+ "y": 50
},
"id": 36,
"panels": [],
@@ -1447,10 +1917,10 @@
"overrides": []
},
"gridPos": {
- "h": 8,
+ "h": 4,
"w": 5,
"x": 0,
- "y": 38
+ "y": 51
},
"id": 37,
"options": {
@@ -1548,7 +2018,7 @@
"h": 8,
"w": 5,
"x": 5,
- "y": 38
+ "y": 51
},
"id": 38,
"options": {
@@ -1657,7 +2127,7 @@
"h": 8,
"w": 5,
"x": 10,
- "y": 38
+ "y": 51
},
"id": 39,
"options": {
@@ -1750,7 +2220,7 @@
"h": 8,
"w": 5,
"x": 15,
- "y": 38
+ "y": 51
},
"id": 40,
"options": {
@@ -1845,7 +2315,7 @@
"h": 8,
"w": 3,
"x": 20,
- "y": 38
+ "y": 51
},
"id": 41,
"options": {
@@ -1905,10 +2375,10 @@
"overrides": []
},
"gridPos": {
- "h": 8,
+ "h": 4,
"w": 5,
"x": 0,
- "y": 46
+ "y": 55
},
"id": 45,
"options": {
@@ -1959,5 +2429,5 @@
"timezone": "",
"title": "Home",
"uid": "nC8N_kO7k",
- "version": 5
+ "version": 6
}
diff --git a/docker-compose/grafana/dashboards/sensors.json b/docker-compose/grafana/dashboards/sensors.json
index 95e39f60d024ea355119a24d72cbd9bdd9c178fe..43c85da09acc89c8ef487d60e8f46a5bd8605d3c 100644
--- a/docker-compose/grafana/dashboards/sensors.json
+++ b/docker-compose/grafana/dashboards/sensors.json
@@ -22,7 +22,6 @@
"fiscalYearStartMonth": 0,
"gnetId": null,
"graphTooltip": 0,
- "id": 4,
"links": [],
"liveNow": false,
"panels": [
@@ -75,7 +74,6 @@
}
},
"mappings": [],
- "min": 0,
"thresholds": {
"mode": "absolute",
"steps": [
@@ -99,7 +97,7 @@
"x": 0,
"y": 1
},
- "id": 2,
+ "id": 6,
"options": {
"legend": {
"calcs": [],
@@ -114,7 +112,7 @@
"targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/recv/1\",name=\"RCU_temperature_R\"} - 273.15",
+ "expr": "device_attribute{device=\"lts/sdp/1\",name=\"FPGA_temp_R\"} != 0",
"format": "time_series",
"hide": false,
"instant": false,
@@ -123,13 +121,13 @@
"refId": "A"
}
],
- "title": "RCU temperatures",
+ "title": "FPGA Temperatures",
"transformations": [],
"type": "timeseries"
},
{
"datasource": "Prometheus",
- "description": "Temperature sensors of each node on each board",
+ "description": "",
"fieldConfig": {
"defaults": {
"color": {
@@ -202,14 +200,14 @@
"targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_CORE_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_CORE_TEMP_R\"} ",
"interval": "",
"legendFormat": "Core board {{x}} node {{y}}",
"refId": "A"
},
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_ERAM_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_ERAM_TEMP_R\"} ",
"hide": false,
"interval": "",
"legendFormat": "ERAM board {{x}} node {{y}}",
@@ -217,7 +215,7 @@
},
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_RXGXB_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_RXGXB_TEMP_R\"} ",
"hide": false,
"interval": "",
"legendFormat": "TrRx board {{x}} node {{y}}",
@@ -225,7 +223,7 @@
},
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_TXGB_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_TXGB_TEMP_R\"} ",
"hide": false,
"interval": "",
"legendFormat": "TrHx board {{x}} node {{y}}",
@@ -233,23 +231,28 @@
},
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_PGM_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_PGM_TEMP_R\"} ",
"hide": false,
"interval": "",
"legendFormat": "IO board {{x}} node {{y}}",
"refId": "E"
},
{
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_POL_HGXB_TEMP_R\"} ",
"hide": false,
+ "interval": "",
+ "legendFormat": "HGXB board {{x}} node {{y}}",
"refId": "F"
}
],
- "title": "Uniboard2 Node Temperatures",
+ "title": "Uniboard2 FPGA POL Temperatures",
+ "transformations": [],
"type": "timeseries"
},
{
"datasource": "Prometheus",
- "description": "Temperature sensors of the power supply on each board",
+ "description": "",
"fieldConfig": {
"defaults": {
"color": {
@@ -308,7 +311,7 @@
"x": 10,
"y": 1
},
- "id": 8,
+ "id": 22,
"options": {
"legend": {
"calcs": [],
@@ -322,62 +325,287 @@
"targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_QSFP_N01_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_QSFP_CAGE_TEMP_R\"}",
"interval": "",
- "legendFormat": "QSFP N01 board {{x}} ",
+ "legendFormat": "FPGA QSFP Cage {{x}}, {{y}} ",
"refId": "A"
+ }
+ ],
+ "title": "Uniboard2 QSFP Cage Temperatures",
+ "type": "timeseries"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "palette-classic",
+ "seriesBy": "max"
+ },
+ "custom": {
+ "axisLabel": "",
+ "axisPlacement": "auto",
+ "barAlignment": 0,
+ "drawStyle": "line",
+ "fillOpacity": 0,
+ "gradientMode": "none",
+ "hideFrom": {
+ "legend": false,
+ "tooltip": false,
+ "viz": false
+ },
+ "lineInterpolation": "linear",
+ "lineWidth": 1,
+ "pointSize": 5,
+ "scaleDistribution": {
+ "type": "linear"
+ },
+ "showPoints": "never",
+ "spanNulls": false,
+ "stacking": {
+ "group": "A",
+ "mode": "none"
+ },
+ "thresholdsStyle": {
+ "mode": "line"
+ }
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 85
+ }
+ ]
+ },
+ "unit": "celsius"
},
- {
- "exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_QSFP_N23_TEMP_R\"}",
- "hide": false,
- "interval": "",
- "legendFormat": "QSFP N23 board {{x}}",
- "refId": "B"
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 8,
+ "w": 5,
+ "x": 15,
+ "y": 1
+ },
+ "id": 23,
+ "options": {
+ "legend": {
+ "calcs": [],
+ "displayMode": "hidden",
+ "placement": "bottom"
},
+ "tooltip": {
+ "mode": "single"
+ }
+ },
+ "targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_SWITCH_1V2_TEMP_R\"}",
- "hide": false,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_FPGA_DDR4_SLOT_TEMP_R\"}",
"interval": "",
- "legendFormat": "Switch 1v2 board {{x}}",
- "refId": "C"
+ "legendFormat": "FPGA QSFP Cage {{x}}, {{y}} ",
+ "refId": "A"
+ }
+ ],
+ "title": "Uniboard2 DDR4 Temperatures",
+ "type": "timeseries"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "palette-classic"
+ },
+ "custom": {
+ "axisLabel": "",
+ "axisPlacement": "auto",
+ "barAlignment": 0,
+ "drawStyle": "line",
+ "fillOpacity": 0,
+ "gradientMode": "none",
+ "hideFrom": {
+ "legend": false,
+ "tooltip": false,
+ "viz": false
+ },
+ "lineInterpolation": "linear",
+ "lineWidth": 1,
+ "pointSize": 5,
+ "scaleDistribution": {
+ "type": "linear"
+ },
+ "showPoints": "auto",
+ "spanNulls": false,
+ "stacking": {
+ "group": "A",
+ "mode": "none"
+ },
+ "thresholdsStyle": {
+ "mode": "off"
+ }
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 80
+ }
+ ]
+ },
+ "unit": "celsius"
},
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 8,
+ "w": 5,
+ "x": 0,
+ "y": 9
+ },
+ "id": 2,
+ "options": {
+ "legend": {
+ "calcs": [],
+ "displayMode": "hidden",
+ "placement": "bottom"
+ },
+ "tooltip": {
+ "mode": "single"
+ }
+ },
+ "pluginVersion": "8.1.2",
+ "targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_SWITCH_PHY_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/recv/1\",name=\"RCU_TEMP_R\"}",
+ "format": "time_series",
"hide": false,
+ "instant": false,
"interval": "",
- "legendFormat": "Switch PHY board {{x}}",
- "refId": "D"
+ "legendFormat": "{{x}}",
+ "refId": "A"
+ }
+ ],
+ "title": "RCU Temperatures",
+ "transformations": [],
+ "type": "timeseries"
+ },
+ {
+ "datasource": "Prometheus",
+ "description": "Temperatures reported by APSCT and APSPU",
+ "fieldConfig": {
+ "defaults": {
+ "color": {
+ "mode": "palette-classic",
+ "seriesBy": "max"
+ },
+ "custom": {
+ "axisLabel": "",
+ "axisPlacement": "auto",
+ "barAlignment": 0,
+ "drawStyle": "line",
+ "fillOpacity": 0,
+ "gradientMode": "none",
+ "hideFrom": {
+ "legend": false,
+ "tooltip": false,
+ "viz": false
+ },
+ "lineInterpolation": "linear",
+ "lineWidth": 1,
+ "pointSize": 5,
+ "scaleDistribution": {
+ "type": "linear"
+ },
+ "showPoints": "never",
+ "spanNulls": false,
+ "stacking": {
+ "group": "A",
+ "mode": "none"
+ },
+ "thresholdsStyle": {
+ "mode": "line"
+ }
+ },
+ "mappings": [],
+ "thresholds": {
+ "mode": "absolute",
+ "steps": [
+ {
+ "color": "green",
+ "value": null
+ },
+ {
+ "color": "red",
+ "value": 85
+ }
+ ]
+ },
+ "unit": "celsius"
+ },
+ "overrides": []
+ },
+ "gridPos": {
+ "h": 8,
+ "w": 5,
+ "x": 5,
+ "y": 9
+ },
+ "id": 24,
+ "options": {
+ "legend": {
+ "calcs": [],
+ "displayMode": "hidden",
+ "placement": "bottom"
},
+ "tooltip": {
+ "mode": "single"
+ }
+ },
+ "targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_CLOCK_TEMP_R\"}",
- "hide": false,
+ "expr": "device_attribute{device=\"lts/apsct/1\",name=~\"APSCT_TEMP_R\"}",
"interval": "",
- "legendFormat": "Clock PWR board {{x}}",
- "refId": "E"
+ "legendFormat": "{{name}}",
+ "refId": "A"
},
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_DC_DC_48V_12V_TEMP_R\"}",
+ "expr": "device_attribute{device=\"lts/apspu/1\",name=~\"APSPU_.*_TEMP_R\"}",
"hide": false,
"interval": "",
- "legendFormat": "DC-DC board {{x}}",
- "refId": "F"
+ "legendFormat": "{{name}}",
+ "refId": "B"
}
],
- "title": "Uniboard2 Power Supply Temperatures",
+ "title": "APS Temperatures",
"type": "timeseries"
},
{
"datasource": "Prometheus",
- "description": "",
+ "description": "Temperature sensors of the power supply on each board",
"fieldConfig": {
"defaults": {
"color": {
- "mode": "palette-classic"
+ "mode": "palette-classic",
+ "seriesBy": "max"
},
"custom": {
"axisLabel": "",
@@ -397,14 +625,14 @@
"scaleDistribution": {
"type": "linear"
},
- "showPoints": "auto",
+ "showPoints": "never",
"spanNulls": false,
"stacking": {
"group": "A",
"mode": "none"
},
"thresholdsStyle": {
- "mode": "off"
+ "mode": "line"
}
},
"mappings": [],
@@ -417,7 +645,7 @@
},
{
"color": "red",
- "value": 80
+ "value": 85
}
]
},
@@ -429,9 +657,9 @@
"h": 8,
"w": 5,
"x": 15,
- "y": 1
+ "y": 9
},
- "id": 6,
+ "id": 8,
"options": {
"legend": {
"calcs": [],
@@ -442,21 +670,56 @@
"mode": "single"
}
},
- "pluginVersion": "8.1.2",
"targets": [
{
"exemplar": true,
- "expr": "device_attribute{device=\"lts/sdp/1\",name=\"FPGA_temp_R\"}",
- "format": "time_series",
- "hide": false,
- "instant": false,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_QSFP_N01_TEMP_R\"} ",
"interval": "",
- "legendFormat": "{{x}}",
+ "legendFormat": "QSFP N01 board {{x}}",
"refId": "A"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_QSFP_N23_TEMP_R\"} ",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "QSFP N23 board {{x}}",
+ "refId": "B"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_SWITCH_1V2_TEMP_R\"} ",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "Switch 1v2 board {{x}}",
+ "refId": "C"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_SWITCH_PHY_TEMP_R\"} ",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "Switch PHY board {{x}}",
+ "refId": "D"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_POL_CLOCK_TEMP_R\"} ",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "Clock PWR board {{x}}",
+ "refId": "E"
+ },
+ {
+ "exemplar": true,
+ "expr": "device_attribute{device=\"lts/unb2/1\",name=\"UNB2_DC_DC_48V_12V_TEMP_R\"} ",
+ "hide": false,
+ "interval": "",
+ "legendFormat": "DC-DC board {{x}}",
+ "refId": "F"
}
],
- "title": "FPGA temperatures",
- "transformations": [],
+ "title": "Uniboard2 Power Supply Temperatures",
"type": "timeseries"
},
{
@@ -466,7 +729,7 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 9
+ "y": 17
},
"id": 18,
"panels": [],
@@ -534,7 +797,7 @@
"h": 8,
"w": 5,
"x": 0,
- "y": 10
+ "y": 18
},
"id": 21,
"options": {
@@ -619,7 +882,7 @@
"h": 8,
"w": 5,
"x": 5,
- "y": 10
+ "y": 18
},
"id": 10,
"options": {
@@ -736,7 +999,7 @@
"h": 8,
"w": 5,
"x": 10,
- "y": 10
+ "y": 18
},
"id": 12,
"options": {
@@ -808,7 +1071,7 @@
"h": 1,
"w": 24,
"x": 0,
- "y": 18
+ "y": 26
},
"id": 20,
"panels": [],
@@ -878,7 +1141,7 @@
"h": 8,
"w": 5,
"x": 0,
- "y": 19
+ "y": 27
},
"id": 14,
"options": {
@@ -923,5 +1186,5 @@
"timezone": "",
"title": "Sensors",
"uid": "KMRmQzd7z",
- "version": 3
+ "version": 1
}
diff --git a/docker-compose/tango-prometheus-exporter/ska-tango-grafana-exporter b/docker-compose/tango-prometheus-exporter/ska-tango-grafana-exporter
index 774d39a40ca19c9d979ad22565e57b4af3e9a831..dddb23ff587f6e9c837cdb77e7955e94272eca6f 160000
--- a/docker-compose/tango-prometheus-exporter/ska-tango-grafana-exporter
+++ b/docker-compose/tango-prometheus-exporter/ska-tango-grafana-exporter
@@ -1 +1 @@
-Subproject commit 774d39a40ca19c9d979ad22565e57b4af3e9a831
+Subproject commit dddb23ff587f6e9c837cdb77e7955e94272eca6f