From 35da0af03a90a77e58da9dfd9e4c9fe22417ea32 Mon Sep 17 00:00:00 2001
From: Jan David Mol <mol@astron.nl>
Date: Tue, 1 Jun 2021 09:39:44 +0200
Subject: [PATCH] L2SS-246: Capitalise CP/MP names of SDP points
---
devices/SDP.py | 78 +++++++++++++++++++++++++-------------------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/devices/SDP.py b/devices/SDP.py
index dce6068c2..4ccc928b2 100644
--- a/devices/SDP.py
+++ b/devices/SDP.py
@@ -68,45 +68,45 @@ class SDP(hardware_device):
version_R = attribute(dtype=str, access=AttrWriteType.READ, fget=lambda self: get_version())
- # SDP will switch from fpga_mask_RW to tr_fpga_mask_RW, offer both for now as its a critical flag
- tr_fpga_mask_RW = attribute_wrapper(comms_annotation=["2:tr_fpga_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_mask_RW = attribute_wrapper(comms_annotation=["2:fpga_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_scrap_R = attribute_wrapper(comms_annotation=["2:fpga_scrap_R"], datatype=numpy.int32, dims=(2048,))
- fpga_scrap_RW = attribute_wrapper(comms_annotation=["2:fpga_scrap_RW"], datatype=numpy.int32, dims=(2048,), access=AttrWriteType.READ_WRITE)
- fpga_status_R = attribute_wrapper(comms_annotation=["2:fpga_status_R"], datatype=numpy.bool_, dims=(16,))
- fpga_temp_R = attribute_wrapper(comms_annotation=["2:fpga_temp_R"], datatype=numpy.float_, dims=(16,))
- fpga_version_R = attribute_wrapper(comms_annotation=["2:fpga_version_R"], datatype=numpy.str_, dims=(16,))
- fpga_weights_R = attribute_wrapper(comms_annotation=["2:fpga_weights_R"], datatype=numpy.int16, dims=(16, 12 * 488 * 2))
- fpga_weights_RW = attribute_wrapper(comms_annotation=["2:fpga_weights_RW"], datatype=numpy.int16, dims=(16, 12 * 488 * 2), access=AttrWriteType.READ_WRITE)
- fpga_processing_enable_RW = attribute_wrapper(comms_annotation=["2:fpga_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_processing_enable_R = attribute_wrapper(comms_annotation=["2:fpga_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
- fpga_sst_offload_enable_RW = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sst_offload_enable_R = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
- fpga_sst_offload_selector_RW = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_selector_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sst_offload_selector_R = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_selector_R"], datatype=numpy.bool_, dims=(16,))
- fpga_sst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_eth_destination_mac_R"], datatype=numpy.str_, dims=(16,))
- fpga_sst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_ip_destination_address_RW"], datatype=numpy.str_, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_ip_destination_address_R"], datatype=numpy.str_, dims=(16,))
- fpga_sst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["2:fpga_sst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
- fpga_sdp_info_station_id_RW = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_station_id_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sdp_info_station_id_R = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_station_id_R"], datatype=numpy.uint16, dims=(16,))
- fpga_sdp_info_observation_id_RW = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_observation_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sdp_info_observation_id_R = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_observation_id_R"], datatype=numpy.uint32, dims=(16,))
- fpga_sdp_info_nyquist_sampling_zone_index_RW = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_nyquist_sampling_zone_index_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
- fpga_sdp_info_nyquist_sampling_zone_index_R = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_nyquist_sampling_zone_index_R"], datatype=numpy.uint16, dims=(16,))
- fpga_sdp_info_subband_calibrated_flag_R = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_subband_calibrated_flag_R"], datatype=numpy.uint16, dims=(16,))
- fpga_sdp_info_beamlet_scale_R = attribute_wrapper(comms_annotation=["2:fpga_sdp_info_beamlet_scale_R"], datatype=numpy.uint16, dims=(16,))
-
- tr_busy_R = attribute_wrapper(comms_annotation=["2:tr_busy_R"], datatype=numpy.bool_)
- tr_reload_RW = attribute_wrapper(comms_annotation=["2:tr_reload_RW"], datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
- tr_tod_R = attribute_wrapper(comms_annotation=["2:tr_tod_R"], datatype=numpy.uint64)
- tr_uptime_R = attribute_wrapper(comms_annotation=["2:tr_uptime_R"], datatype=numpy.uint64)
-
- fpga_firmware_version_R = attribute_wrapper(comms_annotation=["2:fpga_firmware_version_R"], datatype=numpy.str_, dims=(16,))
- fpga_hardware_version_R = attribute_wrapper(comms_annotation=["2:fpga_hardware_version_R"], datatype=numpy.str_, dims=(16,))
- tr_software_version_R = attribute_wrapper(comms_annotation=["2:tr_software_version_R"], datatype=numpy.str_)
+ # SDP will switch from FPGA_mask_RW to TR_FPGA_mask_RW, offer both for now as its a critical flag
+ TR_FPGA_mask_RW = attribute_wrapper(comms_annotation=["2:TR_FPGA_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_mask_RW = attribute_wrapper(comms_annotation=["2:FPGA_mask_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_scrap_R = attribute_wrapper(comms_annotation=["2:FPGA_scrap_R"], datatype=numpy.int32, dims=(2048,))
+ FPGA_scrap_RW = attribute_wrapper(comms_annotation=["2:FPGA_scrap_RW"], datatype=numpy.int32, dims=(2048,), access=AttrWriteType.READ_WRITE)
+ FPGA_status_R = attribute_wrapper(comms_annotation=["2:FPGA_status_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_temp_R = attribute_wrapper(comms_annotation=["2:FPGA_temp_R"], datatype=numpy.float_, dims=(16,))
+ FPGA_version_R = attribute_wrapper(comms_annotation=["2:FPGA_version_R"], datatype=numpy.sTR_, dims=(16,))
+ FPGA_weights_R = attribute_wrapper(comms_annotation=["2:FPGA_weights_R"], datatype=numpy.int16, dims=(16, 12 * 488 * 2))
+ FPGA_weights_RW = attribute_wrapper(comms_annotation=["2:FPGA_weights_RW"], datatype=numpy.int16, dims=(16, 12 * 488 * 2), access=AttrWriteType.READ_WRITE)
+ FPGA_processing_enable_RW = attribute_wrapper(comms_annotation=["2:FPGA_processing_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_processing_enable_R = attribute_wrapper(comms_annotation=["2:FPGA_processing_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_sst_offload_enable_RW = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_enable_R = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_sst_offload_selector_RW = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_selector_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_selector_R = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_selector_R"], datatype=numpy.bool_, dims=(16,))
+ FPGA_sst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.sTR_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_eth_destination_mac_R"], datatype=numpy.sTR_, dims=(16,))
+ FPGA_sst_offload_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_ip_destination_address_RW"], datatype=numpy.sTR_, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_ip_destination_address_R"], datatype=numpy.sTR_, dims=(16,))
+ FPGA_sst_offload_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sst_offload_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["2:FPGA_sst_offload_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_sdp_info_station_id_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_station_id_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_station_id_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_station_id_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_sdp_info_observation_id_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_observation_id_RW"], datatype=numpy.uint32, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_observation_id_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_observation_id_R"], datatype=numpy.uint32, dims=(16,))
+ FPGA_sdp_info_nyquist_sampling_zone_index_RW = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_nyquist_sampling_zone_index_RW"], datatype=numpy.uint16, dims=(16,), access=AttrWriteType.READ_WRITE)
+ FPGA_sdp_info_nyquist_sampling_zone_index_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_nyquist_sampling_zone_index_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_sdp_info_subband_calibrated_flag_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_subband_calibrated_flag_R"], datatype=numpy.uint16, dims=(16,))
+ FPGA_sdp_info_beamlet_scale_R = attribute_wrapper(comms_annotation=["2:FPGA_sdp_info_beamlet_scale_R"], datatype=numpy.uint16, dims=(16,))
+
+ TR_busy_R = attribute_wrapper(comms_annotation=["2:TR_busy_R"], datatype=numpy.bool_)
+ TR_reload_RW = attribute_wrapper(comms_annotation=["2:TR_reload_RW"], datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
+ TR_tod_R = attribute_wrapper(comms_annotation=["2:TR_tod_R"], datatype=numpy.uint64)
+ TR_uptime_R = attribute_wrapper(comms_annotation=["2:TR_uptime_R"], datatype=numpy.uint64)
+
+ FPGA_firmware_version_R = attribute_wrapper(comms_annotation=["2:FPGA_firmware_version_R"], datatype=numpy.sTR_, dims=(16,))
+ FPGA_hardware_version_R = attribute_wrapper(comms_annotation=["2:FPGA_hardware_version_R"], datatype=numpy.sTR_, dims=(16,))
+ TR_software_version_R = attribute_wrapper(comms_annotation=["2:TR_software_version_R"], datatype=numpy.sTR_)
def always_executed_hook(self):
"""Method always executed before any TANGO command is executed."""
--
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