diff --git a/CDB/stations/DTS_ConfigDb.json b/CDB/stations/DTS_ConfigDb.json
index f2c36a66f81a92713b2068e9026e8037ba841e17..1263040256ab94d74f87bdbbd9d593aa3cbda701 100644
--- a/CDB/stations/DTS_ConfigDb.json
+++ b/CDB/stations/DTS_ConfigDb.json
@@ -102,40 +102,40 @@
                                 "5.0"
                             ],
                             "FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1",
-                                "0c:c4:7a:c0:30:f1"
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc",
+                                "ec:0d:9a:bf:f2:dc"
                             ],
                             "FPGA_beamlet_output_hdr_ip_destination_address_RW_default": [
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250",
-                                "10.99.250.250"
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250",
+                                "192.168.1.250"
                             ]
                         }
                     }