From 13393cebcb6a1e69b3b534a34a364073299e0b53 Mon Sep 17 00:00:00 2001
From: stedif <stefano.difrischia@inaf.it>
Date: Thu, 13 Oct 2022 15:26:34 +0200
Subject: [PATCH] L2SS-1008: add beamlet source values
---
CDB/stations/CS001_ConfigDb.json | 54 +++++++++++++++++++
CDB/stations/simulators_ConfigDb.json | 54 +++++++++++++++++++
.../devices/sdp/beamlet.py | 3 ++
3 files changed, 111 insertions(+)
diff --git a/CDB/stations/CS001_ConfigDb.json b/CDB/stations/CS001_ConfigDb.json
index 12411a459..8036e8444 100644
--- a/CDB/stations/CS001_ConfigDb.json
+++ b/CDB/stations/CS001_ConfigDb.json
@@ -126,6 +126,60 @@
"OPC_Time_Out": [
"5.0"
],
+ "FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
+ "00:22:86:00:01:00",
+ "00:22:86:00:01:01",
+ "00:22:86:00:01:02",
+ "00:22:86:00:01:03",
+ "00:22:86:00:01:04",
+ "00:22:86:00:01:05",
+ "00:22:86:00:01:06",
+ "00:22:86:00:01:07",
+ "00:22:86:00:01:08",
+ "00:22:86:00:01:09",
+ "00:22:86:00:01:10",
+ "00:22:86:00:01:11",
+ "00:22:86:00:01:12",
+ "00:22:86:00:01:13",
+ "00:22:86:00:01:14",
+ "00:22:86:00:01:15"
+ ],
+ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
+ "10.175.1.0",
+ "10.175.1.1",
+ "10.175.1.2",
+ "10.175.1.3",
+ "10.175.1.4",
+ "10.175.1.5",
+ "10.175.1.6",
+ "10.175.1.7",
+ "10.175.1.8",
+ "10.175.1.9",
+ "10.175.1.10",
+ "10.175.1.11",
+ "10.175.1.12",
+ "10.175.1.13",
+ "10.175.1.14",
+ "10.175.1.15"
+ ],
+ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
+ "4346",
+ "4347",
+ "4348",
+ "4349",
+ "4350",
+ "4351",
+ "4352",
+ "4353",
+ "4354",
+ "4355",
+ "4356",
+ "4357",
+ "4358",
+ "4359",
+ "4360",
+ "4361"
+ ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"3c:ec:ef:86:2f:b7",
"3c:ec:ef:86:2f:b7",
diff --git a/CDB/stations/simulators_ConfigDb.json b/CDB/stations/simulators_ConfigDb.json
index 51ea37683..f67bac703 100644
--- a/CDB/stations/simulators_ConfigDb.json
+++ b/CDB/stations/simulators_ConfigDb.json
@@ -84,6 +84,60 @@
"OPC_Time_Out": [
"5.0"
],
+ "FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
+ "00:11:22:33:44:00",
+ "00:11:22:33:44:01",
+ "00:11:22:33:44:02",
+ "00:11:22:33:44:03",
+ "00:11:22:33:44:04",
+ "00:11:22:33:44:05",
+ "00:11:22:33:44:06",
+ "00:11:22:33:44:07",
+ "00:11:22:33:44:08",
+ "00:11:22:33:44:09",
+ "00:11:22:33:44:10",
+ "00:11:22:33:44:11",
+ "00:11:22:33:44:12",
+ "00:11:22:33:44:13",
+ "00:11:22:33:44:14",
+ "00:11:22:33:44:15"
+ ],
+ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
+ "10.0.0.0",
+ "10.0.0.1",
+ "10.0.0.2",
+ "10.0.0.3",
+ "10.0.0.4",
+ "10.0.0.5",
+ "10.0.0.6",
+ "10.0.0.7",
+ "10.0.0.8",
+ "10.0.0.9",
+ "10.0.0.10",
+ "10.0.0.11",
+ "10.0.0.12",
+ "10.0.0.13",
+ "10.0.0.14",
+ "10.0.0.15"
+ ],
+ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
+ "4346",
+ "4347",
+ "4348",
+ "4349",
+ "4350",
+ "4351",
+ "4352",
+ "4353",
+ "4354",
+ "4355",
+ "4356",
+ "4357",
+ "4358",
+ "4359",
+ "4360",
+ "4361"
+ ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
diff --git a/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py b/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
index 52ae56d16..e09ca0968 100644
--- a/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
+++ b/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
@@ -98,6 +98,9 @@ class Beamlet(opcua_device):
)
FIRST_DEFAULT_SETTINGS = [
+ 'FPGA_beamlet_output_hdr_eth_source_mac_RW',
+ 'FPGA_beamlet_output_hdr_ip_source_address_RW',
+ 'FPGA_beamlet_output_hdr_udp_source_port_RW',
'FPGA_beamlet_output_hdr_eth_destination_mac_RW',
'FPGA_beamlet_output_hdr_ip_destination_address_RW',
'FPGA_beamlet_output_hdr_udp_destination_port_RW',
--
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