diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index c6037d4ef4512c9aaa9eb3c07b70ef7b163eb9d6..27b2beee9a63dad5fd18c4cc104fec08716b2bbd 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -1652,7 +1652,7 @@ bool Periph_fpga::write_wg_enable(const char *data) {
     bool *_ptr = (bool *)data;
     bool retval = true;
     uint32_t *reg = new uint32_t[4];
-    uint64_t start_bsn;
+    uint64_t scheduled_bsn;
     bool wg_enable;
 
     string regname1;
@@ -1681,20 +1681,20 @@ bool Periph_fpga::write_wg_enable(const char *data) {
     // get bsn and add latency
     wg_enable = _ptr[0];
     if (wg_enable == true) {
-        regname1 = "mm/0/REG_BSN_SCHEDULER/0/start_bsn";
+        regname1 = "mm/0/REG_BSN_SCHEDULER/0/scheduled_bsn";
         retval = Read(regname1, reg);
-        start_bsn = (((uint64_t)reg[1] << 32) + reg[0]);
-        cout << "bsn=" << to_string(start_bsn) << endl;
-        start_bsn += C_BSN_LATENCY;
-        cout << "new bsn=" << to_string(start_bsn) << endl;
-        reg[0] = (uint32_t)(start_bsn & 0xffffffff);
-        reg[1] = (uint32_t)((start_bsn >> 32) & 0xffffffff);
+        scheduled_bsn = (((uint64_t)reg[1] << 32) + reg[0]);
+        cout << "bsn=" << to_string(scheduled_bsn) << endl;
+        scheduled_bsn += C_BSN_LATENCY;
+        cout << "new bsn=" << to_string(scheduled_bsn) << endl;
+        reg[0] = (uint32_t)(scheduled_bsn & 0xffffffff);
+        reg[1] = (uint32_t)((scheduled_bsn >> 32) & 0xffffffff);
     }
     // write sheduled bsn
     for (uint i=0; i< C_S_pn; i++) {
         wg_enable = _ptr[i];
         if (wg_enable == true) {
-            regname1 = "mm/0/REG_BSN_SCHEDULER/" + to_string(i) + "/start_bsn";
+            regname1 = "mm/0/REG_BSN_SCHEDULER/" + to_string(i) + "/scheduled_bsn";
             retval = Write(regname1, reg);
         }
     }