diff --git a/src/fpga_map.cpp b/src/fpga_map.cpp index aa0d2da346248c680e0d71cc07568dce5045ea9c..17df8cb9012a10586ee80f7ce4a086c68706ffab 100644 --- a/src/fpga_map.cpp +++ b/src/fpga_map.cpp @@ -291,6 +291,7 @@ FpgaMap::FpgaMap() pointMap->add_register("FPGA_pps_expected_cnt_RW", PPS_EXPECTED_CNT, nFpgas, 1, "RW", REG_FORMAT_UINT32); pointMap->add_register("FPGA_pps_present_R", PPS_PRESENT, nFpgas, 1, "RO", REG_FORMAT_BOOLEAN); pointMap->add_register("FPGA_pps_capture_cnt_R", PPS_CAPTURE_CNT, nFpgas, 1, "RO", REG_FORMAT_UINT32); + pointMap->add_register("FPGA_pps_error_cnt_R", PPS_ERROR_CNT, nFpgas, 1, "RO", REG_FORMAT_UINT32); pointMap->add_register("FPGA_monitor_pps_offset_time_R", MONITOR_PPS_OFFSET_TIME, nFpgas, 1, "RO", REG_FORMAT_DOUBLE); pointMap->add_register("FPGA_time_since_last_pps_R", TIME_SINCE_LAST_PPS, nFpgas, 1, "RO", REG_FORMAT_DOUBLE); diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp index 4bfc5ebc4135c58f148ee1151ab4fae481bf2bed..1adb4bc540d28589ebb0aec507b3df4ad90fdd49 100644 --- a/src/periph/fpga.cpp +++ b/src/periph/fpga.cpp @@ -117,6 +117,7 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint udpport, uint n_fil pps_expected_cnt(0), pps_present(false), pps_capture_cnt(0), + pps_error_cnt(0), xst_ring_rx_bsn{0}, xst_ring_rx_nof_packets{0}, xst_ring_rx_nof_valid{0}, @@ -248,6 +249,7 @@ bool Periph_fpga::clear_fw_values() pps_expected_cnt = 0; pps_present = false; pps_capture_cnt = 0; + pps_error_cnt = 0; xst_aligned_bsn = 0; xst_aligned_nof_packets = 0; xst_aligned_nof_valid = 0; @@ -401,6 +403,9 @@ bool Periph_fpga::read(char *data, const uint32_t cmd_id) case PPS_CAPTURE_CNT: retval = read_pps_capture_cnt(data, R_MEM); break; + case PPS_ERROR_CNT: + retval = read_pps_error_cnt(data); + break; case TIME_SINCE_LAST_PPS: retval = read_time_since_last_pps(data); break; @@ -3819,11 +3824,13 @@ bool Periph_fpga::read_pps_capture_cnt(char *data, int mode) retval = Read("mm/0/PIO_PPS/0/capture_cnt", &sdp_data); pps_capture_cnt = sdp_data; // check if capture count is as expected, and set pps_present - pps_present = false; - if (pps_capture_cnt == pps_expected_cnt) - { + if (pps_capture_cnt == pps_expected_cnt) { pps_present = true; } + else { + pps_present = false; + pps_error_cnt++; + } } uint32_t *_ptr = (uint32_t *)data; @@ -3831,6 +3838,14 @@ bool Periph_fpga::read_pps_capture_cnt(char *data, int mode) return retval; } +bool Periph_fpga::read_pps_error_cnt(char *data) +{ + bool retval = true; + uint32_t *_ptr = (uint32_t *)data; + *_ptr = pps_error_cnt; + return retval; +} + bool Periph_fpga::read_time_since_last_pps(char *data) { bool retval = true; diff --git a/src/periph/fpga.h b/src/periph/fpga.h index 4555c84ffef570da855e83cb447c9cd57a10acb6..1f71f9afaf6fdb92c6b904e237b7e701008ccc5a 100644 --- a/src/periph/fpga.h +++ b/src/periph/fpga.h @@ -57,8 +57,9 @@ #define PPS_PRESENT 100 #define PPS_EXPECTED_CNT 101 #define PPS_CAPTURE_CNT 102 -#define TIME_SINCE_LAST_PPS 103 -#define MONITOR_PPS_OFFSET_TIME 104 +#define PPS_ERROR_CNT 103 +#define TIME_SINCE_LAST_PPS 104 +#define MONITOR_PPS_OFFSET_TIME 105 #define PROCESSING_ENABLE 110 #define SIGNAL_INPUT_BSN 120 #define SIGNAL_INPUT_NOF_BLOCKS 121 @@ -271,6 +272,7 @@ private: uint32_t pps_expected_cnt; bool pps_present; uint32_t pps_capture_cnt; + uint32_t pps_error_cnt; int64_t xst_ring_rx_bsn[C_N_pn_max]; int32_t xst_ring_rx_nof_packets[C_N_pn_max]; int32_t xst_ring_rx_nof_valid[C_N_pn_max]; @@ -489,6 +491,7 @@ private: bool write_pps_expected_cnt(const char *data); bool read_pps_present(char *data, int mode); bool read_pps_capture_cnt(char *data, int mode); + bool read_pps_error_cnt(char *data); bool read_time_since_last_pps(char *data); bool read_monitor_pps_offset_time(char *data, int mode); bool write_wdi_override(char *data);