From affaa1575b5b80360c2a8dc48e38001dd2b2b278 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 29 Sep 2021 17:00:29 +0200
Subject: [PATCH] L2SDP-489, with review comments.

---
 src/constants.h     | 1 +
 src/periph/fpga.cpp | 8 ++++----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/constants.h b/src/constants.h
index c520fb4e..f86fe460 100644
--- a/src/constants.h
+++ b/src/constants.h
@@ -34,6 +34,7 @@
 #define C_S_pn 12
 #define C_W_adc 14
 #define C_F_adc 200E6
+#define C_T_adc (1 / C_F_adc)
 
 #define C_WG_MODE_OFF  0
 #define C_WG_MODE_CALC 1
diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index 27b2beee..1fc5a5da 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -1441,7 +1441,7 @@ bool Periph_fpga::write_xst_processing_enable(const char *data)
         if (retval == true) {
             start_bsn = (((uint64_t)reg[1] << 32) + reg[0]);
             cout << "bsn=" << to_string(start_bsn) << endl;
-            start_bsn = start_bsn + 2 * C_F_adc / C_N_fft;
+            start_bsn = start_bsn + (2 * C_F_adc) / C_N_fft;
             cout << "new bsn=" << to_string(start_bsn) << endl;
             reg[0] = (uint32_t)(start_bsn & 0xffffffff);
             reg[1] = (uint32_t)((start_bsn >> 32) & 0xffffffff);
@@ -1467,7 +1467,7 @@ bool Periph_fpga::read_xst_integration_interval(TermOutput& termout, int format)
     uint32_t data[20];
     memset((void *)data, 0, sizeof(data));
     retval = Read("mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/ctrl_interval_size", data);
-    double interval = (double)data[0] / C_F_adc;
+    double interval = (double)data[0] * C_T_adc;
 
     double *_ptr = (double *)termout.val;
     *_ptr = interval;
@@ -1507,7 +1507,7 @@ bool Periph_fpga::read_xst_input_sync_at_bsn(TermOutput& termout, int format, in
     bool retval = true;
     int64_t bsn = my_xst_input_bsn_at_sync;
     if (mode == R_UCP) {
-        uint32_t data[20];
+        uint32_t data[2];
         memset((void *)data, 0, sizeof(data));
         string regname;
         regname = "mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_input_bsn_at_sync";
@@ -1526,7 +1526,7 @@ bool Periph_fpga::read_xst_output_sync_bsn(TermOutput& termout, int format, int
     bool retval = true;
     int64_t bsn = my_xst_output_sync_bsn;
     if (mode == R_UCP) {
-        uint32_t data[20];
+        uint32_t data[2];
         memset((void *)data, 0, sizeof(data));
         string regname;
         regname = "mm/0/REG_BSN_SYNC_SCHEDULER_XSUB/0/mon_output_sync_bsn";
-- 
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