diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index 86532cfefae814283195835f2c478310172a1037..b85754efda51b3a80f3d04c43b48d07639cfde1c 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -72,10 +72,12 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets):
current_fw_version("-.-"),
signal_input_sync_timeout(false),
signal_input_bsn(0),
- xst_input_bsn_at_sync(0),
- xst_output_sync_bsn(0),
signal_input_nof_packets(0),
signal_input_nof_samples(0),
+ signal_input_mean {0.0},
+ signal_input_rms {0.0},
+ xst_input_bsn_at_sync(0),
+ xst_output_sync_bsn(0),
sst_offload_nof_packets(0),
sst_offload_nof_valid(0),
bst_offload_nof_packets {0},
@@ -88,8 +90,6 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets):
jesd_csr_dev_syncn {0},
jesd_rx_err0 {0},
jesd_rx_err1 {0},
- signal_input_mean {0.0},
- signal_input_rms {0.0},
pps_offset_cnt(0),
pps_expected_cnt(0),
pps_present(false),
@@ -138,10 +138,10 @@ bool Periph_fpga::clear_fw_values()
current_fw_version = "-.-";
signal_input_sync_timeout = false;
signal_input_bsn = 0;
- xst_input_bsn_at_sync = 0;
- xst_output_sync_bsn = 0;
signal_input_nof_packets = 0;
signal_input_nof_samples = 0;
+ xst_input_bsn_at_sync = 0;
+ xst_output_sync_bsn = 0;
sst_offload_nof_packets = 0;
sst_offload_nof_valid = 0;
xst_offload_nof_packets = 0;
@@ -197,16 +197,16 @@ bool Periph_fpga::read(char *data, const string addr, const string type, const i
if (addr == "fpga/time_since_last_pps") { retval = read_time_since_last_pps(data, format, R_MEM); }
else if (addr == "fpga/pps_capture_cnt") { retval = read_pps_capture_cnt(data, format, R_MEM); }
else if (addr == "fpga/signal_input_bsn") { retval = read_signal_input_bsn(data, format, R_MEM); }
- else if (addr == "fpga/xst_input_sync_at_bsn") { retval = read_xst_input_sync_at_bsn(data, format, R_MEM); }
- else if (addr == "fpga/xst_output_sync_bsn") { retval = read_xst_output_sync_bsn(data, format, R_MEM); }
else if (addr == "fpga/signal_input_nof_packets") { retval = read_signal_input_nof_packets(data, format, R_MEM); }
else if (addr == "fpga/signal_input_nof_samples") { retval = read_signal_input_nof_samples(data, format, R_MEM); }
+ else if (addr == "fpga/signal_input_mean") { retval = read_signal_input_mean(data, format, R_MEM); }
+ else if (addr == "fpga/signal_input_rms") { retval = read_signal_input_rms(data, format, R_MEM); }
+ else if (addr == "fpga/xst_input_sync_at_bsn") { retval = read_xst_input_sync_at_bsn(data, format, R_MEM); }
+ else if (addr == "fpga/xst_output_sync_bsn") { retval = read_xst_output_sync_bsn(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_csr_dev_syncn") { retval = read_jesd204b_csr_dev_syncn(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_csr_rbd_count") { retval = read_jesd204b_csr_rbd_count(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_rx_err0") { retval = read_jesd204b_rx_err0(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_rx_err1") { retval = read_jesd204b_rx_err1(data, format, R_MEM); }
- else if (addr == "fpga/signal_input_mean") { retval = read_signal_input_mean(data, format, R_MEM); }
- else if (addr == "fpga/signal_input_rms") { retval = read_signal_input_rms(data, format, R_MEM); }
else if (addr == "fpga/sst_offload_nof_packets") { retval = read_sst_offload_nof_packets(data, format, R_MEM); }
else if (addr == "fpga/sst_offload_nof_valid") { retval = read_sst_offload_nof_valid(data, format, R_MEM); }
else if (addr == "fpga/bst_offload_nof_packets") { retval = read_bst_offload_nof_packets(data, format, R_MEM); }
@@ -400,16 +400,16 @@ bool Periph_fpga::monitor(char *data)
read_pps_capture_cnt(data, REG_FORMAT_UINT32, R_UCP);
read_signal_input_sync_timeout(data, REG_FORMAT_INT64, R_UCP);
read_signal_input_bsn(data, REG_FORMAT_INT64, R_UCP);
- read_xst_input_sync_at_bsn(data, REG_FORMAT_INT64, R_UCP);
- read_xst_output_sync_bsn(data, REG_FORMAT_INT64, R_UCP);
read_signal_input_nof_packets(data, REG_FORMAT_INT32, R_UCP);
read_signal_input_nof_samples(data, REG_FORMAT_INT32, R_UCP);
+ read_signal_input_mean(data, REG_FORMAT_DOUBLE, R_UCP);
+ read_signal_input_rms(data, REG_FORMAT_DOUBLE, R_UCP);
+ read_xst_input_sync_at_bsn(data, REG_FORMAT_INT64, R_UCP);
+ read_xst_output_sync_bsn(data, REG_FORMAT_INT64, R_UCP);
read_jesd204b_csr_rbd_count(data, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_csr_dev_syncn(data, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_rx_err0(data, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_rx_err1(data, REG_FORMAT_UINT32, R_UCP);
- read_signal_input_mean(data, REG_FORMAT_DOUBLE, R_UCP);
- read_signal_input_rms(data, REG_FORMAT_DOUBLE, R_UCP);
read_sst_offload_nof_packets(data, REG_FORMAT_INT32, R_UCP);
read_sst_offload_nof_valid(data, REG_FORMAT_INT32, R_UCP);
read_bst_offload_nof_packets(data, REG_FORMAT_INT32, R_UCP);
@@ -1935,6 +1935,29 @@ bool Periph_fpga::write_wg_frequency(const char *data) {
return retval;
}
+bool Periph_fpga::write_signal_input_samples_delay(const char *data) {
+ uint32_t *_ptr = (uint32_t *)data;
+ bool retval = true;
+ uint32_t sdp_data;
+ uint32_t min_sample_delay = 0;
+ uint32_t max_sample_delay = 4095;
+ uint32_t sample_delay;
+ string regname;
+ for (uint i=0; i< C_S_pn; i++) {
+ sample_delay = *_ptr;
+ if ((sample_delay < min_sample_delay) || (sample_delay > max_sample_delay)) {
+ LOG_F(ERROR, "signal_input_sample_delay not in range<%d:%d>", min_sample_delay, max_sample_delay);
+ retval = false;
+ } else {
+ regname = "mm/0/REG_DP_SHIFTRAM/" + to_string(i) + "/shift";
+ sdp_data = sample_delay;
+ retval = Write(regname, &sdp_data);
+ _ptr++;
+ }
+ }
+ return retval;
+}
+
bool Periph_fpga::read_signal_input_sync_timeout(char *data, int format, int mode) {
bool retval = true;
uint32_t sdp_data;
@@ -2007,172 +2030,149 @@ bool Periph_fpga::read_signal_input_nof_samples(char *data, int format, int mode
return retval;
}
-bool Periph_fpga::read_jesd204b_csr_rbd_count(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_mean(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
- uint32_t sdp_data;
+ uint32_t sdp_data[2];
+ memset(sdp_data, 0, sizeof(sdp_data));
string regname;
+ int64_t mean_sum;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/JESD204B/" + to_string(i) + "/csr_rbd_count";
- retval = Read(regname, &sdp_data);
- jesd_csr_rbd_count[i] = (uint32_t)sdp_data;
+ regname = "mm/0/REG_ADUH_MONITOR/" + to_string(i) + "/mean_sum";
+ retval = Read(regname, sdp_data);
+ mean_sum = (int64_t)(((int64_t)sdp_data[1] << 32) + sdp_data[0]);
+ signal_input_mean[i] = (double)mean_sum / C_N_CLK_PER_PPS;
}
}
- uint32_t *_ptr = (uint32_t *)data;
+ double *_ptr = (double *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = jesd_csr_rbd_count[i];
+ *_ptr = signal_input_mean[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::read_jesd204b_csr_dev_syncn(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_rms(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
- uint32_t sdp_data;
+ uint32_t sdp_data[2];
+ memset(sdp_data, 0, sizeof(sdp_data));
string regname;
+ int64_t power_sum;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/JESD204B/" + to_string(i) + "/csr_dev_syncn";
- retval = Read(regname, &sdp_data);
- jesd_csr_dev_syncn[i] = (uint32_t)sdp_data;
+ regname = "mm/0/REG_ADUH_MONITOR/" + to_string(i) + "/power_sum";
+ retval = Read(regname, sdp_data);
+ power_sum = (int64_t)(((int64_t)sdp_data[1] << 32) + sdp_data[0]);
+ signal_input_rms[i] = sqrt((double)power_sum / C_N_CLK_PER_PPS);
}
}
- uint32_t *_ptr = (uint32_t *)data;
+ double *_ptr = (double *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = jesd_csr_dev_syncn[i];
+ *_ptr = signal_input_rms[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::read_jesd204b_rx_err0(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_data_buffer(char *data, int format) {
+ bool retval = true;
+ uint32_t sdp_data[C_V_si_db];
+ string regname;
+ int16_t *_ptr = (int16_t *)data;
+ for (uint i=0; i< C_S_pn; i++) {
+ memset(sdp_data, 0, sizeof(sdp_data));
+ regname = "mm/0/RAM_DIAG_DATA_BUFFER_BSN/" + to_string(i) + "/data";
+ retval &= Read(regname, sdp_data);
+ for (uint j=0; j< C_V_si_db; j++) {
+ *_ptr = (int16_t)((sdp_data[j] & 0x3FFF) << 2) / 4;
+ _ptr++;
+ }
+ }
+ return retval;
+}
+
+bool Periph_fpga::read_jesd204b_csr_rbd_count(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
uint32_t sdp_data;
string regname;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/JESD204B/" + to_string(i) + "/rx_err0";
+ regname = "mm/0/JESD204B/" + to_string(i) + "/csr_rbd_count";
retval = Read(regname, &sdp_data);
- jesd_rx_err0[i] = (uint32_t)sdp_data;
+ jesd_csr_rbd_count[i] = (uint32_t)sdp_data;
}
}
uint32_t *_ptr = (uint32_t *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = jesd_rx_err0[i];
+ *_ptr = jesd_csr_rbd_count[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::read_jesd204b_rx_err1(char *data, int format, int mode) {
+bool Periph_fpga::read_jesd204b_csr_dev_syncn(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
uint32_t sdp_data;
string regname;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/JESD204B/" + to_string(i) + "/rx_err1";
+ regname = "mm/0/JESD204B/" + to_string(i) + "/csr_dev_syncn";
retval = Read(regname, &sdp_data);
- jesd_rx_err1[i] = (uint32_t)sdp_data;
+ jesd_csr_dev_syncn[i] = (uint32_t)sdp_data;
}
}
uint32_t *_ptr = (uint32_t *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = jesd_rx_err1[i];
+ *_ptr = jesd_csr_dev_syncn[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::write_signal_input_samples_delay(const char *data) {
- uint32_t *_ptr = (uint32_t *)data;
- bool retval = true;
- uint32_t sdp_data;
- uint32_t min_sample_delay = 0;
- uint32_t max_sample_delay = 4095;
- uint32_t sample_delay;
- string regname;
- for (uint i=0; i< C_S_pn; i++) {
- sample_delay = *_ptr;
- if ((sample_delay < min_sample_delay) || (sample_delay > max_sample_delay)) {
- LOG_F(ERROR, "signal_input_sample_delay not in range<%d:%d>", min_sample_delay, max_sample_delay);
- retval = false;
- } else {
- regname = "mm/0/REG_DP_SHIFTRAM/" + to_string(i) + "/shift";
- sdp_data = sample_delay;
- retval = Write(regname, &sdp_data);
- _ptr++;
- }
- }
- return retval;
-}
-
-bool Periph_fpga::read_signal_input_mean(char *data, int format, int mode) {
+bool Periph_fpga::read_jesd204b_rx_err0(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
- uint32_t sdp_data[2];
- memset(sdp_data, 0, sizeof(sdp_data));
+ uint32_t sdp_data;
string regname;
- int64_t mean_sum;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/REG_ADUH_MONITOR/" + to_string(i) + "/mean_sum";
- retval = Read(regname, sdp_data);
- mean_sum = (int64_t)(((int64_t)sdp_data[1] << 32) + sdp_data[0]);
- signal_input_mean[i] = (double)mean_sum / C_N_CLK_PER_PPS;
+ regname = "mm/0/JESD204B/" + to_string(i) + "/rx_err0";
+ retval = Read(regname, &sdp_data);
+ jesd_rx_err0[i] = (uint32_t)sdp_data;
}
}
- double *_ptr = (double *)data;
+ uint32_t *_ptr = (uint32_t *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = signal_input_mean[i];
+ *_ptr = jesd_rx_err0[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::read_signal_input_rms(char *data, int format, int mode) {
+bool Periph_fpga::read_jesd204b_rx_err1(char *data, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
- uint32_t sdp_data[2];
- memset(sdp_data, 0, sizeof(sdp_data));
+ uint32_t sdp_data;
string regname;
- int64_t power_sum;
for (uint i=0; i< C_S_pn; i++) {
- regname = "mm/0/REG_ADUH_MONITOR/" + to_string(i) + "/power_sum";
- retval = Read(regname, sdp_data);
- power_sum = (int64_t)(((int64_t)sdp_data[1] << 32) + sdp_data[0]);
- signal_input_rms[i] = sqrt((double)power_sum / C_N_CLK_PER_PPS);
+ regname = "mm/0/JESD204B/" + to_string(i) + "/rx_err1";
+ retval = Read(regname, &sdp_data);
+ jesd_rx_err1[i] = (uint32_t)sdp_data;
}
}
- double *_ptr = (double *)data;
+ uint32_t *_ptr = (uint32_t *)data;
for (uint i=0; i< C_S_pn; i++) {
- *_ptr = signal_input_rms[i];
+ *_ptr = jesd_rx_err1[i];
_ptr++;
}
return retval;
}
-bool Periph_fpga::read_signal_input_data_buffer(char *data, int format) {
- bool retval = true;
- uint32_t sdp_data[C_V_si_db];
- string regname;
- int16_t *_ptr = (int16_t *)data;
- for (uint i=0; i< C_S_pn; i++) {
- memset(sdp_data, 0, sizeof(sdp_data));
- regname = "mm/0/RAM_DIAG_DATA_BUFFER_BSN/" + to_string(i) + "/data";
- retval &= Read(regname, sdp_data);
- for (uint j=0; j< C_V_si_db; j++) {
- *_ptr = (int16_t)((sdp_data[j] & 0x3FFF) << 2) / 4;
- _ptr++;
- }
- }
- return retval;
-}
-
bool Periph_fpga::write_subband_weights(const char *data) {
uint32_t *_ptr = (uint32_t *)data;
bool retval = true;
diff --git a/src/periph/fpga.h b/src/periph/fpga.h
index 91af78ba1b4aef36d1bbebf8f3ff01fafc919b6b..2a1f5d1786a44915269f681648cb651d218736fe 100644
--- a/src/periph/fpga.h
+++ b/src/periph/fpga.h
@@ -62,10 +62,12 @@ private:
bool signal_input_sync_timeout;
int64_t signal_input_bsn;
- int64_t xst_input_bsn_at_sync;
- int64_t xst_output_sync_bsn;
int32_t signal_input_nof_packets;
int32_t signal_input_nof_samples;
+ double signal_input_mean[C_S_pn];
+ double signal_input_rms[C_S_pn];
+ int64_t xst_input_bsn_at_sync;
+ int64_t xst_output_sync_bsn;
int32_t sst_offload_nof_packets;
int32_t sst_offload_nof_valid;
int32_t bst_offload_nof_packets[C_N_beamsets_sdp];
@@ -79,10 +81,8 @@ private:
uint32_t jesd_csr_dev_syncn[C_S_pn];
uint32_t jesd_rx_err0[C_S_pn];
uint32_t jesd_rx_err1[C_S_pn];
- bool xst_processing_enable;
+ bool xst_processing_enable;
- double signal_input_mean[C_S_pn];
- double signal_input_rms[C_S_pn];
uint32_t pps_offset_cnt; // used by read_time_since_last_pps()
uint32_t pps_expected_cnt;
@@ -189,20 +189,20 @@ private:
bool write_wg_frequency(const char *data);
bool read_wg_frequency(char *data, int format);
+ bool write_signal_input_samples_delay(const char *data);
bool read_signal_input_sync_timeout(char *data, int format, int mode);
bool read_signal_input_bsn(char *data, int format, int mode);
bool read_signal_input_nof_packets(char *data, int format, int mode);
bool read_signal_input_nof_samples(char *data, int format, int mode);
+ bool read_signal_input_mean(char *data, int format, int mode);
+ bool read_signal_input_rms(char *data, int format, int mode);
+ bool read_signal_input_data_buffer(char *data, int format);
bool read_jesd204b_csr_rbd_count(char *data, int format, int mode);
bool read_jesd204b_csr_dev_syncn(char *data, int format, int mode);
bool read_jesd204b_rx_err0(char *data, int format, int mode);
bool read_jesd204b_rx_err1(char *data, int format, int mode);
- bool write_signal_input_samples_delay(const char *data);
- bool read_signal_input_mean(char *data, int format, int mode);
- bool read_signal_input_rms(char *data, int format, int mode);
- bool read_signal_input_data_buffer(char *data, int format);
bool write_subband_weights(const char *data);
bool read_beamlet_subband_select(char *data, int format);