diff --git a/src/board.cpp b/src/board.cpp
index 19cf25b6eeadc5495f64a6830650746fecea5418..5a449356201e7a42ba8a69d1bf3508a6e145b11f 100644
--- a/src/board.cpp
+++ b/src/board.cpp
@@ -93,12 +93,6 @@ vector<int> Board::get_nodes(void)
return nodes;
}
-CPointMap * Board::get_RegisterMap(int node)
-{
- auto n = select_node(node);
- return n->get_RegisterMap();
-}
-
bool Board::monitor(TermOutput& termout)
{
// cout << "board_monitor start" << endl;
diff --git a/src/board.h b/src/board.h
index f9b8648e534ac0b49b485dec97ddb6c7773cb9bf..e8caec456fcb9b02ad252da906b5b2e4e1952611 100644
--- a/src/board.h
+++ b/src/board.h
@@ -66,7 +66,6 @@ public:
std::vector<int> unb_pn__to__nodes(std::vector<int> unbs, std::vector<int> pns);
uint ipaddr_to_id(const std::string ipaddr);
- CPointMap * get_RegisterMap(int node);
std::string string_node_id(int node);
diff --git a/src/constants.h b/src/constants.h
index cf60b6a4006f107d1970bd643c4b4958640d92e1..fbc39cc04cb0bd3581a00ffd7807693b4fc9ebf6 100644
--- a/src/constants.h
+++ b/src/constants.h
@@ -47,5 +47,10 @@
#define C_N_beamsets 2
#define C_N_step 1
#define C_N_crosslets_max 7
+#define C_N_scrap 512 // Number of 32 bit words in FPGA scrap memory.
+#define C_N_pol 2 // Number of antenna polarizations, X and Y.
+#define C_A_pn 6 // Number of dual polarization antennas per Processing Node (PN) FPGA.
+#define C_N_beamlets 976 // Number of beamlets per antenna band 488, 976
+
#endif
diff --git a/src/fpga.cpp b/src/fpga.cpp
index 65c122ad21f89037d614d7791d78410922b550b4..6bbaae2cf874d494bec4e3bc0f200607dd0f58fd 100644
--- a/src/fpga.cpp
+++ b/src/fpga.cpp
@@ -58,7 +58,7 @@ Fpga::Fpga(list<class Node*>& nodelist)
pointMap->add_register("FPGA_mask_RW", "fpga/enable_mask", nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_status_R", "fpga/status", nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_temp_R", "fpga/temp", nodes.size(), 1, "RO", REG_FORMAT_DOUBLE);
- pointMap->add_register("FPGA_version_R", "fpga/name", nodes.size(), 1, "RO", REG_FORMAT_STRING);
+ // pointMap->add_register("FPGA_version_R", "fpga/name", nodes.size(), 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_firmware_version_R", "fpga/firmware_version", nodes.size(), 1, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_hardware_version_R", "fpga/hardware_version", nodes.size(), 1, "RO", REG_FORMAT_STRING);
@@ -128,8 +128,8 @@ Fpga::Fpga(list<class Node*>& nodelist)
pointMap->add_register("FPGA_jesd204b_csr_rbd_count_R", "fpga/jesd204b_csr_rbd_count", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_jesd204b_csr_dev_syncn_R", "fpga/jesd204b_csr_dev_syncn", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_jesd204b_rx_err0_R", "fpga/jesd204b_csr_rx_err0", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_jesd204b_rx_err1_R", "fpga/jesd204b_csr_rx_err1", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
+ pointMap->add_register("FPGA_jesd204b_rx_err0_R", "fpga/jesd204b_rx_err0", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
+ pointMap->add_register("FPGA_jesd204b_rx_err1_R", "fpga/jesd204b_rx_err1", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_signal_input_samples_delay_R", "fpga/signal_input_samples_delay", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_signal_input_samples_delay_RW", "fpga/signal_input_samples_delay", nodes.size(), C_S_pn, "RW", REG_FORMAT_UINT32);
@@ -137,37 +137,11 @@ Fpga::Fpga(list<class Node*>& nodelist)
pointMap->add_register("FPGA_subband_weights_R", "fpga/subband_weights", nodes.size(), C_S_pn*C_N_sub, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_subband_weights_RW", "fpga/subband_weights", nodes.size(), C_S_pn*C_N_sub, "RW", REG_FORMAT_UINT32);
- uint32_t scrap_span = 0;
- uint32_t scrap_span_next = 0;
- uint32_t scrap_span_prev = 0;
- for (uint idx=0; idx<nodes.size(); idx++) {
- auto node = select_node(nodes[idx]);
- CPointMap *regmap = node->get_RegisterMap();
- scrap_span_next = regmap->getDataSize("fpga/scrap");
- if (scrap_span_next > scrap_span_prev) {
- scrap_span = scrap_span_next;
- }
- scrap_span_prev = scrap_span_next;
- }
- cout << "scrap_span=" << scrap_span << endl;
- pointMap->add_register("FPGA_scrap_R", "fpga/scrap", nodes.size(), scrap_span, "RO", REG_FORMAT_UINT32);
- pointMap->add_register("FPGA_scrap_RW", "fpga/scrap", nodes.size(), scrap_span, "RW", REG_FORMAT_UINT32);
+ pointMap->add_register("FPGA_scrap_R", "fpga/scrap", nodes.size(), C_N_scrap, "RO", REG_FORMAT_UINT32);
+ pointMap->add_register("FPGA_scrap_RW", "fpga/scrap", nodes.size(), C_N_scrap, "RW", REG_FORMAT_UINT32);
- uint32_t weights_span = 0;
- uint32_t weights_span_next = 0;
- uint32_t weights_span_prev = 0;
- for (uint idx=0; idx<nodes.size(); idx++) {
- auto node = select_node(nodes[idx]);
- CPointMap *regmap = node->get_RegisterMap();
- weights_span_next = regmap->getDataSize("fpga/weights");
- if (weights_span_next > weights_span_prev) {
- weights_span = weights_span_next;
- }
- weights_span_prev = weights_span_next;
- }
- cout << "weights_span=" << weights_span << endl;
- pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), weights_span, "RO", REG_FORMAT_INT16);
- pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), weights_span, "RW", REG_FORMAT_INT16);
+ pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), C_S_pn*C_N_beamlets, "RO", REG_FORMAT_INT16);
+ pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), C_S_pn*C_N_beamlets, "RW", REG_FORMAT_INT16);
}
Fpga::~Fpga()
@@ -242,6 +216,7 @@ bool Fpga::point(TermOutput& termout, const char cmd, const string addr,
}
int format = pointMap->getFormat(addr);
+ int nof_values = pointMap->getDataSize(addr);
vector<int> nodes = get_all_nodes();
@@ -251,7 +226,7 @@ bool Fpga::point(TermOutput& termout, const char cmd, const string addr,
retval = true;
}
else if (cmd == 'W') {
- if (nvalues < (int)pointMap->getDataSize(addr)) {
+ if (nvalues < nof_values) {
return false;
}
retval = true;
@@ -263,13 +238,6 @@ bool Fpga::point(TermOutput& termout, const char cmd, const string addr,
auto node = select_node(nodes[idx]);
// if (node->getEnabled() == false) { continue; }
- CPointMap *regmap = node->get_RegisterMap();
- int span = regmap->getDataSize(relative_addr);
-
- int nof_values = nvalues;
- if (nvalues < 0 || nvalues > span) {
- nof_values = span;
- }
ret = false;
try {
diff --git a/src/node.cpp b/src/node.cpp
index f2dadc60ad4808843ffed6acd37d6f05ae13394e..26d4bc173b7e121a5c684931a0175715bc8e52eb 100644
--- a/src/node.cpp
+++ b/src/node.cpp
@@ -142,42 +142,7 @@ void Node::worker()
// cout << " r.format=" << r.datatype << endl;
// cout << " p.cmd=" << p->cmdId << endl;
- int sz = 0;
- switch (r.datatype) {
- case REG_FORMAT_FLOAT: {
- sz = sizeof(float);
- } break;
- case REG_FORMAT_DOUBLE: {
- sz = sizeof(double);
- } break;
- case REG_FORMAT_INT64: {
- sz = sizeof(int64_t);
- } break;
- case REG_FORMAT_UINT64: {
- sz = sizeof(uint64_t);
- } break;
- case REG_FORMAT_INT32: {
- sz = sizeof(int32_t);
- } break;
- case REG_FORMAT_UINT32: {
- sz = sizeof(uint32_t);
- } break;
- case REG_FORMAT_INT16: {
- sz = sizeof(int16_t);
- } break;
- case REG_FORMAT_UINT16: {
- sz = sizeof(uint16_t);
- } break;
- case REG_FORMAT_STRING: {
- sz = sizeof(char) * SIZE1STRING;
- } break;
- case REG_FORMAT_BOOLEAN: {
- sz = sizeof(bool);
- } break;
- default: {
- // cout << "node-r177, Not supported datatype (" << r.datatype << ")" << endl;
- } break;
- }
+ int sz = reg_format_size_in_bytes(r.datatype);
memcpy((void *)r.val, (void *)termout.val, termout.nof_vals * sz);
@@ -263,12 +228,6 @@ bool Node::monitor(TermOutput& termout) {
return true;
}
-
-CPointMap * Node::get_RegisterMap(void)
-{
- return periph_fpga->getRegisterMap();
-}
-
CMMap * Node::get_MMap(void)
{
return periph_fpga->getMMap();
@@ -333,43 +292,7 @@ bool Node::exec_reply(TermOutput& termout)
//cout << "no retval" << endl;
throw runtime_error("no retval");
}
- int sz = 0;
-
- switch (r->datatype) {
- case REG_FORMAT_DOUBLE: {
- sz = sizeof(double);
- } break;
- case REG_FORMAT_FLOAT: {
- sz = sizeof(float);
- } break;
- case REG_FORMAT_INT64: {
- sz = sizeof(int64_t);
- } break;
- case REG_FORMAT_UINT64: {
- sz = sizeof(uint64_t);
- } break;
- case REG_FORMAT_INT32: {
- sz = sizeof(int32_t);
- } break;
- case REG_FORMAT_UINT32: {
- sz = sizeof(uint32_t);
- } break;
- case REG_FORMAT_INT16: {
- sz = sizeof(int16_t);
- } break;
- case REG_FORMAT_UINT16: {
- sz = sizeof(uint16_t);
- } break;
- case REG_FORMAT_BOOLEAN: {
- sz = sizeof(bool);
- } break;
- case REG_FORMAT_STRING: {
- sz = sizeof(char) * SIZE1STRING;
- } break;
- default: {
- // cout << "node-r400, Not supported datatype (" << r->datatype << ")" << endl;
- } break;
- }
+ int sz = reg_format_size_in_bytes(r->datatype);
memcpy((void *)termout.val, (void *)r->val, r->nof_vals * sz);
return r->retval;
}
diff --git a/src/node.h b/src/node.h
index dabb5799e569f53df09e4e0ca749193e430ffca5..52ce52b8b364a2bf0bff15f8a5fce39ffc4bc678 100644
--- a/src/node.h
+++ b/src/node.h
@@ -101,7 +101,6 @@ class Node {
const int nvalues, const int format);
bool exec_reply(TermOutput& t);
- CPointMap * get_RegisterMap(void);
CMMap * get_MMap(void);
};
diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index 1d354e9c5f15867047340cb911405e362b2b5d08..e49bed6b40e68204c6a78da092ec0d31bdae98fb 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -86,82 +86,6 @@ Periph_fpga::Periph_fpga(string ipaddr, string expected_design_name, uint expect
mmap = new CMMap();
}
- registerMap = new CPointMap();
- registerMap->add_register("fpga/system", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/name", "-", 1, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/stamps", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/note", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/firmware_version", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/hardware_version", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/temp", "-", 1, 1, "RO", REG_FORMAT_DOUBLE);
- registerMap->add_register("fpga/status", "-", 1, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/enable_mask", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/rbf", "-", 0, 1, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/flash_init", "-", 0, 1, "WO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/flash_erase", "-", 0, 1, "WO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/flash_pages", "-", 0, 1, "WO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/flash_page", "-", 0, 1, "WO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/flash_prot", "-", 0, 1, "WO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/epcs_wait_busy", "-", 0, 1, "RO", REG_FORMAT_STRING);
- registerMap->add_register("fpga/epcs_mmdp_data", "-", 0, 1, "WO", REG_FORMAT_STRING);
-
- uint32_t scrap_span = mmap->getSpan("mm/0/RAM_SCRAP/0/data");
- registerMap->add_register("fpga/scrap", "-", 1, scrap_span, "RW", REG_FORMAT_UINT32);
-
- uint32_t weights_span = (187392 / 16); // = 11712
- registerMap->add_register("fpga/weights", "-", 1, weights_span, "RW", REG_FORMAT_INT16);
-
- registerMap->add_register("fpga/processing_enable", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/sst_offload_weighted_subbands", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/sst_offload_enable", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/sst_offload_hdr_eth_destination_mac", "-", 1, 1, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/sst_offload_hdr_ip_destination_address", "-", 1, 1, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/sst_offload_hdr_udp_destination_port", "-", 1, 1, "RW", REG_FORMAT_UINT16);
-
- registerMap->add_register("fpga/bst_offload_enable", "-", 1, 2, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/bst_offload_hdr_eth_destination_mac", "-", 1, 2, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/bst_offload_hdr_ip_destination_address", "-", 1, 2, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/bst_offload_hdr_udp_destination_port", "-", 1, 2, "RW", REG_FORMAT_UINT16);
- registerMap->add_register("fpga/bst_offload_nof_beamlets_per_packet", "-", 1, 2, "RW", REG_FORMAT_UINT32);
-
- registerMap->add_register("fpga/xst_subband_select", "-", 1, 1+C_N_crosslets_max, "RW", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/xst_integration_interval", "-", 1, 1, "RW", REG_FORMAT_DOUBLE);
- registerMap->add_register("fpga/xst_processing_enable", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/xst_offload_enable", "-", 1, 1, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/xst_offload_hdr_eth_destination_mac", "-", 1, 1, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/xst_offload_hdr_ip_destination_address", "-", 1, 1, "RW", REG_FORMAT_STRING);
- registerMap->add_register("fpga/xst_offload_hdr_udp_destination_port", "-", 1, 1, "RW", REG_FORMAT_UINT16);
-
- registerMap->add_register("fpga/sdp_info_station_id", "-", 1, 1, "RW", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_observation_id", "-", 1, 1, "RW", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_nyquist_sampling_zone_index", "-", 1, 1, "RW", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_antenna_band_index", "-", 1, 1, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_f_adc", "-", 1, 1, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_fsub_type", "-", 1, 1, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/sdp_info_block_period", "-", 1, 1, "RO", REG_FORMAT_UINT32);
-
- registerMap->add_register("fpga/wg_enable", "-", 1, 12, "RW", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/wg_amplitude", "-", 1, 12, "RW", REG_FORMAT_DOUBLE);
- registerMap->add_register("fpga/wg_phase", "-", 1, 12, "RW", REG_FORMAT_DOUBLE);
- registerMap->add_register("fpga/wg_frequency", "-", 1, 12, "RW", REG_FORMAT_DOUBLE);
-
- registerMap->add_register("fpga/bsn_monitor_input_sync_timeout", "-", 1, 1, "RO", REG_FORMAT_BOOLEAN);
- registerMap->add_register("fpga/bsn_monitor_input_bsn", "-", 1, 1, "RO", REG_FORMAT_INT64);
- registerMap->add_register("fpga/bsn_monitor_input_nof_packets", "-", 1, 1, "RO", REG_FORMAT_INT32);
- registerMap->add_register("fpga/bsn_monitor_input_nof_valid", "-", 1, 1, "RO", REG_FORMAT_INT32);
- registerMap->add_register("fpga/bsn_monitor_input_nof_err", "-", 1, 1, "RO", REG_FORMAT_INT32);
-
- registerMap->add_register("fpga/jesd204b_csr_rbd_count", "-", 1, 12, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/jesd204b_csr_dev_syncn", "-", 1, 12, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/jesd204b_csr_rx_err0", "-", 1, 12, "RO", REG_FORMAT_UINT32);
- registerMap->add_register("fpga/jesd204b_csr_rx_err1", "-", 1, 12, "RO", REG_FORMAT_UINT32);
-
- registerMap->add_register("fpga/signal_input_samples_delay", "-", 1, 12, "RW", REG_FORMAT_UINT32);
-
- registerMap->add_register("fpga/subband_weights", "-", 1, 12*512, "RW", REG_FORMAT_UINT32);
-
- registerMap->print_screen();
-
// Test FPGA by reading system info:
try {
TermOutput termout;
@@ -170,11 +94,6 @@ Periph_fpga::Periph_fpga(string ipaddr, string expected_design_name, uint expect
cerr << "Test Periph_fpga::Periph_fpga:read_system_info(): " << e.what() << endl;
}
-// rbf_wf.open ("/tmp/rbf.dat", ofstream::out | ofstream::binary );
-// if (!rbf_wf) {
-// cerr << "Cannot open file!" << endl;
-// exit(-1);
-// }
Flash_fact_sector_start = 0;
Flash_fact_sector_end = 159;
Flash_user_sector_start = 160;
@@ -200,7 +119,6 @@ Periph_fpga::~Periph_fpga()
// rbf_wf.close();
if (ucp != NULL) delete ucp;
if (mmap != NULL) delete mmap;
- if (registerMap != NULL) delete registerMap;
}
bool Periph_fpga::Read(const string addr_str, uint32_t *data_ptr, bool use_mask_shift=true)
@@ -356,7 +274,7 @@ bool Periph_fpga::read_system_info(TermOutput& termout)
// my_expected_design_name.c_str(), my_expected_firmware_version);
my_current_status = "offline";
- registerMap->setAllPermission_NA();
+ // registerMap->setAllPermission_NA();
}
return retval;
}
@@ -388,7 +306,7 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
retval = read_system_info(termout);
}
else if (addr == "fpga/name") {
- termout.nof_vals = my_current_design_name.size();
+ termout.nof_vals = 1; //my_current_design_name.size();
termout.datatype = format;
strcpy(termout.val, my_current_design_name.c_str());
retval = true;
@@ -530,11 +448,11 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
else if (addr == "fpga/jesd204b_csr_dev_syncn") {
retval = read_jesd204b_csr_dev_syncn(termout, format, R_MEM);
}
- else if (addr == "fpga/jesd204b_csr_rx_err0") {
- retval = read_jesd204b_csr_rx_err0(termout, format, R_MEM);
+ else if (addr == "fpga/jesd204b_rx_err0") {
+ retval = read_jesd204b_rx_err0(termout, format, R_MEM);
}
- else if (addr == "fpga/jesd204b_csr_rx_err0") {
- retval = read_jesd204b_csr_rx_err1(termout, format, R_MEM);
+ else if (addr == "fpga/jesd204b_rx_err1") {
+ retval = read_jesd204b_rx_err1(termout, format, R_MEM);
}
else if (addr == "fpga/signal_input_samples_delay") {
retval = read_signal_input_samples_delay(termout, format);
@@ -707,8 +625,8 @@ bool Periph_fpga::monitor(TermOutput& termout)
read_bsn_monitor_input_nof_err(termout, REG_FORMAT_INT32, R_UCP);
read_jesd204b_csr_rbd_count(termout, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_csr_dev_syncn(termout, REG_FORMAT_UINT32, R_UCP);
- read_jesd204b_csr_rx_err0(termout, REG_FORMAT_UINT32, R_UCP);
- read_jesd204b_csr_rx_err1(termout, REG_FORMAT_UINT32, R_UCP);
+ read_jesd204b_rx_err0(termout, REG_FORMAT_UINT32, R_UCP);
+ read_jesd204b_rx_err1(termout, REG_FORMAT_UINT32, R_UCP);
termout.clear();
tictoc.toc();
@@ -985,7 +903,7 @@ bool Periph_fpga::read_fpga_weights(TermOutput& termout, int format)
*ptr++ = (int16_t)(ds >> 16);
}
}
- termout.nof_vals = registerMap->getDataSize("fpga/weights_R");
+ termout.nof_vals = mmap->getSpan("mm/0/RAM_BF_WEIGHTS/0/data");
delete[] data_scrap;
termout.datatype = format;
return retval;
@@ -995,7 +913,7 @@ bool Periph_fpga::write_fpga_weights(const uint32_t *data)
{
bool retval = false;
uint32_t nvalues_scrap = mmap->getSpan("mm/0/RAM_SCRAP/0/data");
- uint32_t nvalues = registerMap->getDataSize("fpga/weights_R");
+ uint32_t nvalues = mmap->getSpan("mm/0/RAM_BF_WEIGHTS/0/data");
uint nblocks = 48; // 11712/244=48
uint32_t *data_scrap = new uint32_t[nvalues_scrap];
@@ -1208,7 +1126,7 @@ bool Periph_fpga::read_bst_offload_enable(TermOutput& termout, int format)
*_ptr = select;
_ptr++;
}
- termout.nof_vals = 2;
+ termout.nof_vals = C_N_beamsets;
termout.datatype = format;
return retval;
}
@@ -2240,7 +2158,7 @@ bool Periph_fpga::read_jesd204b_csr_dev_syncn(TermOutput& termout, int format, i
return retval;
}
-bool Periph_fpga::read_jesd204b_csr_rx_err0(TermOutput& termout, int format, int mode) {
+bool Periph_fpga::read_jesd204b_rx_err0(TermOutput& termout, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
uint32_t data[20];
@@ -2263,7 +2181,7 @@ bool Periph_fpga::read_jesd204b_csr_rx_err0(TermOutput& termout, int format, int
return retval;
}
-bool Periph_fpga::read_jesd204b_csr_rx_err1(TermOutput& termout, int format, int mode) {
+bool Periph_fpga::read_jesd204b_rx_err1(TermOutput& termout, int format, int mode) {
bool retval = true;
if (mode == R_UCP) {
uint32_t data[20];
diff --git a/src/periph/fpga.h b/src/periph/fpga.h
index 59746dc8f8e7a2e0523bcf9033309c171a364d79..b66d47d27acfbb8a7a2d15a32968330ecc21c762 100644
--- a/src/periph/fpga.h
+++ b/src/periph/fpga.h
@@ -46,7 +46,6 @@ private:
Tictoc tictoc; // used to get some timing information
UCP *ucp;
CMMap *mmap;
- CPointMap *registerMap;
bool Enabled;
std::string my_expected_design_name;
@@ -171,8 +170,8 @@ private:
bool read_jesd204b_csr_rbd_count(TermOutput& termout, int format, int mode);
bool read_jesd204b_csr_dev_syncn(TermOutput& termout, int format, int mode);
- bool read_jesd204b_csr_rx_err0(TermOutput& termout, int format, int mode);
- bool read_jesd204b_csr_rx_err1(TermOutput& termout, int format, int mode);
+ bool read_jesd204b_rx_err0(TermOutput& termout, int format, int mode);
+ bool read_jesd204b_rx_err1(TermOutput& termout, int format, int mode);
bool write_signal_input_samples_delay(uint32_t *data);
bool read_signal_input_samples_delay(TermOutput& termout, int format);
@@ -197,9 +196,7 @@ public:
char *data, const uint nvalues, const int format);
bool monitor(TermOutput& termout);
- CPointMap* getRegisterMap(void) { return registerMap; };
CMMap* getMMap(void) { return mmap; };
- void print_regmap(std::ostringstream& strs, std::string prefix) { registerMap->print(strs, prefix); };
bool getEnabled(void) { return Enabled; }
};
diff --git a/src/registers.cpp b/src/registers.cpp
index ddcf7d7ffe69f209d9858ba2a9c4298ff9ee3395..51b266f5dd31a27234cbb2f1f477a37afb429b2c 100644
--- a/src/registers.cpp
+++ b/src/registers.cpp
@@ -34,6 +34,54 @@
using namespace std;
+
+int32_t reg_format_size_in_bytes(int32_t type) {
+ int32_t sz = 0;
+ switch (type) {
+ case REG_FORMAT_FLOAT: {
+ sz = sizeof(float);
+ } break;
+ case REG_FORMAT_DOUBLE: {
+ sz = sizeof(double);
+ } break;
+ case REG_FORMAT_INT64: {
+ sz = sizeof(int64_t);
+ } break;
+ case REG_FORMAT_UINT64: {
+ sz = sizeof(uint64_t);
+ } break;
+ case REG_FORMAT_INT32: {
+ sz = sizeof(int32_t);
+ } break;
+ case REG_FORMAT_UINT32: {
+ sz = sizeof(uint32_t);
+ } break;
+ case REG_FORMAT_INT16: {
+ sz = sizeof(int16_t);
+ } break;
+ case REG_FORMAT_UINT16: {
+ sz = sizeof(uint16_t);
+ } break;
+ case REG_FORMAT_INT8: {
+ sz = sizeof(int8_t);
+ } break;
+ case REG_FORMAT_UINT8: {
+ sz = sizeof(uint8_t);
+ } break;
+ case REG_FORMAT_STRING: {
+ sz = sizeof(char) * SIZE1STRING;
+ } break;
+ case REG_FORMAT_BOOLEAN: {
+ sz = sizeof(bool);
+ } break;
+ default: {
+ cout << "size_in_bytes, Not supported datatype (" << type << ")" << endl;
+ } break;
+ }
+ return sz;
+}
+
+
//
// CMMap used for holding fpga mm register information
//
diff --git a/src/registers.h b/src/registers.h
index fb9d9a3a44a69b2d1920a38441f8c3b23a961dae..f9f8c818c760029a9eaea543b63e97f8701dc0c1 100644
--- a/src/registers.h
+++ b/src/registers.h
@@ -33,6 +33,8 @@
#include <map>
#include <vector>
+#define SIZE1STRING 100
+
#define REG_ADDR_ROM_SYSTEM (0x10000)
#define REG_ADDR_ROM_SYSTEM_SPAN (8192)
@@ -50,6 +52,9 @@
#define REG_FORMAT_DOUBLE 11
#define REG_FORMAT_STRING 12
+int32_t reg_format_size_in_bytes(int32_t type);
+
+
class CMMap {
private:
diff --git a/src/tools/util.h b/src/tools/util.h
index 01650fd8ebdd92337b92ee8120248021254e7fa4..de9c2f1d84cbb9c59f3f84eab45d15f14dbbb9cf 100644
--- a/src/tools/util.h
+++ b/src/tools/util.h
@@ -54,7 +54,7 @@ class TermOutput {
public:
#define SIZE400K 400000
-#define SIZE1STRING 100
+
char val[SIZE400K];
unsigned int nof_vals;